专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5870337A Flash-erasable semiconductor memory device having an improved reliability 失效
标题翻译：闪存可擦除半导体存储器件具有改进的可靠性
公开(公告)号：US5870337A
公开(公告)日：1999-02-09
申请号：US986575
申请日：1997-12-05
申请人： Takao Akaogi , Yasushige Ogawa , Tatsuya Kajita , Hisayoshi Watanabe , Minoru Yamashita
发明人： Takao Akaogi , Yasushige Ogawa , Tatsuya Kajita , Hisayoshi Watanabe , Minoru Yamashita
IPC分类号： G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/00 , H01L21/8247 , H01L27/105 , H01L27/115 , G11C16/06
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device has a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on the floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.
摘要翻译：闪存可擦除半导体存储器件具有存储单元阵列，其包括多个存储单元晶体管，每个存储单元晶体管具有用于存储信息的绝缘浮动栅极和设置在浮置栅极上的控制电极，其中闪存可擦除半导体存储器件包括写入控制电路提供写入控制信号时，写入信息。写入控制电路产生控制信号，使得漏极控制信号的前沿出现在栅极控制信号的前沿之后。此外，栅极控制电路关闭栅极控制信号，使得栅极控制信号的后沿出现在漏极控制信号的后沿之后。

2. 发明授权

US5761127A Flash-erasable semiconductor memory device having an improved reliability 失效
公开(公告)号：US5761127A
公开(公告)日：1998-06-02
申请号：US978976
申请日：1992-11-20
申请人： Takao Akaogi , Yasushige Ogawa , Tatsuya Kajita , Hisayoshi Watanabe , Minoru Yamashita
发明人： Takao Akaogi , Yasushige Ogawa , Tatsuya Kajita , Hisayoshi Watanabe , Minoru Yamashita
IPC分类号： G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/00 , H01L21/8247 , H01L27/105 , H01L27/115 , G11C16/06
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.

3. 发明授权

US5835408A Flash-erasable semiconductor memory device having an improved reliability 失效
公开(公告)号：US5835408A
公开(公告)日：1998-11-10
申请号：US985714
申请日：1997-12-05
申请人： Takao Akaogi , Yasushige Ogawa , Tatsuya Kajita , Hisayoshi Watanabe , Minoru Yamashita
发明人： Takao Akaogi , Yasushige Ogawa , Tatsuya Kajita , Hisayoshi Watanabe , Minoru Yamashita
IPC分类号： G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/00 , H01L21/8247 , H01L27/105 , H01L27/115 , G11C16/06
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device has a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on the floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.

4. 发明授权

US6014329A Flash-erasable semiconductor memory device having an improved reliability 失效
标题翻译：闪存可擦除半导体存储器件具有改进的可靠性
公开(公告)号：US6014329A
公开(公告)日：2000-01-11
申请号：US986337
申请日：1997-12-05
申请人： Takao Akaogi , Yasushige Ogawa , Tatsuya Kajita , Hisayoshi Watanabe , Minoru Yamashita
发明人： Takao Akaogi , Yasushige Ogawa , Tatsuya Kajita , Hisayoshi Watanabe , Minoru Yamashita
IPC分类号： G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/00 , H01L21/8247 , H01L27/105 , H01L27/115 , G11C16/06
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.
摘要翻译：闪存可擦除半导体存储器件包括存储单元阵列，其包括多个存储单元晶体管，每个存储单元晶体管具有用于存储信息的绝缘浮动栅极和设置在所述浮置栅极上的控制电极，其中闪存可擦除半导体存储器件包括写入控制电路提供写入控制信号时，写入信息。写入控制电路产生控制信号，使得漏极控制信号的前沿出现在栅极控制信号的前沿之后。此外，栅极控制电路关闭栅极控制信号，使得栅极控制信号的后沿出现在漏极控制信号的后沿之后。

5. 发明授权

US5910916A Flash-erasable semiconductor memory device having improved reliability 失效
标题翻译：闪存可擦除半导体存储器件具有改进的可靠性
公开(公告)号：US5910916A
公开(公告)日：1999-06-08
申请号：US986339
申请日：1997-12-05
申请人： Takao Akaogi , Yasushige Ogawa , Tatsuya Kajita , Hisayoshi Watanabe , Minoru Yamashita
发明人： Takao Akaogi , Yasushige Ogawa , Tatsuya Kajita , Hisayoshi Watanabe , Minoru Yamashita
IPC分类号： G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/00 , H01L21/8247 , H01L27/105 , H01L27/115 , G11C16/00
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.
摘要翻译：闪存可擦除半导体存储器件包括存储单元阵列，其包括多个存储单元晶体管，每个存储单元晶体管具有用于存储信息的绝缘浮动栅极和设置在所述浮置栅极上的控制电极，其中闪存可擦除半导体存储器件包括写入控制电路提供写入控制信号时，写入信息。写入控制电路产生控制信号，使得漏极控制信号的前沿出现在栅极控制信号的前沿之后。此外，栅极控制电路关闭栅极控制信号，使得栅极控制信号的后沿出现在漏极控制信号的后沿之后。

6. 发明授权

US5835416A Flash-erasable semiconductor memory device having an improved reliability 失效
公开(公告)号：US5835416A
公开(公告)日：1998-11-10
申请号：US986338
申请日：1997-12-05
申请人： Takao Akaogi , Yasushige Ogawa , Tatsuya Kajita , Hisayoshi Watanabe , Minoru Yamashita
发明人： Takao Akaogi , Yasushige Ogawa , Tatsuya Kajita , Hisayoshi Watanabe , Minoru Yamashita
IPC分类号： G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/00 , H01L21/8247 , H01L27/105 , H01L27/115 , G11C16/00
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.

7. 发明授权

US5590074A Nonvolatile semiconductor memory 失效
公开(公告)号：US5590074A
公开(公告)日：1996-12-31
申请号：US466732
申请日：1995-06-06
申请人： Takao Akaogi , Masanobu Yoshida , Yasushige Ogawa , Yasushi Kasa , Shouichi Kawamura
发明人： Takao Akaogi , Masanobu Yoshida , Yasushige Ogawa , Yasushi Kasa , Shouichi Kawamura
IPC分类号： G11C16/26 , G11C16/30 , G11C29/04 , G11C11/34
CPC分类号： G11C16/30 , G11C16/26 , G11C29/04 , G06F2201/81
摘要： A nonvolatile semiconductor memory employs sense amplifiers, circuits for providing stabilized source voltages, and circuits for realizing high-speed and reliable read and write operations. The semiconductor memory has a matrix of nonvolatile erasable memory cell transistors. The semiconductor memory employs an arrangement for effectively using a plurality of source voltages and applying a verify voltage to sense amplifiers and word lines, a write verify arrangement for detecting an output of the sense amplifiers, an arrangement for comparing an output of the sense amplifiers with a reference value to determine whether or not a written state of the memory cell transistors is acceptable, an arrangement for adjusting an output of the sense amplifiers with use of inverters and transistors in response to a current flowing to the memory cell transistors, to improve a drive speed of the sense amplifiers, an internal source voltage generating arrangement using an n-channel depletion transistor connected to an external source voltage (Vcc), the gate of the transistor being connected to a low source voltage (Vss) to provide an internal source voltage (Vci), a combination of an arrangement for dropping the external source voltage (Vcc) for read to a predetermined value to drive a read circuit in the memory and an arrangement for dropping an external voltage (Vpp) for write, to generate a word line potential for a verify-after-write operation, an arrangement for setting a reference voltage (Vref) as a lower threshold (Vth) allowed for cell transistors (11.sub.00 to 11.sub.22), and comparing the voltage of a data bus (13) with the reference voltage (Vref), to simultaneously carry out an erase-verify operation on all memory cell transistors, and a pre-read arrangement for accessing the next address during a read time of the sense amplifiers, to improve a read speed.

8. 发明授权

US5631597A Negative voltage circuit for a flash memory 失效
标题翻译：闪存的负电压电路
公开(公告)号：US5631597A
公开(公告)日：1997-05-20
申请号：US445103
申请日：1995-05-19
申请人： Takao Akaogi , Hiromi Kawashima , Tetsuji Takeguchi , Ryoji Hagiwara , Yasushi Kasa , Kiyoshi Itano , Yasushige Ogawa , Shouichi Kawamura
发明人： Takao Akaogi , Hiromi Kawashima , Tetsuji Takeguchi , Ryoji Hagiwara , Yasushi Kasa , Kiyoshi Itano , Yasushige Ogawa , Shouichi Kawamura
IPC分类号： G05F3/20 , G11C5/14 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/16 , G11C16/30 , G11C29/00 , H03K3/356 , H03K19/0185 , H03K19/21 , G05F1/10
CPC分类号： G11C29/82 , G05F3/205 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , G11C5/145 , H03K19/018521 , H03K19/215 , H03K3/356147 , H03K3/356165
摘要： A negative-voltage circuit for realizing a flash memory is installed independently and is applied selectively to word lines in response to signals sent from row decoders. Row decoders for specifying word lines need not be installed in the negative voltage circuit. The negative circuit can therefore be reduced in scale.
摘要翻译：独立地安装用于实现闪速存储器的负电压电路，并响应于从行解码器发送的信号而选择性地对字线施加。用于指定字线的行解码器不需要安装在负电压电路中。因此，可以减小负电路的规模。

9. 发明授权

US5519652A Nonvolatile semiconductor memory for positively holding stored data 失效
标题翻译：用于积极保存存储数据的非易失性半导体存储器
公开(公告)号：US5519652A
公开(公告)日：1996-05-21
申请号：US158796
申请日：1993-12-01
申请人： Sinsuke Kumakura , Yasushige Ogawa , Takao Akaogi , Tetsuya Chida
发明人： Sinsuke Kumakura , Yasushige Ogawa , Takao Akaogi , Tetsuya Chida
IPC分类号： G11C17/00 , G11C16/06 , G11C16/26 , G11C16/28 , G11C29/00 , G11C29/06 , G11C29/50 , G11C29/56 , G11C11/34
CPC分类号： G11C29/50016 , G11C16/26 , G11C16/28 , G11C29/50 , G06F2201/81 , G11C16/04 , G11C2029/5006
摘要： A semiconductor memory has a plurality of word lines, a plurality of bit lines, a plurality of memory cells, a differential sense amplifier, and load transistors. Each of the memory cells is a MIS transistor formed at each intersection of the word and bit lines. The threshold voltage of the MIS transistor is externally electrically controllable. The differential sense amplifier senses data stored in a selected memory cell located at an intersection of selected word and bit lines. A control pulse signal is applied to the gates of the load transistors, to bias the bit lines. The pulse width of the control pulse signal is a minimum essential to read data out of the selected memory cell. The control pulse signal controls the switching of the load transistors, to shorten a period during which a stress voltage is continuously applied to the drains of unselected memory cells that are connected to the bit line to which the selected memory cell is connected.
摘要翻译：半导体存储器具有多个字线，多个位线，多个存储单元，差分读出放大器和负载晶体管。每个存储单元是形成在字和位线的每个交叉处的MIS晶体管。 MIS晶体管的阈值电压是外部电可控的。差分读出放大器感测存储在位于选定字和位线的交叉点处的选定存储单元中的数据。控制脉冲信号施加到负载晶体管的栅极，以偏置位线。控制脉冲信号的脉冲宽度是从所选存储单元读出数据所必需的最小值。控制脉冲信号控制负载晶体管的切换，以缩短连续施加到与所选存储单元连接的位线的未选择存储单元的漏极的应力电压的周期。

10. 发明授权

US5770963A Flash memory with improved erasability and its circuitry 失效
标题翻译：闪存具有改进的可擦除性及其电路
公开(公告)号：US5770963A
公开(公告)日：1998-06-23
申请号：US436699
申请日：1995-05-08
申请人： Takao Akaogi , Hiromi Kawashima , Tetsuji Takeguchi , Ryoji Hagiwara , Yasushi Kasa , Kiyoshi Itano , Yasushige Ogawa , Shouichi Kawamura
发明人： Takao Akaogi , Hiromi Kawashima , Tetsuji Takeguchi , Ryoji Hagiwara , Yasushi Kasa , Kiyoshi Itano , Yasushige Ogawa , Shouichi Kawamura
IPC分类号： G05F3/20 , G11C5/14 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/16 , G11C16/30 , G11C29/00 , H03K3/356 , H03K19/0185 , H03K19/21 , H03K5/08
CPC分类号： G11C29/82 , G05F3/205 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , G11C5/145 , H03K19/018521 , H03K19/215 , H03K3/356147 , H03K3/356165
摘要： A flash memory performs channel erasing or source erasing by applying a negative voltage to a control gate. The device includes a voltage restriction device which restricts the negative voltage to be applied to the control gate so that the negative voltage will be a constant value relative to the voltage of the channel or source. Alternatively, two voltage restricting devices restrict the negative voltage applied to the control gate and the voltage to be applied to the source so that the voltages will be a constant value relative to a common reference voltage.
摘要翻译：闪存通过向控制栅极施加负电压来执行信道擦除或源擦除。该装置包括限制施加到控制栅极的负电压的电压限制装置，使得负电压相对于通道或源的电压将是恒定值。或者，两个电压限制装置限制施加到控制栅极的负电压和施加到源极的电压，使得电压相对于公共参考电压将是恒定值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式