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1. 发明申请

US20110143271A1 PATTERN GENERATING METHOD AND PROCESS DETERMINING METHOD 审中-公开
标题翻译：模式生成方法和过程确定方法
公开(公告)号：US20110143271A1
公开(公告)日：2011-06-16
申请号：US12822716
申请日：2010-06-24
申请人： Takeshi KOSHIBA , Hidefumi Mukai , Kazuhito Kobayashi , Takumi Ota
发明人： Takeshi KOSHIBA , Hidefumi Mukai , Kazuhito Kobayashi , Takumi Ota
IPC分类号： G03F7/20
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00
摘要： A pattern generating method includes obtaining an on-substrate pattern by performing a process for forming the on-substrate pattern by simulation or experiment based on a design pattern of the on-substrate pattern formed by an imprint process using a template, employing the design pattern when a comparison result of the design pattern and obtained on-substrate pattern satisfies a predetermined condition, and correcting the design pattern to satisfy the predetermined condition when the comparison result does not satisfy the predetermined condition.
摘要翻译：图案生成方法包括通过基于通过使用模板的压印处理形成的衬底上图案的设计图案通过模拟或实验进行用于形成衬底上图案的处理来获得衬底图案，采用设计图案当设计图案和获得的基板图案的比较结果满足预定条件时，并且当比较结果不满足预定条件时，校正设计图案以满足预定条件。

2. 发明申请

US20120174045A1 ACCEPTANCE DETERMINING METHOD OF BLANK FOR EUV MASK AND MANUFACTURING METHOD OF EUV MASK 有权
标题翻译： EUV掩模防护罩和EUV掩模制造方法的接受度测定方法
公开(公告)号：US20120174045A1
公开(公告)日：2012-07-05
申请号：US13237790
申请日：2011-09-20
申请人： Takeshi KOSHIBA , Hidefumi Mukai , Seiro Miyoshi , Kazunori IIda
发明人： Takeshi KOSHIBA , Hidefumi Mukai , Seiro Miyoshi , Kazunori IIda
IPC分类号： G06F17/50
CPC分类号： G03F1/22 , B82Y10/00 , B82Y40/00 , G03F1/70
摘要： According to one embodiment, an acceptance determining method of a blank for an EUV mask includes evaluating whether or not an integrated circuit device becomes defective, on the basis of information of a defect contained in a blank for an EUV mask and design information of a mask pattern to be formed on the blank. The integrated circuit device is to be manufactured by using the EUV mask. The EUV mask is manufactured by forming the mask pattern on the blank. And the blank is determined to be non-defective in a case that the integrated circuit device is not to be defective.
摘要翻译：根据一个实施例，用于EUV掩模的空白的接受确定方法包括基于包含在EUV掩码的空白中的缺陷的信息和掩模的设计信息来评估集成电路器件是否变得有缺陷图案要在空白上形成。集成电路器件将通过使用EUV掩模来制造。通过在空白上形成掩模图案来制造EUV掩模。在集成电路装置不具有缺陷的情况下，判断为无缺陷。

3. 发明授权

US08423926B2 Acceptance determining method of blank for EUV mask and manufacturing method of EUV mask 有权
标题翻译： EUV掩模的掩模验证方法和EUV掩模的制造方法
公开(公告)号：US08423926B2
公开(公告)日：2013-04-16
申请号：US13237790
申请日：2011-09-20
申请人： Takeshi Koshiba , Hidefumi Mukai , Seiro Miyoshi , Kazunori Iida
发明人： Takeshi Koshiba , Hidefumi Mukai , Seiro Miyoshi , Kazunori Iida
IPC分类号： G06F17/50
CPC分类号： G03F1/22 , B82Y10/00 , B82Y40/00 , G03F1/70
摘要： According to one embodiment, an acceptance determining method of a blank for an EUV mask includes evaluating whether or not an integrated circuit device becomes defective, on the basis of information of a defect contained in a blank for an EUV mask and design information of a mask pattern to be formed on the blank. The integrated circuit device is to be manufactured by using the EUV mask. The EUV mask is manufactured by forming the mask pattern on the blank. And the blank is determined to be non-defective in a case that the integrated circuit device is not to be defective.
摘要翻译：根据一个实施例，用于EUV掩模的空白的接受确定方法包括基于包含在EUV掩码的空白中的缺陷的信息和掩模的设计信息来评估集成电路器件是否变得有缺陷图案要在空白上形成。集成电路器件将通过使用EUV掩模来制造。通过在空白上形成掩模图案来制造EUV掩模。在集成电路装置不具有缺陷的情况下，判断为无缺陷。

4. 发明授权

US08178366B2 Pattern forming method, manufacturing method of semiconductor device, and template manufacturing method 有权
标题翻译：图案形成方法，半导体器件的制造方法和模板制造方法
公开(公告)号：US08178366B2
公开(公告)日：2012-05-15
申请号：US13015351
申请日：2011-01-27
申请人： Seiro Miyoshi , Hidefumi Mukai , Takeshi Koshiba
发明人： Seiro Miyoshi , Hidefumi Mukai , Takeshi Koshiba
IPC分类号： H01L21/66
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00 , Y10S977/887
摘要： In the pattern forming method according to the embodiment, second templates are manufactured by an imprint technology using first templates manufactured by applying a predetermined misalignment distribution for each shot on a first substrate by an exposure apparatus. Then, an upper-layer-side pattern is formed by an imprint technology using a second template in which an inter-layer misalignment amount between a lower-layer-side pattern already formed above a second substrate and the upper-layer-side pattern to be formed above the second substrate becomes equal to or lower than a predetermined reference value.
摘要翻译：在根据实施例的图案形成方法中，通过压印技术制造第二模板，使用通过由曝光装置在第一基板上施加每次拍摄的预定的未对准分布而制造的第一模板。然后，通过使用第二模板的压印技术形成上层侧图案，其中在已经形成在第二基板上的下层侧图案与上层侧图案之间的层间未对准量与形成在第二基板的上方成为规定的基准值以下。

5. 发明申请

US20110012297A1 PATTERN TRANSFER METHOD 审中-公开
标题翻译：图案转移方法
公开(公告)号：US20110012297A1
公开(公告)日：2011-01-20
申请号：US12718778
申请日：2010-03-05
申请人： Ayumi KOBIKI , Takeshi Koshiba , Hidefumi Mukai , Seiro Miyoshi
发明人： Ayumi KOBIKI , Takeshi Koshiba , Hidefumi Mukai , Seiro Miyoshi
IPC分类号： B29C35/08 , B29C39/00
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00
摘要： A pattern transfer method for transferring an uneven pattern onto a resist material is disclosed. The uneven pattern is formed in a template having a through-groove in a predetermined region. The resist material is applied to a substrate. The template is made to come into contact with the resist material. The resist material is filled to concave portion in the uneven pattern. The residual resist material leaked from a gap between the substrate and the template to the outside is sucked through the through-groove in a state where the template is in contact with the resist material. The resist material is made to cure in a state where the template is in contact with the resist material after the suction of the residual resist material. The template is separated from the cured resist material.
摘要翻译：公开了一种用于将不均匀图案转印到抗蚀剂材料上的图案转印方法。不规则图案形成在具有预定区域中的通槽的模板中。将抗蚀剂材料施加到基底上。使模板与抗蚀剂材料接触。抗蚀剂材料以不均匀图案填充到凹部。在模板与抗蚀剂材料接触的状态下，从基板和模板之间的间隙向外部泄漏的残留抗蚀剂材料通过贯通槽进行吸引。抗蚀剂材料在残留抗蚀剂材料的吸附之后，在模板与抗蚀剂材料接触的状态下使其固化。将模板与固化的抗蚀剂材料分离。

6. 发明申请

US20120020158A1 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20120020158A1
公开(公告)日：2012-01-26
申请号：US13187000
申请日：2011-07-20
申请人： Tohru OZAKI , Mitsuhiro Noguchi , Hideaki Maekawa , Hiromitsu Mashita , Takafumi Taguchi , Kazuhito Kobayashi , Hidefumi Mukai , Hiroyuki Nitta
发明人： Tohru OZAKI , Mitsuhiro Noguchi , Hideaki Maekawa , Hiromitsu Mashita , Takafumi Taguchi , Kazuhito Kobayashi , Hidefumi Mukai , Hiroyuki Nitta
IPC分类号： G11C16/04 , H01L21/78
CPC分类号： H01L27/11521
摘要： A memory cell array includes memory strings arranged in a first direction. Word-lines and select gate lines extend in a second direction perpendicular to the first direction. The select gate line also extends in the second direction. The word-lines have a first line width in the first direction and arranged with a first distance therebetween. The select gate line includes a first interconnection in the first direction, the first interconnection having a second line width larger than the first line width, and a second interconnection extending from an end portion of the first interconnection, the second interconnection having a third line width the same as the first line width. A first word-line adjacent to the select gate line is arranged having a second distance to the second interconnection, the second distance being (4N+1) times the first distance (N being an integer of 1 or more).
摘要翻译：存储单元阵列包括沿第一方向布置的存储器串。字线和选择栅极线在垂直于第一方向的第二方向上延伸。选择栅极线也沿第二方向延伸。字线在第一方向上具有第一线宽度并且以它们之间的第一距离布置。选择栅极线包括在第一方向上的第一互连，第一互连具有大于第一线宽的第二线宽，以及从第一互连的端部延伸的第二互连，第二互连具有第三线宽与第一行宽度相同。与选择栅极线相邻的第一字线布置成具有到第二互连的第二距离，第二距离为（4N + 1）倍于第一距离（N为1或更大的整数）。

7. 发明授权

US08440376B2 Exposure determining method, method of manufacturing semiconductor device, and computer program product 有权
标题翻译：曝光确定方法，制造半导体器件的方法和计算机程序产品
公开(公告)号：US08440376B2
公开(公告)日：2013-05-14
申请号：US13007238
申请日：2011-01-14
申请人： Toshiya Kotani , Kazuya Fukuhara , Michiya Takimoto , Hidefumi Mukai , Soichi Inoue
发明人： Toshiya Kotani , Kazuya Fukuhara , Michiya Takimoto , Hidefumi Mukai , Soichi Inoue
IPC分类号： G03F9/00 , G03C5/00
CPC分类号： G03F7/70425 , G03F7/70558
摘要： According to one embodiment, a deviation amount distribution of a two-dimensional shape parameter between a mask pattern formed on a mask and a desired mask pattern is acquired as a mask pattern map. Such that a deviation amount of the two-dimensional shape parameter between a pattern on substrate formed when the mask is subjected to exposure shot to form a pattern on a substrate and a desired pattern on substrate fits within a predetermined range, an exposure is determined for each position in the exposure shot in forming the pattern on substrate based on the mask pattern map.
摘要翻译：根据一个实施例，获取形成在掩模上的掩模图案与期望的掩模图案之间的二维形状参数的偏差量分布作为掩模图案图。使得当在掩模经受曝光拍摄以形成基板上的图案和在基板上形成图案之后形成的基板上的图案之间的二维形状参数的偏移量适合在预定范围内时，确定曝光基于掩模图案图，在基板上形成图案的曝光中的每个位置。

8. 发明授权

US07713833B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07713833B2
公开(公告)日：2010-05-11
申请号：US12557111
申请日：2009-09-10
申请人： Hiromitsu Mashita , Toshiya Kotani , Hidefumi Mukai , Fumiharu Nakajima , Chikaaki Kodama
发明人： Hiromitsu Mashita , Toshiya Kotani , Hidefumi Mukai , Fumiharu Nakajima , Chikaaki Kodama
IPC分类号： H01L21/76
CPC分类号： H01L27/11524 , H01L21/0337 , H01L21/32139
摘要： According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a first film on a target film; forming resist patterns on the first film; processing the first film with the resist patterns to form first patterns including: periodic patterns; and aperiodic patterns; removing the resist patterns; forming a second film over the target film; processing the second film to form second side wall patterns on side walls of the first patterns; removing the periodic patterns; and processing the target film with the aperiodic patterns and the second side wall patterns, thereby forming a target patterns including: periodic target patterns; aperiodic target patterns; and dummy patterns arranged between the periodic target patterns and the aperiodic patterns and arranged periodically with the periodic target patterns.
摘要翻译：根据本发明的一个方面，提供一种制造半导体器件的方法，所述方法包括：在靶膜上形成第一膜; 在第一膜上形成抗蚀剂图案; 用抗蚀剂图案处理第一膜以形成第一图案，包括：周期图案; 和非周期性模式; 去除抗蚀剂图案; 在目标膜上形成第二膜; 处理所述第二膜以在所述第一图案的侧壁上形成第二侧壁图案; 去除周期性模式; 用非周期图案和第二侧壁图案处理目标薄膜，从而形成包括周期性目标图案的目标图案; 非周期目标模式; 以及布置在周期性目标图案和非周期性图案之间的虚拟图案，并且周期性地布置有周期性目标图案。

9. 发明授权

US07941782B2 Pattern layout of integrated circuit 失效
标题翻译：集成电路图案布局
公开(公告)号：US07941782B2
公开(公告)日：2011-05-10
申请号：US11943771
申请日：2007-11-21
申请人： Yasunobu Kai , Kazuo Hatakeyama , Hidefumi Mukai , Hiromitsu Mashita , Koji Hashimoto
发明人： Yasunobu Kai , Kazuo Hatakeyama , Hidefumi Mukai , Hiromitsu Mashita , Koji Hashimoto
IPC分类号： G06F17/50
CPC分类号： H01L27/0207 , G11C5/025 , H01L27/115 , Y10T428/24802
摘要： In a pattern layout which includes a first device pattern having a uniformly repeated pattern group having first lines and first spaces formed parallel to one anther and uniformly arranged with constant width at a constant pitch and a non-uniformly repeated pattern group having first lines and first spaces non-uniformly arranged, and a second device pattern arranged adjacent to the end portion of the non-uniformly repeated pattern group in an arrangement direction thereof and having second lines and second spaces whose widths are larger than the widths of the first lines and first spaces of the non-uniformly repeated pattern group, at least part of the widths of the first lines and the first spaces of the non-uniformly repeated pattern group is made larger than the width of the first line or the width of the first space of the uniformly repeated pattern group.
摘要翻译：在图案布局中，包括具有均匀重复的图案组的第一装置图案，该第一装置图案具有第一线和平行于一个花柱形成的第一间隔，并且以恒定间距均匀地布置，并且具有第一线和第一线的不均匀重复的图案组以及与其非排列方向上的非均匀重复图形组的端部相邻排列的第二装置图案，并且具有第二线和第二空间，第二线和第二空间的宽度大于第一线和第一线的宽度不均匀重复图案组的空间，使不均匀重复图案组的第一线和第一空间的宽度的至少一部分大于第一线的宽度或第一空间的第一空间的宽度均匀重复模式组。

10. 发明申请

US20110177458A1 EXPOSURE DETERMINING METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND COMPUTER PROGRAM PRODUCT 有权
标题翻译：曝光测定方法，制造半导体器件的方法和计算机程序产品
公开(公告)号：US20110177458A1
公开(公告)日：2011-07-21
申请号：US13007238
申请日：2011-01-14
申请人： Toshiya KOTANI , Kazuya Fukuhara , Michiya Takimoto , Hidefumi Mukai , Soichi Inoue
发明人： Toshiya KOTANI , Kazuya Fukuhara , Michiya Takimoto , Hidefumi Mukai , Soichi Inoue
IPC分类号： G03F7/20 , G06F17/50
CPC分类号： G03F7/70425 , G03F7/70558
摘要： According to one embodiment, a deviation amount distribution of a two-dimensional shape parameter between a mask pattern formed on a mask and a desired mask pattern is acquired as a mask pattern map. Such that a deviation amount of the two-dimensional shape parameter between a pattern on substrate formed when the mask is subjected to exposure shot to form a pattern on a substrate and a desired pattern on substrate fits within a predetermined range, an exposure is determined for each position in the exposure shot in forming the pattern on substrate based on the mask pattern map.
摘要翻译：根据一个实施例，获取形成在掩模上的掩模图案与期望的掩模图案之间的二维形状参数的偏差量分布作为掩模图案图。使得当在掩模经受曝光拍摄以形成基板上的图案和在基板上形成图案之后形成的基板上的图案之间的二维形状参数的偏移量适合在预定范围内时，确定曝光基于掩模图案图，在基板上形成图案的曝光中的每个位置。

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