专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07941782B2 Pattern layout of integrated circuit 失效
标题翻译：集成电路图案布局
公开(公告)号：US07941782B2
公开(公告)日：2011-05-10
申请号：US11943771
申请日：2007-11-21
申请人： Yasunobu Kai , Kazuo Hatakeyama , Hidefumi Mukai , Hiromitsu Mashita , Koji Hashimoto
发明人： Yasunobu Kai , Kazuo Hatakeyama , Hidefumi Mukai , Hiromitsu Mashita , Koji Hashimoto
IPC分类号： G06F17/50
CPC分类号： H01L27/0207 , G11C5/025 , H01L27/115 , Y10T428/24802
摘要： In a pattern layout which includes a first device pattern having a uniformly repeated pattern group having first lines and first spaces formed parallel to one anther and uniformly arranged with constant width at a constant pitch and a non-uniformly repeated pattern group having first lines and first spaces non-uniformly arranged, and a second device pattern arranged adjacent to the end portion of the non-uniformly repeated pattern group in an arrangement direction thereof and having second lines and second spaces whose widths are larger than the widths of the first lines and first spaces of the non-uniformly repeated pattern group, at least part of the widths of the first lines and the first spaces of the non-uniformly repeated pattern group is made larger than the width of the first line or the width of the first space of the uniformly repeated pattern group.
摘要翻译：在图案布局中，包括具有均匀重复的图案组的第一装置图案，该第一装置图案具有第一线和平行于一个花柱形成的第一间隔，并且以恒定间距均匀地布置，并且具有第一线和第一线的不均匀重复的图案组以及与其非排列方向上的非均匀重复图形组的端部相邻排列的第二装置图案，并且具有第二线和第二空间，第二线和第二空间的宽度大于第一线和第一线的宽度不均匀重复图案组的空间，使不均匀重复图案组的第一线和第一空间的宽度的至少一部分大于第一线的宽度或第一空间的第一空间的宽度均匀重复模式组。

2. 发明申请

US20080137421A1 PATTERN LAYOUT OF INTEGRATED CIRCUIT 失效
标题翻译：集成电路图案布局
公开(公告)号：US20080137421A1
公开(公告)日：2008-06-12
申请号：US11943771
申请日：2007-11-21
申请人： Yasunobu KAI , Kazuo Hatakeyama , Hidefumi Mukai , Hiromitsu Mashita , Koji Hashimoto
发明人： Yasunobu KAI , Kazuo Hatakeyama , Hidefumi Mukai , Hiromitsu Mashita , Koji Hashimoto
IPC分类号： G11C11/34 , B41M5/00 , G03G13/00
CPC分类号： H01L27/0207 , G11C5/025 , H01L27/115 , Y10T428/24802
摘要： In a pattern layout which includes a first device pattern having a uniformly repeated pattern group having first lines and first spaces formed parallel to one anther and uniformly arranged with constant width at a constant pitch and a non-uniformly repeated pattern group having first lines and first spaces non-uniformly arranged, and a second device pattern arranged adjacent to the end portion of the non-uniformly repeated pattern group in an arrangement direction thereof and having second lines and second spaces whose widths are larger than the widths of the first lines and first spaces of the non-uniformly repeated pattern group, at least part of the widths of the first lines and the first spaces of the non-uniformly repeated pattern group is made larger than the width of the first line or the width of the first space of the uniformly repeated pattern group.
摘要翻译：在图案布局中，包括具有均匀重复的图案组的第一装置图案，该第一装置图案具有第一线和平行于一个花柱形成的第一间隔，并且以恒定间距均匀地布置，并且具有第一线和第一线的不均匀重复的图案组以及与其非排列方向上的非均匀重复图形组的端部相邻排列的第二装置图案，并且具有第二线和第二空间，第二线和第二空间的宽度大于第一线和第一线的宽度不均匀重复图案组的空间，使不均匀重复图案组的第一线和第一空间的宽度的至少一部分大于第一线的宽度或第一空间的第一空间的宽度均匀重复模式组。

3. 发明授权

US07713833B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07713833B2
公开(公告)日：2010-05-11
申请号：US12557111
申请日：2009-09-10
申请人： Hiromitsu Mashita , Toshiya Kotani , Hidefumi Mukai , Fumiharu Nakajima , Chikaaki Kodama
发明人： Hiromitsu Mashita , Toshiya Kotani , Hidefumi Mukai , Fumiharu Nakajima , Chikaaki Kodama
IPC分类号： H01L21/76
CPC分类号： H01L27/11524 , H01L21/0337 , H01L21/32139
摘要： According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a first film on a target film; forming resist patterns on the first film; processing the first film with the resist patterns to form first patterns including: periodic patterns; and aperiodic patterns; removing the resist patterns; forming a second film over the target film; processing the second film to form second side wall patterns on side walls of the first patterns; removing the periodic patterns; and processing the target film with the aperiodic patterns and the second side wall patterns, thereby forming a target patterns including: periodic target patterns; aperiodic target patterns; and dummy patterns arranged between the periodic target patterns and the aperiodic patterns and arranged periodically with the periodic target patterns.
摘要翻译：根据本发明的一个方面，提供一种制造半导体器件的方法，所述方法包括：在靶膜上形成第一膜; 在第一膜上形成抗蚀剂图案; 用抗蚀剂图案处理第一膜以形成第一图案，包括：周期图案; 和非周期性模式; 去除抗蚀剂图案; 在目标膜上形成第二膜; 处理所述第二膜以在所述第一图案的侧壁上形成第二侧壁图案; 去除周期性模式; 用非周期图案和第二侧壁图案处理目标薄膜，从而形成包括周期性目标图案的目标图案; 非周期目标模式; 以及布置在周期性目标图案和非周期性图案之间的虚拟图案，并且周期性地布置有周期性目标图案。

4. 发明申请

US20120020158A1 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20120020158A1
公开(公告)日：2012-01-26
申请号：US13187000
申请日：2011-07-20
申请人： Tohru OZAKI , Mitsuhiro Noguchi , Hideaki Maekawa , Hiromitsu Mashita , Takafumi Taguchi , Kazuhito Kobayashi , Hidefumi Mukai , Hiroyuki Nitta
发明人： Tohru OZAKI , Mitsuhiro Noguchi , Hideaki Maekawa , Hiromitsu Mashita , Takafumi Taguchi , Kazuhito Kobayashi , Hidefumi Mukai , Hiroyuki Nitta
IPC分类号： G11C16/04 , H01L21/78
CPC分类号： H01L27/11521
摘要： A memory cell array includes memory strings arranged in a first direction. Word-lines and select gate lines extend in a second direction perpendicular to the first direction. The select gate line also extends in the second direction. The word-lines have a first line width in the first direction and arranged with a first distance therebetween. The select gate line includes a first interconnection in the first direction, the first interconnection having a second line width larger than the first line width, and a second interconnection extending from an end portion of the first interconnection, the second interconnection having a third line width the same as the first line width. A first word-line adjacent to the select gate line is arranged having a second distance to the second interconnection, the second distance being (4N+1) times the first distance (N being an integer of 1 or more).
摘要翻译：存储单元阵列包括沿第一方向布置的存储器串。字线和选择栅极线在垂直于第一方向的第二方向上延伸。选择栅极线也沿第二方向延伸。字线在第一方向上具有第一线宽度并且以它们之间的第一距离布置。选择栅极线包括在第一方向上的第一互连，第一互连具有大于第一线宽的第二线宽，以及从第一互连的端部延伸的第二互连，第二互连具有第三线宽与第一行宽度相同。与选择栅极线相邻的第一字线布置成具有到第二互连的第二距离，第二距离为（4N + 1）倍于第一距离（N为1或更大的整数）。

5. 发明授权

US08196071B2 Creating mask data of integrated circuit patterns using calculated etching conversion difference 失效
标题翻译：使用计算出的蚀刻转换差异创建集成电路图案的掩模数据
公开(公告)号：US08196071B2
公开(公告)日：2012-06-05
申请号：US12688644
申请日：2010-01-15
申请人： Hiromitsu Mashita , Katsumi Iyanagi , Takafumi Taguchi , Toshiya Kotani , Hidefumi Mukai , Taiga Uno , Takashi Nakazawa
发明人： Hiromitsu Mashita , Katsumi Iyanagi , Takafumi Taguchi , Toshiya Kotani , Hidefumi Mukai , Taiga Uno , Takashi Nakazawa
IPC分类号： G06F17/50
CPC分类号： G03F1/80 , G03F1/36 , G03F1/54
摘要： A pattern data creating method comprising: referring to a first correspondence relation between an amount of dimension variation between a first pattern formed on a substrate and a second pattern formed by processing the substrate using the first pattern and either one of a pattern total surface area and a pattern boundary length of the first pattern; and creating pattern data for forming the first pattern.
摘要翻译：一种图形数据生成方法，包括：参照形成在基板上的第一图案和通过使用第一图案处理基板而形成的第二图案之间的尺寸变化量之间的第一对应关系，以及图案总表面积和第一图案的图案边界长度; 以及创建用于形成第一图案的图案数据。

6. 发明申请

US20100185313A1 PATTERN DATA CREATING METHOD, COMPUTER PROGRAM PRODUCT, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD 失效
标题翻译：图形数据创建方法，计算机程序产品和半导体器件制造方法
公开(公告)号：US20100185313A1
公开(公告)日：2010-07-22
申请号：US12688644
申请日：2010-01-15
申请人： Hiromitsu MASHITA , Katsumi Iyanagi , Takafumi Taguchi , Toshiya Kotani , Hidefumi Mukai , Taiga Uno , Takashi Nakazawa
发明人： Hiromitsu MASHITA , Katsumi Iyanagi , Takafumi Taguchi , Toshiya Kotani , Hidefumi Mukai , Taiga Uno , Takashi Nakazawa
IPC分类号： G06F17/50
CPC分类号： G03F1/80 , G03F1/36 , G03F1/54
摘要： A pattern data creating method comprising: referring to a first correspondence relation between an amount of dimension variation between a first pattern formed on a substrate and a second pattern formed by processing the substrate using the first pattern and either one of a pattern total surface area and a pattern boundary length of the first pattern; and creating pattern data for forming the first pattern.
摘要翻译：一种图形数据生成方法，包括：参照形成在基板上的第一图案和通过使用第一图案处理基板而形成的第二图案之间的尺寸变化量之间的第一对应关系，以及图案总表面积和第一图案的图案边界长度; 以及创建用于形成第一图案的图案数据。

7. 发明申请

US20100168895A1 MASK VERIFICATION METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND COMPUTER READABLE MEDIUM 审中-公开
标题翻译：掩模验证方法，制造半导体器件的方法和计算机可读介质
公开(公告)号：US20100168895A1
公开(公告)日：2010-07-01
申请号：US12561626
申请日：2009-09-17
申请人： Hiromitsu MASHITA , Fumiharu Nakajima , Toshiya Kotani , Hidefumi Mukai , Issui Aiba
发明人： Hiromitsu MASHITA , Fumiharu Nakajima , Toshiya Kotani , Hidefumi Mukai , Issui Aiba
IPC分类号： G05B13/04 , G06F17/50
CPC分类号： G03F7/705 , G03F1/36
摘要： A mask verification method includes setting optical parameters, verifying whether a pattern, which is obtained when a mask pattern other than a reference pattern of patterns on a mask is transferred on a substrate with use of the set optical parameters, satisfies dimensional specifications, and varying, when the pattern which is obtained when the mask pattern is transferred on the substrate is determined to fail to satisfy the dimensional specifications, the optical parameters at the time of transfer such that the pattern, which is obtained when the reference pattern is transferred on the substrate, satisfies a target dimensional condition, and verifying whether a pattern, which is obtained when the mask pattern other than the reference pattern of the patterns on the mask is transferred on the substrate with use of the varied optical parameters, satisfies the dimensional specifications.
摘要翻译：掩模验证方法包括设置光学参数，验证当掩模上的图案的参考图案之外的掩模图案使用所设置的光学参数在基板上转印时获得的图案是否满足尺寸规格，并且变化当将掩模图案转印到基板上时获得的图案被确定为不能满足尺寸规格，转印时的光学参数使得当在基板上转印参考图案时获得的图案基板，满足目标尺寸条件，并且验证当使用变化的光学参数在掩模上的图案的参考图案之外的掩模图案被转印到基板上时获得的图案是否满足尺寸规格。

8. 发明申请

US20100081265A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20100081265A1
公开(公告)日：2010-04-01
申请号：US12557111
申请日：2009-09-10
申请人： Hiromitsu Mashita , Toshiya Kotani , Hidefumi Mukai , Fumiharu Nakajima , Chikaaki Kodama
发明人： Hiromitsu Mashita , Toshiya Kotani , Hidefumi Mukai , Fumiharu Nakajima , Chikaaki Kodama
IPC分类号： H01L21/28
CPC分类号： H01L27/11524 , H01L21/0337 , H01L21/32139
摘要： According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a first film on a target film; forming resist patterns on the first film; processing the first film with the resist patterns to form first patterns including: periodic patterns; and aperiodic patterns; removing the resist patterns; forming a second film over the target film; processing the second film to form second side wall patterns on side walls of the first patterns; removing the periodic patterns; and processing the target film with the aperiodic patterns and the second side wall patterns, thereby forming a target patterns including: periodic target patterns; aperiodic target patterns; and dummy patterns arranged between the periodic target patterns and the aperiodic patterns and arranged periodically with the periodic target patterns.
摘要翻译：根据本发明的一个方面，提供一种制造半导体器件的方法，所述方法包括：在靶膜上形成第一膜; 在第一膜上形成抗蚀剂图案; 用抗蚀剂图案处理第一膜以形成第一图案，包括：周期图案; 和非周期性模式; 去除抗蚀剂图案; 在目标膜上形成第二膜; 处理所述第二膜以在所述第一图案的侧壁上形成第二侧壁图案; 去除周期性模式; 用非周期图案和第二侧壁图案处理目标薄膜，从而形成包括周期性目标图案的目标图案; 非周期目标模式; 以及布置在周期性目标图案和非周期性图案之间的虚拟图案，并且周期性地布置有周期性目标图案。

9. 发明申请

US20100202181A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20100202181A1
公开(公告)日：2010-08-12
申请号：US12561531
申请日：2009-09-17
申请人： Takaki HASHIMOTO , Hidefumi Mukai , Yasunobu Kai , Toshiya Kotani
发明人： Takaki HASHIMOTO , Hidefumi Mukai , Yasunobu Kai , Toshiya Kotani
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C5/025
摘要： A semiconductor memory device includes a semiconductor substrate on which memory cells are formed. Interconnects are arranged along a first direction above the semiconductor substrate, and have regular intervals along a second direction perpendicular to the first direction. Interconnect contacts connect the interconnects and the semiconductor substrate, are arranged on three or more rows. The center of each of two of the interconnect contacts which are connected to the interconnects adjacent in the second direction deviate from each other along the first direction.
摘要翻译：半导体存储器件包括形成有存储单元的半导体衬底。互连件沿着半导体衬底上方的第一方向布置，并且沿着垂直于第一方向的第二方向具有规则的间隔。互连触点连接互连和半导体衬底，布置在三行或更多行上。连接到在第二方向相邻的互连件的两个互连触点中的每一个的中心沿着第一方向彼此偏离。

10. 发明授权

US07851914B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07851914B2
公开(公告)日：2010-12-14
申请号：US12407613
申请日：2009-03-19
申请人： Kazuyuki Masukawa , Koji Hashimoto , Hidefumi Mukai , Kosuke Yanagidaira
发明人： Kazuyuki Masukawa , Koji Hashimoto , Hidefumi Mukai , Kosuke Yanagidaira
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit device includes a plurality of contact layers located between two lines running in parallel in a first direction. Each of the contact layers has a structure in which an upper contact and a lower contact are coupled together. The plurality of contact layers are arranged zigzag along the first direction, and coupling portions of the upper contact and the lower contact are displaced from the center of the upper contact in a second direction perpendicular to the first direction.
摘要翻译：半导体集成电路器件包括位于沿第一方向平行运行的两条线之间的多个接触层。每个接触层具有其中上触点和下触点耦合在一起的结构。所述多个接触层沿着所述第一方向被锯齿形地设置，并且所述上触点和所述下触点的耦合部分在垂直于所述第一方向的第二方向上从所述上接触件的中心位移。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式