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1. 发明授权

US06333892B2 Synchronous semiconductor memory device capable of selecting column at high speed 失效
公开(公告)号：US06333892B2
公开(公告)日：2001-12-25
申请号：US09725851
申请日：2000-11-30
申请人： Takeshi Hamamoto , Zenya Kawaguchi , Motoko Hara
发明人： Takeshi Hamamoto , Zenya Kawaguchi , Motoko Hara
IPC分类号： G11C800
CPC分类号： G11C7/1072 , G11C8/18
摘要： A command decoder receives an externally supplied command independently of an internal clock signal, decodes the command, generates a column access mode instruction signal, and activates a column address activation signal when the internal clock signal rises. An internal column address signal generating circuit generates an internal column address signal from an externally supplied address signal according to the column address activation signal. Accordingly, the internal column address is generated at an advanced timing to enable a following column selecting operation to be started at a faster timing. A synchronous semiconductor memory device capable of performing the column selecting operation at a high speed is thus provided.

2. 发明授权

US06243320B1 Synchronous semiconductor memory device capable of selecting column at high speed 失效
标题翻译：能够高速选择色谱柱的同步半导体存储器件
公开(公告)号：US06243320B1
公开(公告)日：2001-06-05
申请号：US09265856
申请日：1999-03-11
申请人： Takeshi Hamamoto , Zenya Kawaguchi , Motoko Hara
发明人： Takeshi Hamamoto , Zenya Kawaguchi , Motoko Hara
IPC分类号： G11C800
CPC分类号： G11C7/1072 , G11C8/18
摘要： A command decoder receives an externally supplied command independently of an internal clock signal, decodes the command, generates a column access mode instruction signal, and activates a column address activation signal when the internal clock signal rises. An internal column address signal generating circuit generates an internal column address signal from an externally supplied address signal according to the column address activation signal. Accordingly, the internal column address is generated at an advanced timing to enable a following column selecting operation to be started at a faster timing. A synchronous semiconductor memory device capable of performing the column selecting operation at a high speed is thus provided.
摘要翻译：命令解码器独立于内部时钟信号接收外部提供的命令，解码该命令，产生列存取模式指令信号，并且当内部时钟信号上升时激活列地址激活信号。内部列地址信号发生电路根据列地址激活信号从外部提供的地址信号产生内部列地址信号。因此，在高级定时产生内部列地址，以使得能够以更快的定时开始以下列选择操作。因此提供了能够高速执行列选择操作的同步半导体存储器件。

3. 发明授权

US06603817B1 Buffer circuit capable of correctly transferring small amplitude signal in synchronization with high speed clock signal 有权
标题翻译：缓冲电路能够与高速时钟信号同步正确传送小振幅信号
公开(公告)号：US06603817B1
公开(公告)日：2003-08-05
申请号：US09531504
申请日：2000-03-21
申请人： Takeshi Hamamoto , Zenya Kawaguchi
发明人： Takeshi Hamamoto , Zenya Kawaguchi
IPC分类号： H03H730
CPC分类号： G11C7/065
摘要： Complementary signals on a pair of first signal lines are transferred onto a pair of second signal lines in synchronization with a clock signal by a buffer circuit. The buffer circuit includes an equalize circuit to equalize a pair of internal nodes to a prescribed potential, a transfer gate circuit activated, when the equalize circuit completes equalization, to couple the pair of first signal lines and the pair of internal nodes, an amplifier circuit to differentially amplify the signals on the internal nodes when the transfer gate completes the transfer operation, an output transfer circuit to transmit the signals on the pair of internal nodes onto the pair of second signal lines in synchronization with the clock signal, and a control circuit to control the operation of the equalize circuit, the transfer gate circuit and the amplifier circuit. After the pair of internal nodes is equalized to the prescribed potential, the signals from the pair of first signal lines are received and amplified. Even if the signals are small amplitude signals, therefore, they can be correctly amplified and transferred in synchronization with the clock signal without destroying the signal amplitude.
摘要翻译：一对第一信号线上的互补信号通过缓冲电路与时钟信号同步地传送到一对第二信号线上。缓冲电路包括均衡电路，以将一对内部节点均衡到规定电位，当均衡电路完成均衡时，传输门电路被激活，耦合该对第一信号线和一对内部节点，放大器电路当传输门完成传送操作时，差分地放大内部节点上的信号;输出传送电路，用于与时钟信号同步地将一对内部节点上的信号传输到一对第二信号线;以及控制电路控制均衡电路，传输门电路和放大电路的工作。在一对内部节点等于规定电位之后，来自该对第一信号线的信号被接收和放大。因此，即使信号是小振幅信号，也可以与时钟信号同步地进行正确的放大和传输，而不会破坏信号幅度。

4. 发明授权

US08643105B2 Semiconductor memory device and manufacturing method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08643105B2
公开(公告)日：2014-02-04
申请号：US12263762
申请日：2008-11-03
申请人： Takeshi Hamamoto
发明人： Takeshi Hamamoto
IPC分类号： H01L27/12
CPC分类号： H01L27/108 , H01L21/84 , H01L27/10802 , H01L27/10826 , H01L27/1203 , H01L29/7841 , H01L29/785
摘要： This disclosure concerns a semiconductor memory device including a semiconductor substrate; a buried insulation film provided on the semiconductor substrate; a semiconductor layer provided on the buried insulation film; a source layer and a drain layer provided in the semiconductor layer; a body region provided in the semiconductor layer between the source layer and the drain layer, and being in an electrically floating state, the body region accumulating or discharging charges to store data; a gate dielectric film provided on the body region; a gate electrode provided on the gate dielectric film; and a plate electrode facing a side surface of the body region via an insulation film, in an element isolation region.
摘要翻译：本公开涉及包括半导体衬底的半导体存储器件; 设置在半导体衬底上的掩埋绝缘膜; 设置在所述掩埋绝缘膜上的半导体层; 设置在所述半导体层中的源极层和漏极层; 设置在所述源极层和所述漏极层之间的所述半导体层中并处于电浮动状态的体区，所述体区累积或放电以存储数据; 设置在所述身体区域上的栅极电介质膜; 设置在栅极电介质膜上的栅电极; 以及在元件隔离区域中经由绝缘膜面对主体区域的侧表面的平板电极。

5. 发明授权

US07952162B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07952162B2
公开(公告)日：2011-05-31
申请号：US12541449
申请日：2009-08-14
申请人： Takeshi Hamamoto
发明人： Takeshi Hamamoto
IPC分类号： H01L21/76
CPC分类号： H01L29/7841 , H01L27/108 , H01L27/10802
摘要： A semiconductor device of one embodiment of the present invention includes a substrate; isolation layers, each of which is formed in a trench formed on the substrate and has an insulating film and a conductive layer; a semiconductor layer of a first conductivity type for storing signal charges, formed between the isolation layers and isolated from the conductive layers by the insulating films; a semiconductor layer of a second conductivity type, formed under the semiconductor layer of the first conductivity type; and a transistor having a gate insulator film formed on the semiconductor layer of the first conductivity type and a gate electrode formed on the gate insulator film.
摘要翻译：本发明的一个实施例的半导体器件包括：衬底; 隔离层，其形成在形成在基板上的沟槽中，并且具有绝缘膜和导电层; 用于存储信号电荷的第一导电类型的半导体层，形成在隔离层之间并通过绝缘膜与导电层隔离; 形成在第一导电类型的半导体层下方的第二导电类型的半导体层; 以及具有形成在第一导电类型的半导体层上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极的晶体管。

6. 发明授权

US07719056B2 Semiconductor memory device having a floating body and a plate electrode 有权
标题翻译：具有浮体和平板电极的半导体存储器件
公开(公告)号：US07719056B2
公开(公告)日：2010-05-18
申请号：US11687131
申请日：2007-03-16
申请人： Takeshi Hamamoto
发明人： Takeshi Hamamoto
IPC分类号： H01L27/088
CPC分类号： H01L27/108 , H01L21/764 , H01L21/84 , H01L27/10802 , H01L29/7841
摘要： This disclosure concerns a method of manufacturing a semiconductor memory device comprising forming a plurality of trenches in a semiconductor substrate; forming a semiconductor layer provided on a cavity by connecting lower spaces of the trenches to one another and closing upper openings of the trenches in a heat treatment under a hydrogen atmosphere; etching the semiconductor layer in an isolation formation area; forming an insulating film on a side surface and a bottom surface of the semiconductor layer; filling the cavity under the semiconductor layer with an electrode material; and forming a memory element on the semiconductor layer.
摘要翻译：本公开涉及一种制造半导体存储器件的方法，包括在半导体衬底中形成多个沟槽; 通过将沟槽的下部空间彼此连接并在氢气氛下的热处理中闭合沟槽的上部开口，形成设置在空腔上的半导体层; 在隔离形成区域中蚀刻半导体层; 在半导体层的侧表面和底表面上形成绝缘膜; 用电极材料填充半导体层下面的空腔; 以及在所述半导体层上形成存储元件。

7. 发明授权

US07692963B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07692963B2
公开(公告)日：2010-04-06
申请号：US11934337
申请日：2007-11-02
申请人： Tomoaki Shino , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
发明人： Tomoaki Shino , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
IPC分类号： G11C11/34
CPC分类号： G11C11/404 , G11C11/409 , G11C11/4091 , G11C11/4097 , G11C11/4099 , G11C2211/4016 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： The disclosure concerns a semiconductor memory device comprising a semiconductor layer; a charge trap film in contact with a first surface of the semiconductor layer; a gate insulating film in contact with a second surface of the semiconductor layer, the second surface being opposite to the first surface; a back gate electrode in contact with the charge trap film; a gate electrode in contact with the gate insulating film; a source and a drain formed in the semiconductor layer; and a body region provided between the drain and the source, the body region being in an electrically floating state, wherein a threshold voltage or a drain current of a memory cell including the source, the drain, and the gate electrode is adjusted by changing number of majority carriers accumulated in the body region and a quantity of charges trapped into the charge trap film.
摘要翻译：本公开涉及包括半导体层的半导体存储器件; 与所述半导体层的第一表面接触的电荷陷阱膜; 与所述半导体层的第二表面接触的栅极绝缘膜，所述第二表面与所述第一表面相对; 与电荷陷阱膜接触的背栅电极; 与栅极绝缘膜接触的栅电极; 在半导体层中形成的源极和漏极; 以及设置在所述漏极和源极之间的体区，所述体区域处于电浮置状态，其中通过改变数量来调整包括所述源极，漏极和所述栅电极的存储单元的阈值电压或漏极电流的多数载体积聚在身体区域中，并且一定量的电荷被捕获到电荷陷阱膜中。

8. 发明授权

US07537989B2 Method for manufacturing SOI substrate 有权
标题翻译：制造SOI衬底的方法
公开(公告)号：US07537989B2
公开(公告)日：2009-05-26
申请号：US11559347
申请日：2006-11-13
申请人： Tetsuya Nakai , Bong-Gyun Ko , Takeshi Hamamoto , Takashi Yamada
发明人： Tetsuya Nakai , Bong-Gyun Ko , Takeshi Hamamoto , Takashi Yamada
IPC分类号： H01L21/8238
CPC分类号： H01L21/76243
摘要： To easily and accurately flush a substrate surface serving an SOI area with a substrate surface serving as a bulk area, make a buried oxide film, and prevent an oxide film from being exposed on substrate surface. After partially forming a mask oxide film 23 on the surface of a substrate 12 constituted of single crystal silicon, oxygen ions 16 are implanted into the surface of the substrate through the mask oxide film, and the substrate is annealed to form a buried oxide film 13 inside the substrate. Further included is a step of forming a predetermined-depth concave portion 12c deeper than substrate surface 12b serving as a bulk area on which the mask oxide film is formed on the substrate surface 12a serving as an SOI area by forming a thermally grown oxide film 21 on the substrate surface 12a serving as an SOI area on which the mask oxide film is not formed between the step of forming the mask oxide film and the step of implanting oxygen ions.
摘要翻译：为了容易且准确地将用作SOI区域的基板表面与用作主体区域的基板表面冲洗，形成掩埋氧化膜，并且防止氧化膜暴露在基板表面上。在由单晶硅构成的基板12的表面上部分地形成掩模氧化膜23之后，通过掩模氧化膜将氧离子16注入到基板的表面，并将基板退火以形成掩埋氧化膜13 在基板内。进一步包括通过形成热生长氧化物膜21，形成比作为其上形成有掩模氧化膜的体积面的衬底表面12b更深的预定深度凹部12c的步骤，该衬底表面12b形成在用作SOI区域的衬底表面12a上在形成掩模氧化膜的步骤和注入氧离子的步骤之间作为其上未形成掩模氧化物膜的SOI区域的衬底表面12a上。

9. 发明申请

US20080305588A1 Nand-type semiconductor storage device and method for manufacturing same 失效
标题翻译： N型半导体存储装置及其制造方法
公开(公告)号：US20080305588A1
公开(公告)日：2008-12-11
申请号：US12222143
申请日：2008-08-04
申请人： Takeshi Hamamoto , Akihiro Nitayama
发明人： Takeshi Hamamoto , Akihiro Nitayama
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L21/84 , H01L27/11521 , H01L27/11524 , H01L27/1203
摘要： According to this invention, there is provided a NAND-type semiconductor storage device including a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, a buried insulating film selectively formed between the semiconductor substrate and the semiconductor layer in a memory transistor formation region, diffusion layers formed on the semiconductor layer in the memory transistor formation region, floating body regions between the diffusion layers, a first insulating film formed on each of the floating body regions, a floating gate electrode formed on the first insulating film, a control electrode on a second insulating film formed on the floating gate electrode, and contact plugs connected to ones of the pairs of diffusion layers which are respectively located at ends of the memory transistor formation region, wherein the ones of the pairs of diffusion layers, which are located at the ends of the memory transistor formation region, are connected to the semiconductor substrate below the contact plugs.
摘要翻译：根据本发明，提供了一种NAND型半导体存储装置，包括半导体衬底，形成在半导体衬底上的半导体层，在存储晶体管形成区域中选择性地形成在半导体衬底和半导体层之间的埋入绝缘膜，形成在存储晶体管形成区域的半导体层上的扩散层，扩散层之间的浮体区域，形成在每个浮体区域上的第一绝缘膜，形成在第一绝缘膜上的浮栅，控制电极形成在浮置栅电极上的第二绝缘膜和连接到分别位于存储晶体管形成区的端部的一对扩散层的接触插塞，其中位于存储晶体管形成区域的端部连接到半导体导体基板在接触塞下方。

10. 发明授权

US06903976B2 Semiconductor memory device reduced in power consumption during burn-in test 失效
标题翻译：半导体存储器件在老化测试期间降低功耗
公开(公告)号：US06903976B2
公开(公告)日：2005-06-07
申请号：US10610762
申请日：2003-07-02
申请人： Tomoya Kawagoe , Takeshi Hamamoto
发明人： Tomoya Kawagoe , Takeshi Hamamoto
IPC分类号： G01R31/30 , G01R31/28 , G11C5/14 , G11C11/401 , G11C11/408 , G11C29/06 , G11C29/14 , G11C7/00
CPC分类号： G11C29/14 , G01R31/2879 , G11C11/401 , G11C29/12005 , G11C2029/1204
摘要： At the time of burn-in test, substrate voltages of transistors in a sense amplifier are switched by a PMOS substrate voltage generating portion and an NMOS substrate voltage generating portion. Specifically, the substrate voltage of a P channel MOS transistor is increased during the test than in a normal operation, whereas the substrate voltage of an N channel MOS transistor is decreased during the test than in the normal operation. Consequently, the threshold voltages of the P channel and N channel MOS transistors can be increased upon the test. Leakage currents in the turned-off states can be reduced, and thus, power consumption during the burn-in test can be decreased.
摘要翻译：在老化测试时，读出放大器中的晶体管的衬底电压由PMOS衬底电压产生部分和NMOS衬底电压产生部分切换。具体而言，在测试中P沟道MOS晶体管的衬底电压比正常工作时增加，而N沟道MOS晶体管的衬底电压在测试期间比在正常工作中降低。因此，可以在测试时增加P沟道和N沟道MOS晶体管的阈值电压。关闭状态下的泄漏电流可以降低，从而可以降低老化试验期间的功耗。

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