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1. 发明授权

US06319853B1 Method of manufacturing a semiconductor device using a minute resist pattern, and a semiconductor device manufactured thereby 有权
标题翻译：使用微小抗蚀剂图案的半导体器件的制造方法以及由此制造的半导体器件
公开(公告)号：US06319853B1
公开(公告)日：2001-11-20
申请号：US09537671
申请日：2000-03-29
申请人： Takeo Ishibashi , Toshiyuki Toyoshima , Keiichi Katayama , Naoki Yasuda
发明人： Takeo Ishibashi , Toshiyuki Toyoshima , Keiichi Katayama , Naoki Yasuda
IPC分类号： H01L2131
CPC分类号： G03F7/40 , G03F7/0035
摘要： There is described a method of producing a pure resist pattern having superior topography smaller than the limit of wavelength of exposure light. A first resist pattern containing material capable of producing an acid on exposure to light is coated with a second resist containing material which causes a crosslinking reaction in the presence of an acid. An acid is produced in the resist pattern by exposing the pattern to light, thus forming a crosslinked layer along the boundary surface between the first resist pattern and the second resist. As a result, a second resist pattern which is greater than the first resist pattern is formed. Minute pure resist patterns are produced through two-step processing: that is, by removing the second resist from the substrate through use of a liquid prepared by dissolving an organic solvent into water and by rinsing the substrate with water. The diameter of holes formed in the resist or the interval between isolated patterns can be reduced.
摘要翻译：描述了一种制造具有比曝光光的波长极限更好的形貌的纯抗蚀剂图案的方法。含有能够在暴露于光下产生酸的材料的第一抗蚀剂图案涂覆有在酸存在下引起交联反应的第二抗蚀剂含量材料。通过将图案曝光而在抗蚀剂图案中产生酸，从而沿着第一抗蚀剂图案和第二抗蚀剂之间的边界面形成交联层。结果，形成比第一抗蚀剂图案大的第二抗蚀剂图案。通过两步处理产生分钟的纯抗蚀剂图案：即，通过使用通过将有机溶剂溶解在水中而制备的液体并通过用水冲洗基材从基材中除去第二抗蚀剂。可以减少在抗蚀剂中形成的孔的直径或隔离图案之间的间隔。

2. 发明授权

US06579657B1 Material for forming a fine pattern and method for manufacturing a semiconductor device using the same 失效
标题翻译：用于形成精细图案的材料和使用其制造半导体器件的方法
公开(公告)号：US06579657B1
公开(公告)日：2003-06-17
申请号：US09049072
申请日：1998-03-27
申请人： Takeo Ishibashi , Toshiyuki Toyoshima , Keiichi Katayama , Ayumi Minamide
发明人： Takeo Ishibashi , Toshiyuki Toyoshima , Keiichi Katayama , Ayumi Minamide
IPC分类号： G03F740
CPC分类号： H01L21/0271 , G03F7/0035 , G03F7/038 , G03F7/40 , H01L21/0273
摘要： A resist pattern, containing a material capable of generating an acid by exposure to light, is covered with a resist containing a material capable of crosslinkage in the presence of an acid. The acid is generated in the resist pattern by application of heat or by exposure to light, and a crosslinked layer is formed at the interface as a cover layer for the resist pattern, thereby causing the resist pattern to be thickened. Thus, the hole diameter of the resist pattern can be reduced, or the isolation width of a resist pattern can be reduced.
摘要翻译：含有能够通过曝光产生酸的材料的抗蚀剂图案被含有能够在酸存在下能够交联的材料的抗蚀剂覆盖。通过施加热或暴露于光而在抗蚀剂图案中产生酸，并且在界面处形成交联层作为抗蚀剂图案的覆盖层，从而使抗蚀剂图案变厚。因此，可以减小抗蚀剂图案的孔径，或者可以减小抗蚀剂图案的隔离宽度。

3. 发明授权

US5858620A Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5858620A
公开(公告)日：1999-01-12
申请号：US785846
申请日：1997-01-24
申请人： Takeo Ishibashi , Ayumi Minamide , Toshiyuki Toyoshima , Keiichi Katayama
发明人： Takeo Ishibashi , Ayumi Minamide , Toshiyuki Toyoshima , Keiichi Katayama
IPC分类号： G03F7/00 , G03F7/40 , H01L21/027 , H01L21/311 , H01L21/3213 , G03C5/00
CPC分类号： H01L21/32139 , G03F7/0035 , G03F7/40 , H01L21/0273 , H01L21/31144 , G03F7/405
摘要： A first resist pattern, which is capable of generating an acid, is formed on a semiconductor device layer. Over the first resist pattern, a layer of a second resist, which is capable of undergoing an cross-linking reaction in the presence of an acid, is formed. Then, a cross-linked film is formed in portions of said layer of the second resist at the boundary with said first resist by action of an acid from said first resist. Thereafter, non-cross-linked portions of said second resist are removed to form a finely isolated resist pattern. The semiconductor device layer is etched, via a mask of said finely isolated resist pattern, to form a fine spaces or holes.
摘要翻译：能够产生酸的第一抗蚀剂图案形成在半导体器件层上。在第一抗蚀剂图案上，形成能够在酸存在下进行交联反应的第二抗蚀剂层。然后，通过来自所述第一抗蚀剂的酸的作用，在与所述第一抗蚀剂的边界处的所述第二抗蚀剂层的部分形成交联膜。此后，除去所述第二抗蚀剂的非交联部分以形成精细隔离的抗蚀剂图案。通过所述精细隔离的抗蚀剂图案的掩模蚀刻半导体器件层，以形成精细的空间或孔。

4. 发明授权

US06180320B2 Method of manufacturing a semiconductor device having a fine pattern, and semiconductor device manufactured thereby 失效
标题翻译：具有精细图案的半导体器件的制造方法以及由此制造的半导体器件
公开(公告)号：US06180320B2
公开(公告)日：2001-01-30
申请号：US09371499
申请日：1999-08-10
申请人： Takayuki Saito , Takeo Ishibashi , Toshiyuki Toyoshima , Kanji Sugino , Naoki Yasuda , Tadashi Miyagi
发明人： Takayuki Saito , Takeo Ishibashi , Toshiyuki Toyoshima , Kanji Sugino , Naoki Yasuda , Tadashi Miyagi
IPC分类号： G03F7039
CPC分类号： G03F7/40 , H01L21/0274 , H01L21/0338
摘要： There is described a method of stably manufacturing a fine resist pattern narrower than the wavelength of exposing light from a stepper. Under the method, a resist pattern is formed on a semiconductor substrate through use of an acid catalyst chemically-amplified photoresist, and an organic film which includes an acid or which produces an acid on exposure to light is formed on the surface of the semiconductor substrate including the resist pattern. The organic film is then subjected to a heat treatment to thereby diffuse an acid. The surface layer of the resist pattern is made soluble in an alkaline developer, and the surface layer of the resist pattern is removed through use of the alkaline developer. As a result, a fine resist pattern is formed.
摘要翻译：描述了一种稳定地制造比曝光来自步进器的光的波长窄的精细抗蚀剂图案的方法。在该方法下，通过使用酸催化剂化学扩增的光致抗蚀剂在半导体衬底上形成抗蚀剂图案，并且在半导体衬底的表面上形成包含酸或在曝光时产生酸的有机膜包括抗蚀剂图案。然后对有机膜进行热处理，从而扩散酸。抗蚀剂图案的表面层可溶于碱性显影剂，通过使用碱性显影剂除去抗蚀剂图案的表面层。结果，形成精细的抗蚀剂图案。

5. 发明申请

US20060246380A1 Micropattern forming material and method for forming micropattern 审中-公开
标题翻译：微图案形成材料和形成微图案的方法
公开(公告)号：US20060246380A1
公开(公告)日：2006-11-02
申请号：US11354728
申请日：2006-02-15
申请人： Mamoru Terai , Toshiyuki Toyoshima , Takeo Ishibashi , Shinji Tarutani
发明人： Mamoru Terai , Toshiyuki Toyoshima , Takeo Ishibashi , Shinji Tarutani
IPC分类号： G03C5/00
CPC分类号： G03F7/40 , G03F7/2024 , H01L21/02118 , H01L21/02282 , H01L21/312
摘要： A micropattern forming material is formed on a resist pattern containing an acidic group. The micropattern forming material comprises a compound that penetrates the resist pattern. The penetration of the compound causes the resist pattern to form a crosslinked layer and thereby swell resulting in formation of a film insoluble in water or alkali.
摘要翻译：在含有酸性基团的抗蚀剂图案上形成微图案形成材料。微图案形成材料包括穿透抗蚀剂图案的化合物。化合物的渗透导致抗蚀剂图案形成交联层，从而溶胀，形成不溶于水或碱的膜。

6. 发明授权

US07030007B2 Via-filling material and process for fabricating semiconductor integrated circuit using the material 失效
标题翻译：通孔填充材料和使用该材料的半导体集成电路的制造工艺
公开(公告)号：US07030007B2
公开(公告)日：2006-04-18
申请号：US10623772
申请日：2003-07-22
申请人： Teruhiko Kumada , Toshiyuki Toyoshima , Hideharu Nobutoki , Takeo Ishibashi , Yoshiharu Ono , Junjiro Sakai
发明人： Teruhiko Kumada , Toshiyuki Toyoshima , Hideharu Nobutoki , Takeo Ishibashi , Yoshiharu Ono , Junjiro Sakai
IPC分类号： H01L21/47
CPC分类号： H01L21/76808 , H01L21/02118 , H01L21/0212 , H01L21/02282 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/312 , H01L21/3127 , H01L21/76814
摘要： A via-filling material includes a polymer containing a repeating unit represented by wherein R1 one of hydrogen, fluorine, chlorine, bromine, and methyl group; R2 is one of hydrogen, a C1-3 alkyl group, and a C1-4 alkyl group in which the hydrogen is replaced by at least one of fluorine, chlorine, and bromine; and X is —C(═O)O— or —S(═O)2O—. This via-filling material does not generate deposits around an opening of a via hole during plasma etching and provides a semiconductor integrated circuit with high reliability, even when a trench wider than the via hole is formed by plasma etching around the via hole filled with the via-filling material.
摘要翻译：通孔填充材料包括含有由氢，氟，氯，溴和甲基中的R 1〜1个表示的重复单元的聚合物; R 2是氢，C 1-3烷基和被取代氢的C 1-4烷基中的一个通过氟，氯和溴中的至少一种; 并且X是-C（-O）O-或-S（-O）2 O-。这种通孔填充材料在等离子体蚀刻期间不会在通孔的开口附近产生沉积物，并且提供具有高可靠性的半导体集成电路，即使当通过等离子体蚀刻形成通孔以外的沟槽时，通孔周围填充有通孔通孔填充材料。

7. 发明申请

US20050101123A1 Via-filling material and process for fabricating semiconductor integrated circuit using the material 失效
标题翻译：通孔填充材料和使用该材料制造半导体集成电路的工艺
公开(公告)号：US20050101123A1
公开(公告)日：2005-05-12
申请号：US10623772
申请日：2003-07-22
申请人： Teruhiko Kumada , Toshiyuki Toyoshima , Hideharu Nobutoki , Takeo Ishibashi , Yoshiharu Ono , Junjiro Sakai
发明人： Teruhiko Kumada , Toshiyuki Toyoshima , Hideharu Nobutoki , Takeo Ishibashi , Yoshiharu Ono , Junjiro Sakai
IPC分类号： C08L33/04 , C08F20/22 , C08L63/00 , H01L21/311 , H01L21/312 , H01L21/768 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76808 , H01L21/02118 , H01L21/0212 , H01L21/02282 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/312 , H01L21/3127 , H01L21/76814
摘要： A via-filling material includes a polymer containing a repeating unit represented by wherein R1 one of hydrogen, fluorine, chlorine, bromine, and methyl group; R2 is one of hydrogen, a C1-3 alkyl group, and a C1-4 alkyl group in which the hydrogen is replaced by at least one of fluorine, chlorine, and bromine; and X is —C(═O)O or —S(═O)2O—. This via-filling material does not generate deposits around an opening of a via hole during plasma etching and provides a semiconductor integrated circuit with high reliability, even when a trench wider than the via hole is formed by plasma etching around the via hole filled with the via-filling material.
摘要翻译：通孔填充材料包括含有由氢，氟，氯，溴和甲基中的R 1〜1个表示的重复单元的聚合物; R 2是氢，C 1-3烷基和被取代氢的C 1-4烷基中的一个通过氟，氯和溴中的至少一种; 并且X是-C（-O）O或-S（-O）2 O-。这种通孔填充材料在等离子体蚀刻期间不会在通孔的开口附近产生沉积物，并且提供具有高可靠性的半导体集成电路，即使当通过等离子体蚀刻形成通孔以外的沟槽时，通孔周围填充有通孔通孔填充材料。

8. 发明授权

US08017305B2 Pattern forming method, semiconductor device manufacturing method and exposure mask set 有权
标题翻译：图案形成方法，半导体器件制造方法和曝光掩模组
公开(公告)号：US08017305B2
公开(公告)日：2011-09-13
申请号：US12652470
申请日：2010-01-05
申请人： Takeo Ishibashi , Takayuki Saito , Maya Itoh , Shuji Nakao
发明人： Takeo Ishibashi , Takayuki Saito , Maya Itoh , Shuji Nakao
IPC分类号： G03F7/26
CPC分类号： G03F7/70466 , G03F1/00
摘要： First, a first exposure process is performed using dipole illumination with only a grating-pattern forming region as a substantial object to be exposed. Next, a second exposure process is performed with only a standard-pattern forming region as a substantial object to be exposed. A development process is then performed to obtain a resist pattern. A mask for the first exposure process is such that a light blocking pattern is formed on the whole surface of a standard-pattern mask part corresponding to the standard-pattern forming region. A mask for the second exposure is such that a light blocking pattern is formed on the whole surface of a grating-pattern mask part corresponding to the grating-pattern forming region.
摘要翻译：首先，使用仅具有光栅图案形成区域的偶极照明作为要暴露的实质对象来执行第一曝光处理。接下来，仅以标准图案形成区域作为要曝光的实质物体进行第二曝光处理。然后进行显影处理以获得抗蚀剂图案。用于第一曝光处理的掩模使得在对应于标准图案形成区域的标准图案掩模部件的整个表面上形成遮光图案。用于第二曝光的掩模使得在对应于光栅图案形成区域的光栅图案掩模部分的整个表面上形成遮光图案。

9. 发明申请

US20090039519A1 SEMICONDUCTOR DEVICE, PHOTOMASK, SEMICONDUCTOR DEVICE PRODUCTION METHOD, AND PATTERN LAYOUT METHOD 审中-公开
标题翻译：半导体器件，光电子器件，半导体器件生产方法和图案布局方法
公开(公告)号：US20090039519A1
公开(公告)日：2009-02-12
申请号：US12187786
申请日：2008-08-07
申请人： Takayuki Saito , Takeo Ishibashi , Itaru Kanai
发明人： Takayuki Saito , Takeo Ishibashi , Itaru Kanai
IPC分类号： H01L23/48 , G03F1/00
CPC分类号： G03F1/36 , G03F1/00 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to an aspect of the invention includes plural line pattern and plural pad patterns. The line patterns are repeatedly disposed with a space pattern interposed therebetween. The pad pattern straddles plural columns of the line patterns. The pad pattern is connected to the line pattern located on one side of the pad pattern in one of the plural columns, the pad pattern is connected to the line pattern located on the other side of the pad pattern in another column of the plural columns, and the line pattern located on one side of the pad pattern includes an open-circuit portion in another column. Therefore, a semiconductor device in which an interconnection pattern including the fine line-and-space-shape line pattern and the pad pattern is accurately formed at low cost, a semiconductor device production method, and a photomask used to produce the semiconductor device can be provided.
摘要翻译：根据本发明的一个方面的半导体器件包括多个线图案和多个衬垫图案。线图案重复地设置有插入其间的空间图案。焊盘图案跨越多列线图案。焊盘图案连接到位于多列之一中的焊盘图案的一侧的线图案，焊盘图案连接到位于多列的另一列中的焊盘图案另一侧的线图案，并且位于焊盘图案的一侧上的线图案包括另一列中的开路部分。因此，以低成本精确地形成包括细线和空间形线图案和焊盘图案的布线图形的半导体器件可以是用于制造半导体器件的半导体器件制造方法和光掩模提供。

10. 发明申请

US20110221077A1 WATER REPELLANT COMPOSITION FOR SUBSTRATE TO BE EXPOSED, METHOD FOR FORMING RESIST PATTERN, ELECTRONIC DEVICE PRODUCED BY THE FORMATION METHOD, TREATMENT METHOD FOR IMPARTING WATER REPELLENCY TO SUBSTRATE TO BE EXPOSED, WATER REPELLANT SET FOR SUBSTRATE TO BE EXPOSED, AND TREATMENT METHOD FOR IMPARTING WATER REPELLENCY TO SUBSTRATE TO BE EXPOSED USING THE SAME 失效
标题翻译：用于形成耐蚀图案的水性组合物，形成方法生产的电子装置，用于将水再循环到底层以进行喷涂的处理方法，待被暴露的基材的水刷组合物，以及用于改变水的处理方法使用相同方式进行基材曝光
公开(公告)号：US20110221077A1
公开(公告)日：2011-09-15
申请号：US12867670
申请日：2009-02-20
申请人： Takeo Ishibashi , Miwako Ishibashi , Mamoru Terai , Takuya Hagiwara , Osamu Yokokoji , Yoko Takebe
发明人： Takeo Ishibashi , Miwako Ishibashi , Mamoru Terai , Takuya Hagiwara , Osamu Yokokoji , Yoko Takebe
IPC分类号： H01L23/00 , C09D5/00 , G03F7/20
CPC分类号： G03F7/16 , G03F7/11 , G03F7/2041
摘要： It is an object of the present invention to provide a water repellant composition for a substrate to be exposed which inhibits the back side of a substrate to be exposed from being contaminated by an immersion liquid, can improve adhesion between a film to be processed and an organic film directly overlying that film to inhibit film peeling, and has excellent workability, a method for forming a resist pattern, an electronic device produced by the formation method, a treatment method for imparting water repellency to a substrate to be exposed, a water repellent set for a substrate to be exposed, and a treatment method for imparting water repellency to a substrate to be exposed using the same. A water repellent composition for a substrate to be exposed including at least an organosilicon compound represented by the following general formula (1) and a solvent is used. In the formula, R1 is a monovalent organic group having 14 to 30 carbon atoms, each R2, R3, and R4 is independently a monovalent organic group or a hydrolyzable group having 1 to 10 carbon atoms, and at least one of R2, R3, and R4 is a hydrolyzable group.
摘要翻译：本发明的目的是提供一种抑制待暴露基板的背面被浸没液体污染的待曝光基材的防水组合物，可提高被处理膜与有机膜直接覆盖该膜以抑制膜剥离，并且具有优异的可加工性，形成抗蚀剂图案的方法，通过形成方法制造的电子器件，对待暴露的基底赋予拒水性的处理方法，防水剂设置为要暴露的基底，以及用于使用其进行曝光的基底赋予拒水性的处理方法。使用至少包含由以下通式（1）表示的有机硅化合物和溶剂的待曝光底物用防水组合物。式中，R1为碳原子数为14〜30的一价有机基团，R2，R3，R4分别独立为1价有机基团或碳原子数1〜10的可水解基团，R2，R3， R4是可水解基团。

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