专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07459265B2 Pattern forming method, semiconductor device manufacturing method and exposure mask set 有权
标题翻译：图案形成方法，半导体器件制造方法和曝光掩模组
公开(公告)号：US07459265B2
公开(公告)日：2008-12-02
申请号：US11255877
申请日：2005-10-24
申请人： Takeo Ishibashi , Takayuki Saito , Maya Itoh , Shuji Nakao
发明人： Takeo Ishibashi , Takayuki Saito , Maya Itoh , Shuji Nakao
IPC分类号： G03F7/00
CPC分类号： G03F7/70466 , G03F1/00
摘要： First, a first exposure process is performed using dipole illumination with only a grating-pattern forming region as a substantial object to be exposed. Next, a second exposure process is performed with only a standard-pattern forming region as a substantial object to be exposed. A development process is then performed to obtain a resist pattern. A mask for the first exposure process is such that a light blocking pattern is formed on the whole surface of a standard-pattern mask part corresponding to the standard-pattern forming region. A mask for the second exposure is such that a light blocking pattern is formed on the whole surface of a grating-pattern mask part corresponding to the grating-pattern forming region.
摘要翻译：首先，使用仅具有光栅图案形成区域的偶极照明作为要暴露的实质对象来执行第一曝光处理。接下来，仅以标准图案形成区域作为要曝光的实质物体进行第二曝光处理。然后进行显影处理以获得抗蚀剂图案。用于第一曝光处理的掩模使得在对应于标准图案形成区域的标准图案掩模部件的整个表面上形成遮光图案。用于第二曝光的掩模使得在对应于光栅图案形成区域的光栅图案掩模部分的整个表面上形成遮光图案。

2. 发明申请

US20060088792A1 Pattern forming method, semiconductor device manufacturing method and exposure mask set 有权
标题翻译：图案形成方法，半导体器件制造方法和曝光掩模组
公开(公告)号：US20060088792A1
公开(公告)日：2006-04-27
申请号：US11255877
申请日：2005-10-24
申请人： Takeo Ishibashi , Takayuki Saito , Maya Itoh , Shuji Nakao
发明人： Takeo Ishibashi , Takayuki Saito , Maya Itoh , Shuji Nakao
IPC分类号： G03F7/00
CPC分类号： G03F7/70466 , G03F1/00
摘要： First, a first exposure process is performed using dipole illumination with only a grating-pattern forming region as a substantial object to be exposed. Next, a second exposure process is performed with only a standard-pattern forming region as a substantial object to be exposed. A development process is then performed to obtain a resist pattern. A mask for the first exposure process is such that a light blocking pattern is formed on the whole surface of a standard-pattern mask part corresponding to the standard-pattern forming region. A mask for the second exposure is such that a light blocking pattern is formed on the whole surface of a grating-pattern mask part corresponding to the grating-pattern forming region.
摘要翻译：首先，使用仅具有光栅图案形成区域的偶极照明作为要暴露的实质对象来执行第一曝光处理。接下来，仅以标准图案形成区域作为要曝光的实质物体进行第二曝光处理。然后进行显影处理以获得抗蚀剂图案。用于第一曝光处理的掩模使得在对应于标准图案形成区域的标准图案掩模部件的整个表面上形成遮光图案。用于第二曝光的掩模使得在对应于光栅图案形成区域的光栅图案掩模部分的整个表面上形成遮光图案。

3. 发明申请

US20100104983A1 PATTERN FORMING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND EXPOSURE MASK SET 有权
标题翻译：图案形成方法，半导体器件制造方法和曝光掩模
公开(公告)号：US20100104983A1
公开(公告)日：2010-04-29
申请号：US12652470
申请日：2010-01-05
申请人： Takeo ISHIBASHI , Takayuki Saito , Maya Itoh , Shuji Nakao
发明人： Takeo ISHIBASHI , Takayuki Saito , Maya Itoh , Shuji Nakao
IPC分类号： G03F7/20
CPC分类号： G03F7/70466 , G03F1/00
摘要： First, a first exposure process is performed using dipole illumination with only a grating-pattern forming region as a substantial object to be exposed. Next, a second exposure process is performed with only a standard-pattern forming region as a substantial object to be exposed. A development process is then performed to obtain a resist pattern. A mask for the first exposure process is such that a light blocking pattern is formed on the whole surface of a standard-pattern mask part corresponding to the standard-pattern forming region. A mask for the second exposure is such that a light blocking pattern is formed on the whole surface of a grating-pattern mask part corresponding to the grating-pattern forming region.
摘要翻译：首先，使用仅具有光栅图案形成区域的偶极照明作为要暴露的实质对象来执行第一曝光处理。接下来，仅以标准图案形成区域作为要曝光的实质物体进行第二曝光处理。然后进行显影处理以获得抗蚀剂图案。用于第一曝光处理的掩模使得在对应于标准图案形成区域的标准图案掩模部件的整个表面上形成遮光图案。用于第二曝光的掩模使得在对应于光栅图案形成区域的光栅图案掩模部分的整个表面上形成遮光图案。

4. 发明授权

US07670756B2 Pattern forming method, semiconductor device manufacturing method and exposure mask set 有权
标题翻译：图案形成方法，半导体器件制造方法和曝光掩模组
公开(公告)号：US07670756B2
公开(公告)日：2010-03-02
申请号：US12271567
申请日：2008-11-14
申请人： Takeo Ishibashi , Takayuki Saito , Maya Itoh , Shuji Nakao
发明人： Takeo Ishibashi , Takayuki Saito , Maya Itoh , Shuji Nakao
IPC分类号： G03F7/00
CPC分类号： G03F7/70466 , G03F1/00
摘要： First, a first exposure process is performed using dipole illumination with only a grating-pattern forming region as a substantial object to be exposed. Next, a second exposure process is performed with only a standard-pattern forming region as a substantial object to be exposed. A development process is then performed to obtain a resist pattern. A mask for the first exposure process is such that a light blocking pattern is formed on the whole surface of a standard-pattern mask part corresponding to the standard-pattern forming region. A mask for the second exposure is such that a light blocking pattern is formed on the whole surface of a grating-pattern mask part corresponding to the grating-pattern forming region.
摘要翻译：首先，使用仅具有光栅图案形成区域的偶极照明作为要暴露的实质对象来执行第一曝光处理。接下来，仅以标准图案形成区域作为要曝光的实质物体进行第二曝光处理。然后进行显影处理以获得抗蚀剂图案。用于第一曝光处理的掩模使得在对应于标准图案形成区域的标准图案掩模部件的整个表面上形成遮光图案。用于第二曝光的掩模使得在对应于光栅图案形成区域的光栅图案掩模部分的整个表面上形成遮光图案。

5. 发明申请

US20090075187A1 PATTERN FORMING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND EXPOSURE MASK SET 有权
标题翻译：图案形成方法，半导体器件制造方法和曝光掩模
公开(公告)号：US20090075187A1
公开(公告)日：2009-03-19
申请号：US12271567
申请日：2008-11-14
申请人： Takeo Ishibashi , Takayuki Saito , Maya Itoh , Shuji Nakao
发明人： Takeo Ishibashi , Takayuki Saito , Maya Itoh , Shuji Nakao
IPC分类号： G03F1/00 , G03F7/20
CPC分类号： G03F7/70466 , G03F1/00
摘要： First, a first exposure process is performed using dipole illumination with only a grating-pattern forming region as a substantial object to be exposed. Next, a second exposure process is performed with only a standard-pattern forming region as a substantial object to be exposed. A development process is then performed to obtain a resist pattern. A mask for the first exposure process is such that a light blocking pattern is formed on the whole surface of a standard-pattern mask part corresponding to the standard-pattern forming region. A mask for the second exposure is such that a light blocking pattern is formed on the whole surface of a grating-pattern mask part corresponding to the grating-pattern forming region.
摘要翻译：首先，使用仅具有光栅图案形成区域的偶极照明作为要暴露的实质对象来执行第一曝光处理。接下来，仅以标准图案形成区域作为要曝光的实质物体进行第二曝光处理。然后进行显影处理以获得抗蚀剂图案。用于第一曝光处理的掩模使得在对应于标准图案形成区域的标准图案掩模部件的整个表面上形成遮光图案。用于第二曝光的掩模使得在对应于光栅图案形成区域的光栅图案掩模部分的整个表面上形成遮光图案。

6. 发明授权

US08017305B2 Pattern forming method, semiconductor device manufacturing method and exposure mask set 有权
标题翻译：图案形成方法，半导体器件制造方法和曝光掩模组
公开(公告)号：US08017305B2
公开(公告)日：2011-09-13
申请号：US12652470
申请日：2010-01-05
申请人： Takeo Ishibashi , Takayuki Saito , Maya Itoh , Shuji Nakao
发明人： Takeo Ishibashi , Takayuki Saito , Maya Itoh , Shuji Nakao
IPC分类号： G03F7/26
CPC分类号： G03F7/70466 , G03F1/00
摘要： First, a first exposure process is performed using dipole illumination with only a grating-pattern forming region as a substantial object to be exposed. Next, a second exposure process is performed with only a standard-pattern forming region as a substantial object to be exposed. A development process is then performed to obtain a resist pattern. A mask for the first exposure process is such that a light blocking pattern is formed on the whole surface of a standard-pattern mask part corresponding to the standard-pattern forming region. A mask for the second exposure is such that a light blocking pattern is formed on the whole surface of a grating-pattern mask part corresponding to the grating-pattern forming region.
摘要翻译：首先，使用仅具有光栅图案形成区域的偶极照明作为要暴露的实质对象来执行第一曝光处理。接下来，仅以标准图案形成区域作为要曝光的实质物体进行第二曝光处理。然后进行显影处理以获得抗蚀剂图案。用于第一曝光处理的掩模使得在对应于标准图案形成区域的标准图案掩模部件的整个表面上形成遮光图案。用于第二曝光的掩模使得在对应于光栅图案形成区域的光栅图案掩模部分的整个表面上形成遮光图案。

7. 发明授权

US06180320B2 Method of manufacturing a semiconductor device having a fine pattern, and semiconductor device manufactured thereby 失效
标题翻译：具有精细图案的半导体器件的制造方法以及由此制造的半导体器件
公开(公告)号：US06180320B2
公开(公告)日：2001-01-30
申请号：US09371499
申请日：1999-08-10
申请人： Takayuki Saito , Takeo Ishibashi , Toshiyuki Toyoshima , Kanji Sugino , Naoki Yasuda , Tadashi Miyagi
发明人： Takayuki Saito , Takeo Ishibashi , Toshiyuki Toyoshima , Kanji Sugino , Naoki Yasuda , Tadashi Miyagi
IPC分类号： G03F7039
CPC分类号： G03F7/40 , H01L21/0274 , H01L21/0338
摘要： There is described a method of stably manufacturing a fine resist pattern narrower than the wavelength of exposing light from a stepper. Under the method, a resist pattern is formed on a semiconductor substrate through use of an acid catalyst chemically-amplified photoresist, and an organic film which includes an acid or which produces an acid on exposure to light is formed on the surface of the semiconductor substrate including the resist pattern. The organic film is then subjected to a heat treatment to thereby diffuse an acid. The surface layer of the resist pattern is made soluble in an alkaline developer, and the surface layer of the resist pattern is removed through use of the alkaline developer. As a result, a fine resist pattern is formed.
摘要翻译：描述了一种稳定地制造比曝光来自步进器的光的波长窄的精细抗蚀剂图案的方法。在该方法下，通过使用酸催化剂化学扩增的光致抗蚀剂在半导体衬底上形成抗蚀剂图案，并且在半导体衬底的表面上形成包含酸或在曝光时产生酸的有机膜包括抗蚀剂图案。然后对有机膜进行热处理，从而扩散酸。抗蚀剂图案的表面层可溶于碱性显影剂，通过使用碱性显影剂除去抗蚀剂图案的表面层。结果，形成精细的抗蚀剂图案。

8. 发明申请

US20090039519A1 SEMICONDUCTOR DEVICE, PHOTOMASK, SEMICONDUCTOR DEVICE PRODUCTION METHOD, AND PATTERN LAYOUT METHOD 审中-公开
标题翻译：半导体器件，光电子器件，半导体器件生产方法和图案布局方法
公开(公告)号：US20090039519A1
公开(公告)日：2009-02-12
申请号：US12187786
申请日：2008-08-07
申请人： Takayuki Saito , Takeo Ishibashi , Itaru Kanai
发明人： Takayuki Saito , Takeo Ishibashi , Itaru Kanai
IPC分类号： H01L23/48 , G03F1/00
CPC分类号： G03F1/36 , G03F1/00 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to an aspect of the invention includes plural line pattern and plural pad patterns. The line patterns are repeatedly disposed with a space pattern interposed therebetween. The pad pattern straddles plural columns of the line patterns. The pad pattern is connected to the line pattern located on one side of the pad pattern in one of the plural columns, the pad pattern is connected to the line pattern located on the other side of the pad pattern in another column of the plural columns, and the line pattern located on one side of the pad pattern includes an open-circuit portion in another column. Therefore, a semiconductor device in which an interconnection pattern including the fine line-and-space-shape line pattern and the pad pattern is accurately formed at low cost, a semiconductor device production method, and a photomask used to produce the semiconductor device can be provided.
摘要翻译：根据本发明的一个方面的半导体器件包括多个线图案和多个衬垫图案。线图案重复地设置有插入其间的空间图案。焊盘图案跨越多列线图案。焊盘图案连接到位于多列之一中的焊盘图案的一侧的线图案，焊盘图案连接到位于多列的另一列中的焊盘图案另一侧的线图案，并且位于焊盘图案的一侧上的线图案包括另一列中的开路部分。因此，以低成本精确地形成包括细线和空间形线图案和焊盘图案的布线图形的半导体器件可以是用于制造半导体器件的半导体器件制造方法和光掩模提供。

9. 发明授权

US08573041B2 Mass air flow measurement device 有权
标题翻译：大气流量测量装置
公开(公告)号：US08573041B2
公开(公告)日：2013-11-05
申请号：US13314591
申请日：2011-12-08
申请人： Takayuki Saito , Takayuki Yogo , Shinya Igarashi , Hiromu Kikawa
发明人： Takayuki Saito , Takayuki Yogo , Shinya Igarashi , Hiromu Kikawa
IPC分类号： G01M15/04
CPC分类号： G01F1/6842 , G01F5/00 , H01L2224/48091 , H01L2924/00014
摘要： An arrangement of a mass intake air flow measurement device suitable for integrating a humidity sensing device as well as a temperature sensing device and a pressure sensing device is provided. A second bypass passage 501 bypassing a bypass passage 205 is formed and a humidity sensing device 500 is mounted in the second bypass passage 501. A second bypass passage inlet 502 and a second bypass passage outlet 503 formed in a wall surface of the bypass passage 205 are opened parallel to the direction of flow of air flowing in the bypass passage 205.
摘要翻译：提供了一种适合于集成湿度感测装置以及温度感测装置和压力感测装置的大量进气流量测量装置的布置。形成旁通旁路通路205的第二旁路通路501，在第二旁路通路501中安装湿度检测装置500.形成在旁通路205的壁面的第二旁路通路入口502和第二旁路通路出口503 平行于在旁路通路205中流动的空气的流动方向开口。

10. 发明授权

US08549901B2 Sensor structure 有权
标题翻译：传感器结构
公开(公告)号：US08549901B2
公开(公告)日：2013-10-08
申请号：US13367939
申请日：2012-02-07
申请人： Takayuki Saito , Keiji Hanzawa , Takayuki Yogo
发明人： Takayuki Saito , Keiji Hanzawa , Takayuki Yogo
IPC分类号： G01M15/04
CPC分类号： G01F1/6842 , F02D41/187 , G01F5/00
摘要： In relation to a humidity sensor sensitive to water and contamination, a sensor implementation structure that achieves both protection performance against water and contaminants and measurement performance such as humidity responsiveness is provided. A sensor structure has a mass airflow measurement element that measures a mass airflow flowing in an intake pipe, a humidity sensing element that senses humidity of air flowing in the intake pipe, a housing structural component having a connector that carries out input/output to/from outside and a terminal component of the connector, and a bypass passage that is composed by using part of the housing structural component and takes in part of the air that flows in the intake pipe, the mass airflow measurement element being mounted in the bypass passage; wherein space is provided in the housing structural component in the vicinity of the bypass passage, the humidity sensing element is mounted in the space.
摘要翻译：关于对水和污染物敏感的湿度传感器，提供了实现对水和污染物的保护性能以及诸如湿度响应性的测量性能的传感器实施结构。传感器结构具有测量进气管中流动的质量气流的质量气流测量元件，感测进气管中流动的空气湿度的湿度感测元件，具有连接器的壳体结构部件，该连接器将输入/ 从连接器的外部和端子部件和旁通通路构成，所述旁通通路由使用所述壳体结构部件的一部分而占据所述进气管中流动的一部分空气，所述质量空气流量测量元件安装在所述旁路通路 ; 其中在所述外壳结构部件中在所述旁通通路附近设置空间，所述湿度感测元件安装在所述空间中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式