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1. 发明申请

US20070236844A1 Semiconductor device and system 审中-公开
标题翻译：半导体器件和系统
公开(公告)号：US20070236844A1
公开(公告)日：2007-10-11
申请号：US11808083
申请日：2007-06-06
申请人： Takemi Negishi , Hiroaki Nambu , Kazuo Kanetani , Hideto Kazama
发明人： Takemi Negishi , Hiroaki Nambu , Kazuo Kanetani , Hideto Kazama
IPC分类号： H02H9/00
CPC分类号： H01L27/0251 , H01L27/0259 , H01L2924/0002 , H03K19/00315 , H01L2924/00
摘要： Disclosed herewith is a semiconductor device improved to prevent withstand voltage defects that might occur in each MOSFET used therein and a system to be designed easily and prevented from withstand voltage defects that might occur in each semiconductor used therein. The system includes the first and second input circuits, each being constituted by MOSFETs manufactured in the same process. The first input circuit receives a voltage of a first signal inputted from a first external terminal and divided by first and second resistor means while the AC component of the input signal is transmitted to the input circuit through a capacitor disposed in parallel to the first resistor means. The second input circuit receives a second input signal inputted from a second external terminal and reduced in signal amplitude so as to become smaller than that of the first input signal. The system also includes a second semiconductor device corresponding to the first input circuit and a third semiconductor device corresponding to the second input circuit.
摘要翻译：这里公开了一种改进的半导体器件，用于防止在其中使用的每个MOSFET中可能发生的耐受电压缺陷，以及容易设计的系统，并防止其中可能发生的每个半导体中可能发生的耐电压缺陷。该系统包括第一和第二输入电路，每个由相同工艺制造的MOSFET构成。第一输入电路接收从第一外部端子输入并由第一和第二电阻器装置分压的第一信号的电压，同时输入信号的AC分量通过与第一电阻器平行设置的电容器传输到输入电路。第二输入电路接收从第二外部端子输入的第二输入信号，并减小信号幅度，使其变得小于第一输入信号的输入信号。该系统还包括对应于第一输入电路的第二半导体器件和对应于第二输入电路的第三半导体器件。

2. 发明申请

US20050063112A1 Semiconductor device and system 有权
标题翻译：半导体器件和系统
公开(公告)号：US20050063112A1
公开(公告)日：2005-03-24
申请号：US10960985
申请日：2004-10-12
申请人： Takemi Negishi , Hiroaki Nambu , Kazuo Kanetani , Hideto Kazama
发明人： Takemi Negishi , Hiroaki Nambu , Kazuo Kanetani , Hideto Kazama
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H03K19/003 , H03K19/0175 , H02H9/00
CPC分类号： H01L27/0251 , H01L27/0259 , H01L2924/0002 , H03K19/00315 , H01L2924/00
摘要： Disclosed herewith is a semiconductor device improved to prevent withstand voltage defects that might occur in each MOSFET used therein and a system to be designed easily and prevented from withstand voltage defects that might occur in each semiconductor used therein. The system includes the first and second input circuits, each being constituted by MOSFETs manufactured in the same process. The first input circuit receives a voltage of a first signal inputted from a first external terminal and divided by first and second resistor means while the AC component of the input signal is transmitted to the input circuit through a capacitor disposed in parallel to the first resistor means. The second input circuit receives a second input signal inputted from a second external terminal and reduced in signal amplitude so as to become smaller than that of the first input signal. The system also includes a second semiconductor device corresponding to the first input circuit and a third semiconductor device corresponding to the second input circuit.
摘要翻译：这里公开了一种改进的半导体器件，用于防止在其中使用的每个MOSFET中可能发生的耐受电压缺陷，以及容易设计的系统，并防止其中可能发生的每个半导体中可能发生的耐电压缺陷。该系统包括第一和第二输入电路，每个由相同工艺制造的MOSFET构成。第一输入电路接收从第一外部端子输入并由第一和第二电阻器装置分压的第一信号的电压，同时输入信号的AC分量通过与第一电阻器平行设置的电容器传输到输入电路。第二输入电路接收从第二外部端子输入的第二输入信号，并减小信号幅度，使其变得小于第一输入信号的输入信号。该系统还包括对应于第一输入电路的第二半导体器件和对应于第二输入电路的第三半导体器件。

3. 发明授权

US07233045B2 Semiconductor device and system 有权
公开(公告)号：US07233045B2
公开(公告)日：2007-06-19
申请号：US10960985
申请日：2004-10-12
申请人： Takemi Negishi , Hiroaki Nambu , Kazuo Kanetani , Hideto Kazama
发明人： Takemi Negishi , Hiroaki Nambu , Kazuo Kanetani , Hideto Kazama
IPC分类号： H01L23/62
CPC分类号： H01L27/0251 , H01L27/0259 , H01L2924/0002 , H03K19/00315 , H01L2924/00
摘要： Disclosed herewith is a semiconductor device improved to prevent withstand voltage defects that might occur in each MOSFET used therein and a system to be designed easily and prevented from withstand voltage defects that might occur in each semiconductor used therein. The system includes the first and second input circuits, each being constituted by MOSFETs manufactured in the same process. The first input circuit receives a voltage of a first signal inputted from a first external terminal and divided by first and second resistor means while the AC component of the input signal is transmitted to the input circuit through a capacitor disposed in parallel to the first resistor means. The second input circuit receives a second input signal inputted from a second external terminal and reduced in signal amplitude so as to become smaller than that of the first input signal. The system also includes a second semiconductor device corresponding to the first input circuit and a third semiconductor device corresponding to the second input circuit.

4. 发明授权

US06806516B2 Semiconductor device and system 失效
标题翻译：半导体器件和系统
公开(公告)号：US06806516B2
公开(公告)日：2004-10-19
申请号：US10369683
申请日：2003-02-21
申请人： Takemi Negishi , Hiroaki Nambu , Kazuo Kanetani , Hideto Kazama
发明人： Takemi Negishi , Hiroaki Nambu , Kazuo Kanetani , Hideto Kazama
IPC分类号： H01L2710
CPC分类号： H01L27/0251 , H01L27/0259 , H01L2924/0002 , H03K19/00315 , H01L2924/00
摘要： Disclosed herewith is a semiconductor device improved to prevent withstand voltage defects that might occur in each MOSFET used therein and a system to be designed easily and prevented from withstand voltage defects that might occur in each semiconductor used therein. The system includes the first and second input circuits, each being constituted by MOSFETs manufactured in the same process. The first input circuit receives a voltage of a first signal inputted from a first external terminal and divided by first and second resistor means while the AC component of the input signal is transmitted to the input circuit through a capacitor disposed in parallel to the first resistor means. The second input circuit receives a second input signal inputted from a second external terminal and reduced in signal amplitude so as to become smaller than that of the first input signal. The system also includes a second semiconductor device corresponding to the first input circuit and a third semiconductor device corresponding to the second input circuit.
摘要翻译：这里公开了一种改进的半导体器件，用于防止在其中使用的每个MOSFET中可能发生的耐受电压缺陷，以及容易设计的系统，并防止其中可能发生的每个半导体中可能发生的耐电压缺陷。该系统包括第一和第二输入电路，每个由相同工艺制造的MOSFET构成。第一输入电路接收从第一外部端子输入并由第一和第二电阻器装置分压的第一信号的电压，同时输入信号的AC分量通过与第一电阻器平行设置的电容器传输到输入电路。第二输入电路接收从第二外部端子输入的第二输入信号，并减小信号幅度，使其变得小于第一输入信号的输入信号。该系统还包括对应于第一输入电路的第二半导体器件和对应于第二输入电路的第三半导体器件。

5. 发明授权

US07685455B2 Semiconductor integrated circuit which generates internal clock signal for fetching input data synchronously with the internal clock signal without decrease of timing margin 有权
标题翻译：半导体集成电路产生内部时钟信号，用于与内部时钟信号同步地提取输入数据，而不会减少定时裕度
公开(公告)号：US07685455B2
公开(公告)日：2010-03-23
申请号：US11936543
申请日：2007-11-07
申请人： Hiroaki Nambu , Masao Shinozaki , Kazuo Kanetani , Hideto Kazama
发明人： Hiroaki Nambu , Masao Shinozaki , Kazuo Kanetani , Hideto Kazama
IPC分类号： G06F1/04
CPC分类号： G11C11/413 , G06F1/04 , G11C11/419
摘要： A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input terminal for receiving a clock signal; a data input terminal for receiving a data signal; internal clock generating circuits for generating an internal clock signal which is switched at an intermediate timing between the i-th (i: an integer of 1 or larger) switch timing and the (i+1)th switch timing of the clock signal; and a latch circuit for latching the data signal synchronously with the internal clock signal. An internal clock signal which is switched at an intermediate timing between the i-th switch timing and the (i+1)th switch timing of the clock signal is generated, and the data signal is fetched synchronously with the internal clock signal.
摘要翻译：提供一种半导体集成电路，其中即使在时钟信号的占空比不同于50％的情况下，也可以防止用于取出数据的定时裕度。半导体集成电路包括：时钟输入端子，用于接收时钟信号; 用于接收数据信号的数据输入端; 内部时钟发生电路，用于产生在第i（i：1或更大的整数）切换定时与时钟信号的第（i + 1）切换定时之间的中间定时切换的内部时钟信号; 以及与内部时钟信号同步地锁存数据信号的锁存电路。产生在时钟信号的第i开关定时和第（i + 1）开关定时之间的中间定时切换的内部时钟信号，并且与内部时钟信号同步取出数据信号。

6. 发明申请

US20080072095A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20080072095A1
公开(公告)日：2008-03-20
申请号：US11936543
申请日：2007-11-07
申请人： Hiroaki Nambu , Masao Shinozaki , Kazuo Kanetani , Hideto Kazama
发明人： Hiroaki Nambu , Masao Shinozaki , Kazuo Kanetani , Hideto Kazama
IPC分类号： G06F1/12 , G06F13/42 , H04L5/00 , H04L7/00
CPC分类号： G11C11/413 , G06F1/04 , G11C11/419
摘要： A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input terminal for receiving a clock signal; a data input terminal for receiving a data signal; internal clock generating circuits for generating an internal clock signal which is switched at an intermediate timing between the i-th (i: an integer of 1 or larger) switch timing and the (i+1)th switch timing of the clock signal; and a latch circuit for latching the data signal synchronously with the internal clock signal. An internal clock signal which is switched at an intermediate timing between the i-th switch timing and the (i+1)th switch timing of the clock signal is generated, and the data signal is fetched synchronously with the internal clock signal.
摘要翻译：提供一种半导体集成电路，其中即使在时钟信号的占空比不同于50％的情况下，也可以防止用于取出数据的定时裕度。半导体集成电路包括：时钟输入端子，用于接收时钟信号; 用于接收数据信号的数据输入端; 内部时钟发生电路，用于产生在第i（i：1或更大的整数）切换定时与时钟信号的第（i + 1）切换定时之间的中间定时切换的内部时钟信号; 以及与内部时钟信号同步地锁存数据信号的锁存电路。产生在时钟信号的第i开关定时和第（i + 1）开关定时之间的中间定时切换的内部时钟信号，并且与内部时钟信号同步取出数据信号。

7. 发明授权

US07296173B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07296173B2
公开(公告)日：2007-11-13
申请号：US10768441
申请日：2004-02-02
申请人： Hiroaki Nambu , Masao Shinozaki , Kazuo Kanetani , Hideto Kazama
发明人： Hiroaki Nambu , Masao Shinozaki , Kazuo Kanetani , Hideto Kazama
IPC分类号： G06F1/12 , G06F13/42 , H04L5/00 , H04L7/00
CPC分类号： G11C11/413 , G06F1/04 , G11C11/419
摘要： A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input terminal for receiving a clock signal; a data input terminal for receiving a data signal; internal clock generating circuits for generating an internal clock signal which is switched at an intermediate timing between the i-th (i: an integer of 1 or larger) switch timing and the (i+1)th switch timing of the clock signal; and a latch circuit for latching the data signal synchronously with the internal clock signal. An internal clock signal which is switched at an intermediate timing between the i-th switch timing and the (i+1)th switch timing of the clock signal is generated, and the data signal is fetched synchronously with the internal clock signal.
摘要翻译：提供一种半导体集成电路，其中即使在时钟信号的占空比不同于50％的情况下，也可以防止用于取出数据的定时裕度。半导体集成电路包括：时钟输入端子，用于接收时钟信号; 用于接收数据信号的数据输入端; 内部时钟发生电路，用于产生在第i（i：1或更大的整数）切换定时与时钟信号的第（i + 1）切换定时之间的中间定时切换的内部时钟信号; 以及与内部时钟信号同步地锁存数据信号的锁存电路。产生在时钟信号的第i开关定时和第（i + 1）开关定时之间的中间定时切换的内部时钟信号，并且与内部时钟信号同步取出数据信号。

8. 发明授权

US06369617B1 Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit 失效
标题翻译：集成电路中使用的半导体集成电路和半导体逻辑电路
公开(公告)号：US06369617B1
公开(公告)日：2002-04-09
申请号：US09437268
申请日：1999-11-10
申请人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Takeshi Kusunoki , Keiichi Higeta , Kunihiko Yamaguchi , Fumihiko Arakawa
发明人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Takeshi Kusunoki , Keiichi Higeta , Kunihiko Yamaguchi , Fumihiko Arakawa
IPC分类号： G11C800
CPC分类号： G11C8/10
摘要： To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit include a semiconductor logic circuit wherein the number of columns of transistors for pulling down an output node is small even if the number of inputs is large, and the true output signal and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. By virtue of this arrangement, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and, in a semiconductor memory, for example, the reduction of access time and power consumption and the increase of the cycles are enabled.
摘要翻译：为了加速解码器电路的运行，降低解码器电路的功耗并增加周期，解码器电路中的每个电路如缓冲器，预解码器和主解码器都包括半导体逻辑电路，其中列数用于下拉输出节点的晶体管即使输入数量大也很小，并且获得具有大致相同延迟时间的真实输出信号和互补输出信号，并且解码器电路中的每个电路的输出脉冲长度为减少通过这种布置，解码器电路的工作可以加快，可以降低功耗，可以提高周期，并且在半导体存储器中，例如可以减少访问时间和功耗，并且增加的周期被启用。

9. 发明授权

US06316961B2 Clocked logic gate circuit 有权
公开(公告)号：US06316961B2
公开(公告)日：2001-11-13
申请号：US09725812
申请日：2000-11-30
申请人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Noboru Masuda , Kenji Kaneko , Makoto Hanawa , Takeshi Kusunoki
发明人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Noboru Masuda , Kenji Kaneko , Makoto Hanawa , Takeshi Kusunoki
IPC分类号： H03K19096
CPC分类号： H03K19/0963 , H03K19/1738
摘要： A clocked logic gate circuit is constituted so that a switch unit is constituted by a logic block and a reference MOS transistor, the source of the reference MOS transistor is connected to one output of the logic block, the gate of the reference MOS transistor is connected to the other output of the logic block, and MOS transistors (input transistors) constituting the logic block are connected in parallel. With this arrangement, complementary inputs are not required and a driving MOS transistor and an input transistor (or a driving MOS transistor and a reference MOS transistor) can be connected in series. As a result, a circuit is obtained which is simpler than the double rail logic in constitution is facilitated and can be operated at a higher speed than a CMOS logic circuit and a path transistor logic circuit.

10. 发明授权

US5398201A Bit-line drive circuit for a semiconductor memory 失效
标题翻译：半导体存储器的位线驱动电路
公开(公告)号：US5398201A
公开(公告)日：1995-03-14
申请号：US53330
申请日：1993-04-28
申请人： Hiroaki Nambu , Noriyuki Homma , Kunihiko Yamaguchi , Hisayuki Higuchi , Kazuo Kanetani , Youji Idei , Ken'ichi Ohata , Yoshiaki Sakurai , Masanori Odaka , Goro Kitsukawa
发明人： Hiroaki Nambu , Noriyuki Homma , Kunihiko Yamaguchi , Hisayuki Higuchi , Kazuo Kanetani , Youji Idei , Ken'ichi Ohata , Yoshiaki Sakurai , Masanori Odaka , Goro Kitsukawa
IPC分类号： G11C5/14 , G11C7/10 , G11C11/34
CPC分类号： G11C7/1057 , G11C5/147 , G11C7/1051 , G11C7/1078 , G11C7/1084
摘要： A circuit technique suitable to attain a high speed of a memory which is constructed in a manner such that memory cells include a field effect transistor and peripheral circuits include a bipolar transistor and a field effect transistor. According to the invention, a bipolar transistor whose collector is connected to a differential amplifier and which supplies a current to the differential amplifier in accordance with a signal which is inputted to a base or an emitter is added, and a bipolar transistor to supply a current only when writing to bit lines is connected. According to the invention, a high speed of the access time when information is read out by switching the selection bit line is accomplished. Further, the charge/discharge time of the bit line when information is written is reduced and a high speed of the writing time can be also accomplished. The improvement of the drivers of word lines and bit lines is also disclosed and a semiconductor memory which can operate at a high speed as a whole semiconductor memory can be realized.
摘要翻译：一种适于实现存储器的高速的电路技术，其以使得存储器单元包括场效应晶体管和外围电路的方式构造，包括双极晶体管和场效应晶体管。根据本发明，将集电极连接到差分放大器并根据输入到基极或发射极的信号向差分放大器提供电流的双极晶体管和双极晶体管，以提供电流只有写入位线才能连接。根据本发明，通过切换选择位线来读取信息时的访问时间的高速度被实现。此外，当写入信息时位线的充电/放电时间减少，并且也可以实现高速的写入时间。还公开了字线和位线的驱动器的改进，并且可以实现可以作为整个半导体存储器以高速度操作的半导体存储器。

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