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1. 发明授权

US06316961B2 Clocked logic gate circuit 有权
公开(公告)号：US06316961B2
公开(公告)日：2001-11-13
申请号：US09725812
申请日：2000-11-30
申请人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Noboru Masuda , Kenji Kaneko , Makoto Hanawa , Takeshi Kusunoki
发明人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Noboru Masuda , Kenji Kaneko , Makoto Hanawa , Takeshi Kusunoki
IPC分类号： H03K19096
CPC分类号： H03K19/0963 , H03K19/1738
摘要： A clocked logic gate circuit is constituted so that a switch unit is constituted by a logic block and a reference MOS transistor, the source of the reference MOS transistor is connected to one output of the logic block, the gate of the reference MOS transistor is connected to the other output of the logic block, and MOS transistors (input transistors) constituting the logic block are connected in parallel. With this arrangement, complementary inputs are not required and a driving MOS transistor and an input transistor (or a driving MOS transistor and a reference MOS transistor) can be connected in series. As a result, a circuit is obtained which is simpler than the double rail logic in constitution is facilitated and can be operated at a higher speed than a CMOS logic circuit and a path transistor logic circuit.

2. 发明授权

US06476644B2 Clocked logic gate circuit 有权
标题翻译：时钟逻辑门电路
公开(公告)号：US06476644B2
公开(公告)日：2002-11-05
申请号：US09725450
申请日：2000-11-30
申请人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Noboru Masuda , Kenji Kaneko , Makoto Hanawa , Takeshi Kusunoki
发明人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Noboru Masuda , Kenji Kaneko , Makoto Hanawa , Takeshi Kusunoki
IPC分类号： G11C800
CPC分类号： H03K19/0963 , H03K19/1738
摘要： A clocked logic gate circuit is constituted so that a switch unit is constituted by a logic block and a reference MOS transistor, the source of the reference MOS transistor is connected to one output of the logic block, the gate of the reference MOS transistor is connected to the other output of the logic block, and MOS transistors (input transistors) constituting the logic block are connected in parallel. With this arrangement, complementary inputs are not required and a driving MOS transistor and an input transistor (or a driving MOS transistor and a reference MOS transistor) can be connected in series. As a result, a circuit is obtained which is simpler than the double rail logic in constitution is facilitated and can be operated at a higher speed than a CMOS logic circuit and a path transistor logic circuit.
摘要翻译：构成时钟逻辑门电路，使得开关单元由逻辑块和参考MOS晶体管构成，参考MOS晶体管的源极连接到逻辑块的一个输出端，参考MOS晶体管的栅极被连接到逻辑块的另一个输出端，构成逻辑块的MOS晶体管（输入晶体管）并联连接。通过这种布置，不需要互补的输入，并且驱动MOS晶体管和输入晶体管（或驱动MOS晶体管和参考MOS晶体管）可以串联连接。结果，获得比构成便利的双轨逻辑简单的电路，并且可以以比CMOS逻辑电路和路径晶体管逻辑电路更高的速度工作。

3. 发明授权

US06333645B1 Clocked logic gate circuit 有权
公开(公告)号：US06333645B1
公开(公告)日：2001-12-25
申请号：US09659541
申请日：2000-09-11
申请人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Noboru Masuda , Kenji Kaneko , Makoto Hanawa , Takeshi Kusunoki
发明人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Noboru Masuda , Kenji Kaneko , Makoto Hanawa , Takeshi Kusunoki
IPC分类号： H03K19096
CPC分类号： H03K19/0963 , H03K19/1738
摘要： A clocked logic gate circuit is constituted so that a switch unit is constituted by a logic block and a reference MOS transistor, the source of the reference MOS transistor is connected to one output of the logic block, the gate of the reference MOS transistor is connected to the other output of the logic block, and MOS transistors (input transistors) constituting the logic block are connected in parallel. With this arrangement, complementary inputs are not required and a driving MOS transistor and an input transistor (or a driving MOS transistor and a reference MOS transistor) can be connected in series. As a result, a circuit is obtained which is simpler than the double rail logic in constitution is facilitated and can be operated at a higher speed than a CMOS logic circuit and a path transistor logic circuit.

4. 发明授权

US06369617B1 Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit 失效
标题翻译：集成电路中使用的半导体集成电路和半导体逻辑电路
公开(公告)号：US06369617B1
公开(公告)日：2002-04-09
申请号：US09437268
申请日：1999-11-10
申请人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Takeshi Kusunoki , Keiichi Higeta , Kunihiko Yamaguchi , Fumihiko Arakawa
发明人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Takeshi Kusunoki , Keiichi Higeta , Kunihiko Yamaguchi , Fumihiko Arakawa
IPC分类号： G11C800
CPC分类号： G11C8/10
摘要： To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit include a semiconductor logic circuit wherein the number of columns of transistors for pulling down an output node is small even if the number of inputs is large, and the true output signal and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. By virtue of this arrangement, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and, in a semiconductor memory, for example, the reduction of access time and power consumption and the increase of the cycles are enabled.
摘要翻译：为了加速解码器电路的运行，降低解码器电路的功耗并增加周期，解码器电路中的每个电路如缓冲器，预解码器和主解码器都包括半导体逻辑电路，其中列数用于下拉输出节点的晶体管即使输入数量大也很小，并且获得具有大致相同延迟时间的真实输出信号和互补输出信号，并且解码器电路中的每个电路的输出脉冲长度为减少通过这种布置，解码器电路的工作可以加快，可以降低功耗，可以提高周期，并且在半导体存储器中，例如可以减少访问时间和功耗，并且增加的周期被启用。

5. 发明授权

US06998878B2 Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit 失效
标题翻译：集成电路中使用的半导体集成电路和半导体逻辑电路
公开(公告)号：US06998878B2
公开(公告)日：2006-02-14
申请号：US10754596
申请日：2004-01-12
申请人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Takeshi Kusunoki , Keiichi Higeta , Kunihiko Yamaguchi , Fumihiko Arakawa
发明人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Takeshi Kusunoki , Keiichi Higeta , Kunihiko Yamaguchi , Fumihiko Arakawa
IPC分类号： H03K19/20
CPC分类号： G11C8/10
摘要： To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit includes a semiconductor logic circuit in which the number of columns of transistors for pulling down at an output node is small, even if the number of inputs is many and the true and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. With this arrangement, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and, in a semiconductor memory, for example, access time and power consumption can be reduced and the cycles can be increased.
摘要翻译：为了加速解码器电路的运行，降低解码器电路的功耗并增加周期，解码器电路中的每个电路如缓冲器，预解码器和主译码器都包括半导体逻辑电路，其中，在输出节点下拉的晶体管列很小，即使输入数量很多，并且获得了真实的和具有大致相同延迟时间的互补输出信号，并且解码器电路中每个电路的输出脉冲长度是减少利用这种布置，可以加速解码器电路的操作，可以降低功耗，可以提高周期，例如，在半导体存储器中，可以减少访问时间和功耗，并且可以将周期增加。

6. 发明授权

US06438050B1 Signal transmission circuit and semiconductor memory using the same 失效
标题翻译：信号传输电路和半导体存储器使用相同
公开(公告)号：US06438050B1
公开(公告)日：2002-08-20
申请号：US10038914
申请日：2002-01-08
申请人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Takeshi Kusunoki , Fumihiko Arakawa
发明人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Takeshi Kusunoki , Fumihiko Arakawa
IPC分类号： G11C700
CPC分类号： H03K3/356139
摘要： A transmission circuit for transmitting a data signal between circuit units through a signal wire. The data signal is transmitted for precharging the signal wire to high potential during a precharge period and discharging it to low potential according to data transmitted during an evaluation period or keeping the signal wire as it is. Latch type Source-Coupled-Logic is configured so that a first node and a second node used as an output terminal to the next stage are respectively charged together to high potential during the precharge period. The second node is discharged according to a potential at the first node during the evaluation period, and the first node is discharged according to a potential on the signal wire. Thus, the operation of discharging the signal wire by the driver circuit can be sped up.
摘要翻译：一种用于通过信号线在电路单元之间传输数据信号的传输电路。发送数据信号，用于在预充电期间将信号线预充电到高电位，并根据在评估期间传输的数据将其放电到低电位，或保持信号线原样。锁存型源耦合逻辑被配置为使得用作下一级的输出端的第一节点和第二节点在预充电周期期间分别充电到高电位。第二节点在评估期间根据第一节点的电位放电，第一节点根据信号线上的电位放电。因此，可以加快由驱动电路对信号线进行放电的动作。

7. 发明授权

US06807115B2 Method of testing a semiconductor integrated device 失效
标题翻译：测试半导体集成器件的方法
公开(公告)号：US06807115B2
公开(公告)日：2004-10-19
申请号：US10360867
申请日：2003-02-10
申请人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Fumihiko Arakawa , Takeshi Kusunoki , Keiichi Higeta
发明人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Fumihiko Arakawa , Takeshi Kusunoki , Keiichi Higeta
IPC分类号： G11C700
CPC分类号： G01R31/31701
摘要： In a dynamic-type semiconductor integrated circuit in which precharge and evaluation operations are preformed per cycle, an IDDQ test and a light detection test can be conducted during an evaluation period for facilitating diagnosis and failure analysis so as to increase test accuracy. The dynamic-type semiconductor integrated circuit operates in a normal operation mode or a test mode, wherein a switch therebetween is triggered by a mode selection signal. In the normal operation mode, the pulse width of an internal activation signal is controlled to be constant, i.e., invariable with an operation cycle time length. In the test mode, the pulse width of the internal activation signal is controlled to vary according to an operation cycle time length.
摘要翻译：在每个周期执行预充电和评估操作的动态型半导体集成电路中，可以在评估期间进行IDDQ测试和光检测测试，以便于诊断和故障分析，从而提高测试精度。动态型半导体集成电路在正常操作模式或测试模式下工作，其中其间的开关由模式选择信号触发。在正常工作模式中，内部激活信号的脉冲宽度被控制为恒定的，即，以操作周期时间长度不变。在测试模式中，内部激活信号的脉冲宽度被控制以根据操作周期时间长度而变化。

8. 发明授权

US06337581B1 Signal transmission circuit and semiconductor memory using the same 失效
标题翻译：信号传输电路和半导体存储器使用相同
公开(公告)号：US06337581B1
公开(公告)日：2002-01-08
申请号：US09599738
申请日：2000-06-23
申请人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Takeshi Kusunoki , Fumihiko Arakawa
发明人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Takeshi Kusunoki , Fumihiko Arakawa
IPC分类号： H03K190185
CPC分类号： H03K3/356139
摘要： Disclosed herein is a transmission circuit for transmitting a data signal between circuit units on a semiconductor integrated circuit through a signal wire. The data signal is transmitted by a driver circuit for precharging the signal wire to a high potential during a precharge period and discharging the signal wire to a low potential according to data to be transmitted during an evaluation period or keeping the signal wire at a high potential as floating as it is. Latch type Source-Coupled-Logic configured so that a first node and a second node used as an output terminal to the next stage are respectively charged together to a high potential during the precharge period, the second node is discharged according to a potential at the first node during the evaluation period, and the first node is discharged according to a potential on the signal wire, is used as a receiving circuit, whereby a distinction as to a high or low level of the potential on the signal wire is made with early timing provided to perform the operation of discharging the signal wire by the driver circuit.
摘要翻译：这里公开了一种用于通过信号线在半导体集成电路上的电路单元之间传输数据信号的发送电路。数据信号由驱动电路传输，用于在预充电期间将信号线预充电到高电位，并根据在评估期间要发送的数据将信号线放电到低电位，或者将信号线保持在高电位像浮动一样。锁存型源耦合逻辑被配置为使得用作到下一级的输出端的第一节点和第二节点在预充电周期期间分别充电到高电位，第二节点根据在在评估期间的第一节点和第一节点根据信号线上的电位放电，被用作接收电路，从而对信号线上的电位的高电平或低电平进行区分以提前提供用于执行由驱动器电路放电信号线的操作的定时。

9. 发明授权

US06677782B2 Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit 有权
标题翻译：集成电路中使用的半导体集成电路和半导体逻辑电路
公开(公告)号：US06677782B2
公开(公告)日：2004-01-13
申请号：US09840190
申请日：2001-04-24
申请人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Takeshi Kusunoki , Keiichi Higeta , Kunihiko Yamaguchi , Fumihiko Arakawa
发明人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Takeshi Kusunoki , Keiichi Higeta , Kunihiko Yamaguchi , Fumihiko Arakawa
IPC分类号： H03K19096
CPC分类号： G11C8/10
摘要： To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit is composed by a semiconductor logic circuit wherein the number of columns of transistors for pulling down at an output node is small even if the number of inputs is many and the true and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. According to the present invention, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and in a semiconductor memory for example, the reduction of access time and power consumption and the increase of the cycles are enabled.
摘要翻译：为了加快解码电路的运行，解码电路的功耗降低，周期增加，解码电路中的缓冲器，预解码器，主译码器等电路由半导体逻辑电路构成，用于在输出节点下拉的晶体管的列较小，即使输入数量多，并且获得具有大致相同延迟时间的真实和互补输出信号，并且解码器电路中的每个电路的输出脉冲长度为根据本发明，可以加速解码器电路的操作，可以降低功耗，可以增加周期，并且在半导体存储器中，例如，减少访问时间和功耗以及增加的周期被启用。

10. 发明授权

US06229745B1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US06229745B1
公开(公告)日：2001-05-08
申请号：US09558375
申请日：2000-04-26
申请人： Hiroaki Nambu , Kazuo Kanetani , Kaname Yamasaki , Fumihiko Arakawa , Takeshi Kusunoki
发明人： Hiroaki Nambu , Kazuo Kanetani , Kaname Yamasaki , Fumihiko Arakawa , Takeshi Kusunoki
IPC分类号： G11C702
CPC分类号： G11C7/06
摘要： A semiconductor memory in accordance with the present invention includes a sense amplifier composed of a plurality of MOS transistors. When the sense amplifier is on standby, a first control circuit brings an input signal of the sense amplifier to zero. A second control circuit uses voltages developed because of an offset voltage occurring in the sense amplifier to feed back the potentials in the wells of the MOS transistors so that the offset voltage will be nullified. When the offset voltage occurring in the sense amplifier is nullified, a delay time required by the sense amplifier is shortened. This results in the high-speed semiconductor memory.
摘要翻译：根据本发明的半导体存储器包括由多个MOS晶体管组成的读出放大器。当读出放大器处于待机状态时，第一个控制电路使读出放大器的输入信号为零。第二控制电路使用由于读出放大器中发生的偏移电压而产生的电压反馈MOS晶体管的阱中的电位，使得偏移电压将被无效。当读出放大器中发生的失调电压无效时，读出放大器所需的延迟时间缩短。这导致高速半导体存储器。

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