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1. 发明授权

US5398201A Bit-line drive circuit for a semiconductor memory 失效
标题翻译：半导体存储器的位线驱动电路
公开(公告)号：US5398201A
公开(公告)日：1995-03-14
申请号：US53330
申请日：1993-04-28
申请人： Hiroaki Nambu , Noriyuki Homma , Kunihiko Yamaguchi , Hisayuki Higuchi , Kazuo Kanetani , Youji Idei , Ken'ichi Ohata , Yoshiaki Sakurai , Masanori Odaka , Goro Kitsukawa
发明人： Hiroaki Nambu , Noriyuki Homma , Kunihiko Yamaguchi , Hisayuki Higuchi , Kazuo Kanetani , Youji Idei , Ken'ichi Ohata , Yoshiaki Sakurai , Masanori Odaka , Goro Kitsukawa
IPC分类号： G11C5/14 , G11C7/10 , G11C11/34
CPC分类号： G11C7/1057 , G11C5/147 , G11C7/1051 , G11C7/1078 , G11C7/1084
摘要： A circuit technique suitable to attain a high speed of a memory which is constructed in a manner such that memory cells include a field effect transistor and peripheral circuits include a bipolar transistor and a field effect transistor. According to the invention, a bipolar transistor whose collector is connected to a differential amplifier and which supplies a current to the differential amplifier in accordance with a signal which is inputted to a base or an emitter is added, and a bipolar transistor to supply a current only when writing to bit lines is connected. According to the invention, a high speed of the access time when information is read out by switching the selection bit line is accomplished. Further, the charge/discharge time of the bit line when information is written is reduced and a high speed of the writing time can be also accomplished. The improvement of the drivers of word lines and bit lines is also disclosed and a semiconductor memory which can operate at a high speed as a whole semiconductor memory can be realized.
摘要翻译：一种适于实现存储器的高速的电路技术，其以使得存储器单元包括场效应晶体管和外围电路的方式构造，包括双极晶体管和场效应晶体管。根据本发明，将集电极连接到差分放大器并根据输入到基极或发射极的信号向差分放大器提供电流的双极晶体管和双极晶体管，以提供电流只有写入位线才能连接。根据本发明，通过切换选择位线来读取信息时的访问时间的高速度被实现。此外，当写入信息时位线的充电/放电时间减少，并且也可以实现高速的写入时间。还公开了字线和位线的驱动器的改进，并且可以实现可以作为整个半导体存储器以高速度操作的半导体存储器。

2. 发明授权

US5255225A Semiconductor integrated circuit device and memory consisting of semiconductor integrated circuit 失效
标题翻译：半导体集成电路器件和存储器由半导体集成电路组成
公开(公告)号：US5255225A
公开(公告)日：1993-10-19
申请号：US845557
申请日：1992-03-04
申请人： Hiroaki Nambu , Noriyuki Homma , Kunihiko Yamaguchi , Kazuo Kanetani , Hisayuki Higuchi , Youji Idei , Kenichi Ohata , Yoshiaki Sakurai , Masanori Odaka , Goro Kitsukawa , Nobuo Tamba , Masayuki Ohayashi , Toshiro Hiramoto , Kayoko Saito
发明人： Hiroaki Nambu , Noriyuki Homma , Kunihiko Yamaguchi , Kazuo Kanetani , Hisayuki Higuchi , Youji Idei , Kenichi Ohata , Yoshiaki Sakurai , Masanori Odaka , Goro Kitsukawa , Nobuo Tamba , Masayuki Ohayashi , Toshiro Hiramoto , Kayoko Saito
IPC分类号： G11C5/14 , G11C7/10 , G11C11/40
CPC分类号： G11C7/1057 , G11C5/147 , G11C7/1051 , G11C7/1078 , G11C7/1084
摘要： A semiconductor integrated circuit device including a level conversion circuit in which the simplifying of the circuit and the increasing of the speed of operation have been attained is provided.A pair of complementary output signals amplified to a required signal level by a current switch circuit including differential transistors which receive an input signal and a reference voltage are inputted into a pair of emitter follower circuits. An emitter follower output transistor is driven by an output signal from one emitter follower circuit, while an N-channel MOSFET provided between the output transistor and a current source used as a load is driven by an output signal from the other emitter follower circuit, to obtain a level-amplified output signal from an emitter of the output transistor.The speed of an operation of the circuit device can be increased to a high level owing to a simple circuit in which a level, which is required to attain an output amplitude, of complementary output signals is secured by the current switch circuit, the amplified complementary signals being inputted into the emitter follower circuit to directly drive the output transistor.
摘要翻译：提供一种包括电平转换电路的半导体集成电路器件，其中电路的简化和操作速度的提高已经达到。通过包括接收输入信号和参考电压的差分晶体管的电流开关电路将被放大到所需信号电平的一对互补输出信号输入到一对发射极跟随器电路中。射极跟随器输出晶体管由来自一个射极跟随器电路的输出信号驱动，而在输出晶体管和用作负载的电流源之间提供的N沟道MOSFET由另一个射极跟随器电路的输出信号驱动到从输出晶体管的发射极获得电平放大的输出信号。电路装置的运行速度可以通过电流开关电路确保互补输出信号的达到输出幅度所需的电平的简单电路而增加到高电平，放大的互补信号被输入射极跟随器电路以直接驱动输出晶体管。

3. 发明授权

US5163022A Semiconductor cell memory with current sensing 失效
标题翻译：具有电流检测功能的半导体单元存储器
公开(公告)号：US5163022A
公开(公告)日：1992-11-10
申请号：US827873
申请日：1992-01-30
申请人： Noriyuki Homma , Hiroaki Nambu , Kunihiko Yamaguchi , Tohru Nakamura , Youji Idei , Kazuo Kanetani , Kenichi Ohhata , Yoshiaki Sakurai , Hisayuki Higuchi
发明人： Noriyuki Homma , Hiroaki Nambu , Kunihiko Yamaguchi , Tohru Nakamura , Youji Idei , Kazuo Kanetani , Kenichi Ohhata , Yoshiaki Sakurai , Hisayuki Higuchi
IPC分类号： G11C7/06 , G11C11/411 , G11C11/412 , G11C11/416 , G11C11/419
CPC分类号： G11C11/4113 , G11C11/412 , G11C11/416 , G11C11/419 , G11C7/062
摘要： The disclosure includes feeding a current I.sub.R to only BIT lines selected, or feeding current I.sub.R transiently to only the BIT lines switched from unselected to selected states; and a sense amplifier for detecting the difference between the currents flowing in selected BIT lines to read out stored information, wherein current I.sub.R and cell current I.sub.cell have a relation of I.sub.R >I.sub.cell. The BiC MOS memory has high speed, low power and high integration density. Diodes are provided between the memory cell and the BIT lines.
摘要翻译：本公开包括将电流IR馈送到仅选择的BIT线，或者将电流IR瞬时馈送到仅从未选择状态切换到选定状态的BIT线; 以及读出放大器，用于检测在所选择的BIT行中流动的电流之间的差以读出存储的信息，其中当前的IR和单元电流Icell具有IR> Icell的关系。 BiC MOS存储器具有高速度，低功耗和高集成度。在存储单元和BIT线之间提供二极管。

4. 发明授权

US5086414A Semiconductor device having latch means 失效
标题翻译：具有锁存装置的半导体装置
公开(公告)号：US5086414A
公开(公告)日：1992-02-04
申请号：US436770
申请日：1989-11-15
申请人： Hiroaki Nambu , Noriyuki Homma , Kunihiko Yamaguchi , Kazuo Kanetani , Youji Idei , Kenichi Ohhata , Yoshiaki Sakurai , Jun Etoh
发明人： Hiroaki Nambu , Noriyuki Homma , Kunihiko Yamaguchi , Kazuo Kanetani , Youji Idei , Kenichi Ohhata , Yoshiaki Sakurai , Jun Etoh
IPC分类号： G11C7/22 , G11C8/18 , H03K3/2885 , H03K3/356
CPC分类号： G11C7/22 , G11C8/18 , H03K3/2885 , H03K3/356113 , H03K3/356156
摘要： A semiconductor circuit having a plurality of circuit blocks, each having latch circuits each one thereof being controlled by an internally provided clock signal for preventing malfunction of the circuit. Each circuit is provided with the latch function so that the cycle time is made shorter than the access time. Moreover, the latch means are driven in such a manner that the adjoining ones are prevented from being put to through-state simultaneously, whereby malfunction is prevented.
摘要翻译：具有多个电路块的半导体电路，每个具有锁存电路，每个电路块由内部提供的时钟信号控制，用于防止电路的故障。每个电路都具有锁存功能，使得周期时间短于访问时间。此外，锁定装置被驱动，使得相邻的锁定装置被阻止同时被置于通过状态，从而防止了故障。

5. 发明授权

US5448527A Decoder and driver for use in a semiconductor memory 失效
标题翻译：用于半导体存储器的解码器和驱动器
公开(公告)号：US5448527A
公开(公告)日：1995-09-05
申请号：US149936
申请日：1993-11-10
申请人： Hiroaki Nambu , Noriyuki Homma , Kazuo Kanetani , Youji Idei , Kenichi Ohhata , Takesi Kusunoki
发明人： Hiroaki Nambu , Noriyuki Homma , Kazuo Kanetani , Youji Idei , Kenichi Ohhata , Takesi Kusunoki
IPC分类号： G11C11/413 , G11C8/08 , G11C8/10 , G11C8/00
CPC分类号： G11C8/10 , G11C8/08
摘要： A decoder formed of multiple circuit blocks each including bipolar transistors Q1 and Q2 having their collectors connected to resistors R1 and R2, respectively, a bipolar transistor Q3 having its collector supplied with a power voltage, and a current source I1 connected commonly to the emitters of Q1-Q3. This circuit configuration permits the decoder and BiCMOS memories using it to operate with a low supply voltage.
摘要翻译：由多个电路块形成的解码器，每个电路块分别包括双极晶体管Q1和Q2，它们的集电极分别连接到电阻器R1和R2，其集电极被提供有电源电压的双极晶体管Q3和共同连接到发射极的发射极 Q1-Q3。该电路配置允许使用它的解码器和BiCMOS存储器以低电源电压工作。

6. 发明授权

US5523966A Memory cell and a memory device having reduced soft error 失效
标题翻译：存储单元和具有降低的软错误的存储器件
公开(公告)号：US5523966A
公开(公告)日：1996-06-04
申请号：US530421
申请日：1995-09-18
申请人： Youji Idei , Hiroaki Nambu , Kazuo Kanetani , Toru Masuda , Kunihiko Yamaguchi , Kenichi Ohhata , Takeshi Kusunoki
发明人： Youji Idei , Hiroaki Nambu , Kazuo Kanetani , Toru Masuda , Kunihiko Yamaguchi , Kenichi Ohhata , Takeshi Kusunoki
IPC分类号： G11C11/41 , G11C11/412 , H01L21/8244 , H01L27/11 , G11C11/00
CPC分类号： G11C11/4125 , H01L27/11 , H01L27/1104
摘要： Disclosed is a static type memory cell with high immunity from alpha ray-induced soft errors. The memory cell has a coupling capacitance C.sub.c between two data storage nodes 1 and 2. The p-well (or p-substrate) in which the driver-MOS transistors MN3, MN4 and the transfer MOS transistors MN1, MN2 are formed is connected to a V.sub.bb generator. The voltage V.sub.bb is set lower than the low level V.sub.L of the memory cell signal potential. Even when the potential variation .DELTA.V.sub.L of the low-voltage side node 2 is large, the parasitic diode present between the n-type diffusion layer corresponding to the source or drain of MN1-MN4 and the p-well (or p-substrate) does not turn on. Erroneous operations can therefore be prevented.
摘要翻译：公开了一种具有高抗α射线诱导的软错误免疫力的静态型记忆体。存储单元在两个数据存储节点1和2之间具有耦合电容Cc。其中形成驱动器MOS晶体管MN3，MN4和传输MOS晶体管MN1，MN2的p阱（或p衬底）连接到一个Vbb发生器。电压Vbb被设定为低于存储单元信号电位的低电平VL。即使当低电压侧节点2的电位变化量DELTA VL大时，存在于与MN1-MN4的源极或漏极对应的n型扩散层与p阱（或p-衬底）之间的寄生二极管，不打开因此可以防止错误的操作。

7. 发明授权

US5402377A Semiconductor memory device having a controlled auxiliary decoder 失效
标题翻译：具有受控辅助解码器的半导体存储器件
公开(公告)号：US5402377A
公开(公告)日：1995-03-28
申请号：US243908
申请日：1994-05-17
申请人： Kenichi Ohhata , Hiroaki Nambu , Kazuo Kanetani , Youji Idei , Takeshi Kusunoki , Toru Masuda
发明人： Kenichi Ohhata , Hiroaki Nambu , Kazuo Kanetani , Youji Idei , Takeshi Kusunoki , Toru Masuda
IPC分类号： G11C29/00 , G11C29/04 , G11C8/00
CPC分类号： G11C29/70
摘要： A semiconductor memory device has a primary memory cell array, a primary decoder having a first circuit producing an intermediate signal from an address signal and a second circuit producing a first cell selection signal from the intermediate signal for selectively driving a word line and a bit line, an auxiliary memory cell array having a plurality of memory cells, each being used for a defective memory cell found in the primary memory cell array, an auxiliary decoder connected to the primary decoder to receive the intermediate signal, a non-volatile memory for storing first information indicating that the primary memory cell array contains a defective memory cell from which a cell defect signal is produced and for storing second information indicating an address of the defective memory cell from which a defective cell address signal is produced, and a control circuit responsive to the cell defect signal and the defective cell address signal for producing a first control signal to be supplied to the second circuit and a second control signal to be supplied to the auxiliary decoder. The primary decoder is prohibited by the first control signal from accessing a defective memory cell having an address represented by the defective cell address signal. The auxiliary decoder produces a second cell selection signal from the intermediate signal under control of the second control signal and of the cell defect signal for selectively accessing a memory cell in the auxiliary memory cell array.
摘要翻译：半导体存储器件具有主存储单元阵列，主解码器具有产生来自地址信号的中间信号的第一电路和从该中间信号产生第一单元选择信号的第二电路，用于选择性地驱动字线和位线，具有多个存储单元的辅助存储单元阵列，每个存储单元用于存储在主存储单元阵列中的缺陷存储单元，连接到主解码器以接收中间信号的辅助解码器，用于存储的非易失性存储器指示主存储单元阵列包含产生单元缺陷信号的缺陷存储单元的第一信息，以及用于存储表示产生有缺陷单元地址信号的缺陷存储单元的地址的第二信息，以及响应于控制电路的控制电路到单元缺陷信号和用于产生第一控制信号的有缺陷单元地址信号提供给第二电路和第二控制信号以提供给辅助解码器。主解码器被第一控制信号禁止访问具有由缺陷单元地址信号表示的地址的有缺陷的存储单元。辅助解码器在第二控制信号和单元缺陷信号的控制下，从中间信号产生第二单元选择信号，用于选择性地访问辅助存储单元阵列中的存储单元。

8. 发明授权

US5926430A Semiconductor integrated circuit device and method of activating the same 失效
标题翻译：半导体集成电路器件及其激活方法
公开(公告)号：US5926430A
公开(公告)日：1999-07-20
申请号：US985425
申请日：1997-12-05
申请人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
发明人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
IPC分类号： G11C11/407 , G11C5/14 , G11C11/4074 , H03K19/00 , H03K17/16
CPC分类号： G11C5/14 , G11C11/4074 , G11C5/147 , H03K19/0016
摘要： A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon reaching its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.
摘要翻译：动态RAM被分成响应于从外部端子提供的输入信号的输入电路块，包括操作开始信号，响应于从输入电路块输入的信号而被激活的内部电路块，以及输出电路块用于将从内部电路块输出的信号输出到外部端子。在用于施加从外部端子提供的工作电压的电力线和用于内部电路块中的第一电路部分的内部电力线的并行设置多个开关MOSFET，其在达到其非电压时不需要存储操作操作状态。此外，响应于通过延迟通过输入电路块提供的启动信号而产生的控制信号，开关MOSFET逐步导通，以便执行每个工作电压的供应。

9. 发明授权

US06396761B2 Semiconductor integrated circuit device and method of activating the same 有权
标题翻译：半导体集成电路器件及其激活方法
公开(公告)号：US06396761B2
公开(公告)日：2002-05-28
申请号：US09875169
申请日：2001-06-07
申请人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
发明人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
IPC分类号： G11C700
CPC分类号： G11C5/14 , G11C5/147 , G11C11/4074 , H03K19/0016
摘要： A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.
摘要翻译：动态RAM被分成响应于从外部端子提供的输入信号的输入电路块，包括操作开始信号，响应于从输入电路块输入的信号而被激活的内部电路块，以及输出电路块用于将从内部电路块输出的信号输出到外部端子。在用于施加从外部端子提供的工作电压的电力线和用于内部电路块中的第一电路部分的内部电力线之间的并行形式提供多个开关MOSFET，其不需要在其非正常状态下的存储操作操作状态。此外，响应于通过延迟通过输入电路块提供的启动信号而产生的控制信号，开关MOSFET逐步导通，以便执行每个工作电压的供应。

10. 发明授权

US06385100B2 Semiconductor memory device with improved column selecting operation 有权
标题翻译：具有改进的列选择操作的半导体存储器件
公开(公告)号：US06385100B2
公开(公告)日：2002-05-07
申请号：US09789753
申请日：2001-02-22
申请人： Hiromasa Noda , Youji Idei , Osamu Nagashima , Tetsuo Ado
发明人： Hiromasa Noda , Youji Idei , Osamu Nagashima , Tetsuo Ado
IPC分类号： G11C700
CPC分类号： G11C29/84 , G11C7/1027 , G11C8/04 , G11C11/4087
摘要： A semiconductor memory device has a column address decoder which includes first and second pre-decoders corresponding to high-order and low-order addresses, respectively, a shift register for using the output signal of the second pre-decoder as an initial value, and an output circuit for selecting either the output signal of the second pre-decoder or the output signal of the shift register in accordance with an action mode. The select signal is formed by the output signal of the first pre-decoder and the output signal through the output circuit. The shift register includes a first shift register for an even address and a second shift register for an odd address and forms two sets of continuous select signals of the bit lines, as composed of a sequential action and an interleave action, on the basis of the initial value by combining its up and down shifting actions.
摘要翻译：一种半导体存储器件具有列地址解码器，它包括分别对应于高阶和低阶地址的第一和第二预解码器，用于使用第二预解码器的输出信号作为初始值的移位寄存器，以及输出电路，用于根据动作模式选择第二预解码器的输出信号或移位寄存器的输出信号。选择信号由第一预解码器的输出信号和通过输出电路的输出信号形成。移位寄存器包括用于偶数地址的第一移位寄存器和奇数地址的第二移位寄存器，并且基于顺序动作和交错动作形成位线的两组连续选择信号通过组合其上下移动动作的初始值。

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