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1. 发明授权

US06806516B2 Semiconductor device and system 失效
标题翻译：半导体器件和系统
公开(公告)号：US06806516B2
公开(公告)日：2004-10-19
申请号：US10369683
申请日：2003-02-21
申请人： Takemi Negishi , Hiroaki Nambu , Kazuo Kanetani , Hideto Kazama
发明人： Takemi Negishi , Hiroaki Nambu , Kazuo Kanetani , Hideto Kazama
IPC分类号： H01L2710
CPC分类号： H01L27/0251 , H01L27/0259 , H01L2924/0002 , H03K19/00315 , H01L2924/00
摘要： Disclosed herewith is a semiconductor device improved to prevent withstand voltage defects that might occur in each MOSFET used therein and a system to be designed easily and prevented from withstand voltage defects that might occur in each semiconductor used therein. The system includes the first and second input circuits, each being constituted by MOSFETs manufactured in the same process. The first input circuit receives a voltage of a first signal inputted from a first external terminal and divided by first and second resistor means while the AC component of the input signal is transmitted to the input circuit through a capacitor disposed in parallel to the first resistor means. The second input circuit receives a second input signal inputted from a second external terminal and reduced in signal amplitude so as to become smaller than that of the first input signal. The system also includes a second semiconductor device corresponding to the first input circuit and a third semiconductor device corresponding to the second input circuit.
摘要翻译：这里公开了一种改进的半导体器件，用于防止在其中使用的每个MOSFET中可能发生的耐受电压缺陷，以及容易设计的系统，并防止其中可能发生的每个半导体中可能发生的耐电压缺陷。该系统包括第一和第二输入电路，每个由相同工艺制造的MOSFET构成。第一输入电路接收从第一外部端子输入并由第一和第二电阻器装置分压的第一信号的电压，同时输入信号的AC分量通过与第一电阻器平行设置的电容器传输到输入电路。第二输入电路接收从第二外部端子输入的第二输入信号，并减小信号幅度，使其变得小于第一输入信号的输入信号。该系统还包括对应于第一输入电路的第二半导体器件和对应于第二输入电路的第三半导体器件。

2. 发明授权

US07233045B2 Semiconductor device and system 有权
公开(公告)号：US07233045B2
公开(公告)日：2007-06-19
申请号：US10960985
申请日：2004-10-12
申请人： Takemi Negishi , Hiroaki Nambu , Kazuo Kanetani , Hideto Kazama
发明人： Takemi Negishi , Hiroaki Nambu , Kazuo Kanetani , Hideto Kazama
IPC分类号： H01L23/62
CPC分类号： H01L27/0251 , H01L27/0259 , H01L2924/0002 , H03K19/00315 , H01L2924/00
摘要： Disclosed herewith is a semiconductor device improved to prevent withstand voltage defects that might occur in each MOSFET used therein and a system to be designed easily and prevented from withstand voltage defects that might occur in each semiconductor used therein. The system includes the first and second input circuits, each being constituted by MOSFETs manufactured in the same process. The first input circuit receives a voltage of a first signal inputted from a first external terminal and divided by first and second resistor means while the AC component of the input signal is transmitted to the input circuit through a capacitor disposed in parallel to the first resistor means. The second input circuit receives a second input signal inputted from a second external terminal and reduced in signal amplitude so as to become smaller than that of the first input signal. The system also includes a second semiconductor device corresponding to the first input circuit and a third semiconductor device corresponding to the second input circuit.

3. 发明申请

US20070236844A1 Semiconductor device and system 审中-公开
标题翻译：半导体器件和系统
公开(公告)号：US20070236844A1
公开(公告)日：2007-10-11
申请号：US11808083
申请日：2007-06-06
申请人： Takemi Negishi , Hiroaki Nambu , Kazuo Kanetani , Hideto Kazama
发明人： Takemi Negishi , Hiroaki Nambu , Kazuo Kanetani , Hideto Kazama
IPC分类号： H02H9/00
CPC分类号： H01L27/0251 , H01L27/0259 , H01L2924/0002 , H03K19/00315 , H01L2924/00
摘要： Disclosed herewith is a semiconductor device improved to prevent withstand voltage defects that might occur in each MOSFET used therein and a system to be designed easily and prevented from withstand voltage defects that might occur in each semiconductor used therein. The system includes the first and second input circuits, each being constituted by MOSFETs manufactured in the same process. The first input circuit receives a voltage of a first signal inputted from a first external terminal and divided by first and second resistor means while the AC component of the input signal is transmitted to the input circuit through a capacitor disposed in parallel to the first resistor means. The second input circuit receives a second input signal inputted from a second external terminal and reduced in signal amplitude so as to become smaller than that of the first input signal. The system also includes a second semiconductor device corresponding to the first input circuit and a third semiconductor device corresponding to the second input circuit.
摘要翻译：这里公开了一种改进的半导体器件，用于防止在其中使用的每个MOSFET中可能发生的耐受电压缺陷，以及容易设计的系统，并防止其中可能发生的每个半导体中可能发生的耐电压缺陷。该系统包括第一和第二输入电路，每个由相同工艺制造的MOSFET构成。第一输入电路接收从第一外部端子输入并由第一和第二电阻器装置分压的第一信号的电压，同时输入信号的AC分量通过与第一电阻器平行设置的电容器传输到输入电路。第二输入电路接收从第二外部端子输入的第二输入信号，并减小信号幅度，使其变得小于第一输入信号的输入信号。该系统还包括对应于第一输入电路的第二半导体器件和对应于第二输入电路的第三半导体器件。

4. 发明申请

US20050063112A1 Semiconductor device and system 有权
标题翻译：半导体器件和系统
公开(公告)号：US20050063112A1
公开(公告)日：2005-03-24
申请号：US10960985
申请日：2004-10-12
申请人： Takemi Negishi , Hiroaki Nambu , Kazuo Kanetani , Hideto Kazama
发明人： Takemi Negishi , Hiroaki Nambu , Kazuo Kanetani , Hideto Kazama
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H03K19/003 , H03K19/0175 , H02H9/00
CPC分类号： H01L27/0251 , H01L27/0259 , H01L2924/0002 , H03K19/00315 , H01L2924/00
摘要： Disclosed herewith is a semiconductor device improved to prevent withstand voltage defects that might occur in each MOSFET used therein and a system to be designed easily and prevented from withstand voltage defects that might occur in each semiconductor used therein. The system includes the first and second input circuits, each being constituted by MOSFETs manufactured in the same process. The first input circuit receives a voltage of a first signal inputted from a first external terminal and divided by first and second resistor means while the AC component of the input signal is transmitted to the input circuit through a capacitor disposed in parallel to the first resistor means. The second input circuit receives a second input signal inputted from a second external terminal and reduced in signal amplitude so as to become smaller than that of the first input signal. The system also includes a second semiconductor device corresponding to the first input circuit and a third semiconductor device corresponding to the second input circuit.
摘要翻译：这里公开了一种改进的半导体器件，用于防止在其中使用的每个MOSFET中可能发生的耐受电压缺陷，以及容易设计的系统，并防止其中可能发生的每个半导体中可能发生的耐电压缺陷。该系统包括第一和第二输入电路，每个由相同工艺制造的MOSFET构成。第一输入电路接收从第一外部端子输入并由第一和第二电阻器装置分压的第一信号的电压，同时输入信号的AC分量通过与第一电阻器平行设置的电容器传输到输入电路。第二输入电路接收从第二外部端子输入的第二输入信号，并减小信号幅度，使其变得小于第一输入信号的输入信号。该系统还包括对应于第一输入电路的第二半导体器件和对应于第二输入电路的第三半导体器件。

5. 发明授权

US07296173B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07296173B2
公开(公告)日：2007-11-13
申请号：US10768441
申请日：2004-02-02
申请人： Hiroaki Nambu , Masao Shinozaki , Kazuo Kanetani , Hideto Kazama
发明人： Hiroaki Nambu , Masao Shinozaki , Kazuo Kanetani , Hideto Kazama
IPC分类号： G06F1/12 , G06F13/42 , H04L5/00 , H04L7/00
CPC分类号： G11C11/413 , G06F1/04 , G11C11/419
摘要： A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input terminal for receiving a clock signal; a data input terminal for receiving a data signal; internal clock generating circuits for generating an internal clock signal which is switched at an intermediate timing between the i-th (i: an integer of 1 or larger) switch timing and the (i+1)th switch timing of the clock signal; and a latch circuit for latching the data signal synchronously with the internal clock signal. An internal clock signal which is switched at an intermediate timing between the i-th switch timing and the (i+1)th switch timing of the clock signal is generated, and the data signal is fetched synchronously with the internal clock signal.
摘要翻译：提供一种半导体集成电路，其中即使在时钟信号的占空比不同于50％的情况下，也可以防止用于取出数据的定时裕度。半导体集成电路包括：时钟输入端子，用于接收时钟信号; 用于接收数据信号的数据输入端; 内部时钟发生电路，用于产生在第i（i：1或更大的整数）切换定时与时钟信号的第（i + 1）切换定时之间的中间定时切换的内部时钟信号; 以及与内部时钟信号同步地锁存数据信号的锁存电路。产生在时钟信号的第i开关定时和第（i + 1）开关定时之间的中间定时切换的内部时钟信号，并且与内部时钟信号同步取出数据信号。

6. 发明申请

US20080072095A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20080072095A1
公开(公告)日：2008-03-20
申请号：US11936543
申请日：2007-11-07
申请人： Hiroaki Nambu , Masao Shinozaki , Kazuo Kanetani , Hideto Kazama
发明人： Hiroaki Nambu , Masao Shinozaki , Kazuo Kanetani , Hideto Kazama
IPC分类号： G06F1/12 , G06F13/42 , H04L5/00 , H04L7/00
CPC分类号： G11C11/413 , G06F1/04 , G11C11/419
摘要： A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input terminal for receiving a clock signal; a data input terminal for receiving a data signal; internal clock generating circuits for generating an internal clock signal which is switched at an intermediate timing between the i-th (i: an integer of 1 or larger) switch timing and the (i+1)th switch timing of the clock signal; and a latch circuit for latching the data signal synchronously with the internal clock signal. An internal clock signal which is switched at an intermediate timing between the i-th switch timing and the (i+1)th switch timing of the clock signal is generated, and the data signal is fetched synchronously with the internal clock signal.
摘要翻译：提供一种半导体集成电路，其中即使在时钟信号的占空比不同于50％的情况下，也可以防止用于取出数据的定时裕度。半导体集成电路包括：时钟输入端子，用于接收时钟信号; 用于接收数据信号的数据输入端; 内部时钟发生电路，用于产生在第i（i：1或更大的整数）切换定时与时钟信号的第（i + 1）切换定时之间的中间定时切换的内部时钟信号; 以及与内部时钟信号同步地锁存数据信号的锁存电路。产生在时钟信号的第i开关定时和第（i + 1）开关定时之间的中间定时切换的内部时钟信号，并且与内部时钟信号同步取出数据信号。

7. 发明授权

US07685455B2 Semiconductor integrated circuit which generates internal clock signal for fetching input data synchronously with the internal clock signal without decrease of timing margin 有权
标题翻译：半导体集成电路产生内部时钟信号，用于与内部时钟信号同步地提取输入数据，而不会减少定时裕度
公开(公告)号：US07685455B2
公开(公告)日：2010-03-23
申请号：US11936543
申请日：2007-11-07
申请人： Hiroaki Nambu , Masao Shinozaki , Kazuo Kanetani , Hideto Kazama
发明人： Hiroaki Nambu , Masao Shinozaki , Kazuo Kanetani , Hideto Kazama
IPC分类号： G06F1/04
CPC分类号： G11C11/413 , G06F1/04 , G11C11/419
摘要： A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input terminal for receiving a clock signal; a data input terminal for receiving a data signal; internal clock generating circuits for generating an internal clock signal which is switched at an intermediate timing between the i-th (i: an integer of 1 or larger) switch timing and the (i+1)th switch timing of the clock signal; and a latch circuit for latching the data signal synchronously with the internal clock signal. An internal clock signal which is switched at an intermediate timing between the i-th switch timing and the (i+1)th switch timing of the clock signal is generated, and the data signal is fetched synchronously with the internal clock signal.
摘要翻译：提供一种半导体集成电路，其中即使在时钟信号的占空比不同于50％的情况下，也可以防止用于取出数据的定时裕度。半导体集成电路包括：时钟输入端子，用于接收时钟信号; 用于接收数据信号的数据输入端; 内部时钟发生电路，用于产生在第i（i：1或更大的整数）切换定时与时钟信号的第（i + 1）切换定时之间的中间定时切换的内部时钟信号; 以及与内部时钟信号同步地锁存数据信号的锁存电路。产生在时钟信号的第i开关定时和第（i + 1）开关定时之间的中间定时切换的内部时钟信号，并且与内部时钟信号同步取出数据信号。

8. 发明授权

US07022563B2 Semiconductor integrated circuit device and a method of manufacturing the same 失效
公开(公告)号：US07022563B2
公开(公告)日：2006-04-04
申请号：US10846872
申请日：2004-05-17
申请人： Fumio Ootsuka , Yusuke Nonaka , Satoshi Shimamoto , Sohei Omori , Hideto Kazama
发明人： Fumio Ootsuka , Yusuke Nonaka , Satoshi Shimamoto , Sohei Omori , Hideto Kazama
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/00 , H01L21/48
CPC分类号： H01L27/11 , H01L27/1104
摘要： In order to improve the performance of a semiconductor integrated circuit device wherein a capacitor provided between storage nodes of an SRAM and a device having an analog capacitor are formed on a single substrate, a plug is formed in a silicon oxide film on a pair of n channel type MISFETs in a memory cell forming area, and a local wiring LIc for connecting respective gate electrodes and drains of the pair of n channel type MISFETs is formed over the silicon oxide film and the plug. Thereafter, a capacitive insulating film and an upper electrode are further formed over the local wiring LIc. According to the same process step as the local wiring, capacitive insulating film and upper electrode formed in the memory cell forming area, a local wiring LIc, a capacitive insulating film and an upper electrode are formed over a silicon oxide film in an analog capacitor forming area and a plug in the silicon oxide film.

9. 发明授权

US5734616A Semiconductor memory device and sense circuit 失效
标题翻译：半导体存储器件和感测电路
公开(公告)号：US5734616A
公开(公告)日：1998-03-31
申请号：US694059
申请日：1996-08-08
申请人： Hideto Kazama , Shuichi Miyaoka , Akihiko Emori , Kinya Mitsumoto , Tomoyuki Someya , Masahiro Iwamura , Noboru Akiyama
发明人： Hideto Kazama , Shuichi Miyaoka , Akihiko Emori , Kinya Mitsumoto , Tomoyuki Someya , Masahiro Iwamura , Noboru Akiyama
IPC分类号： G11C11/419 , G11C7/00
CPC分类号： G11C11/419
摘要： A static RAM includes pre-amplifiers, which are made up solely of emitter-follower transistors having their collectors supplied with the power voltage, in one-to-one correspondence to sub common data line pairs which are connected by column switches to complementary data line pairs of memory arrays. The pre-amplifier is provided with a first switch which turns on during the selected state to connect the sub common data line pair to the bases of the transistors and a second switch which turns on during the unselected state to provide the bases with a certain bias voltage lower than the readout signal voltage on the sub common data line pair. The emitter-follower transistors have their emitters connected commonly to form common emitter lines, which are connected to pairs of input terminals of main amplifiers made up of CMOS transistors.
摘要翻译：静态RAM包括前置放大器，其仅由具有其电源电压的集电极的射极跟随器晶体管组成，与通过列开关连接到互补数据线的子公共数据线对一一对应成对的存储器阵列。前置放大器设置有在选择状态期间导通的第一开关，以将子公共数据线对连接到晶体管的基极;以及第二开关，其在未选择状态期间导通，以向基极提供一定的偏置电压低于副公共数据线对上的读出信号电压。射极跟随器晶体管的发射极共同连接形成共同的发射极线，其连接到由CMOS晶体管构成的主放大器的输入端对。

10. 发明授权

US06762444B2 Semiconductor integrated circuit device and a method of manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06762444B2
公开(公告)日：2004-07-13
申请号：US10308001
申请日：2002-12-03
申请人： Fumio Ootsuka , Yusuke Nonaka , Satoshi Shimamoto , Sohei Omori , Hideto Kazama
发明人： Fumio Ootsuka , Yusuke Nonaka , Satoshi Shimamoto , Sohei Omori , Hideto Kazama
IPC分类号： H01L21336
CPC分类号： H01L27/11 , H01L27/1104
摘要： In order to improve the performance of a semiconductor integrated circuit device wherein a capacitor provided between storage nodes of an SRAM and a device having an analog capacitor are formed on a single substrate, a plug is formed in a silicon oxide film on a pair of n channel type MISFETs in a memory cell forming area, and a local wiring LIc for connecting respective gate electrodes and drains of the pair of n channel type MISFETs is formed over the silicon oxide film and the plug. Thereafter, a capacitive insulating film and an upper electrode are further formed over the local wiring LIc. According to the same process step as the local wiring, capacitive insulating film and upper electrode formed in the memory cell forming area, a local wiring LIc, a capacitive insulating film and an upper electrode are formed over a silicon oxide film in an analog capacitor forming area and a plug in the silicon oxide film.
摘要翻译：为了提高半导体集成电路器件的性能，其中在单个衬底上形成在SRAM的存储节点和具有模拟电容器的器件之间提供的电容器，在一对n上的氧化硅膜中形成插头存储单元形成区域中的沟道型MISFET以及用于连接该n沟道型MISFET的各个栅电极和漏极的局部布线LIc形成在氧化硅膜和插塞上。此后，在本地布线LIc上进一步形成电容绝缘膜和上电极。根据与形成在存储单元形成区域中的局部布线，电容绝缘膜和上电极，局部布线LIc，电容绝缘膜和上电极相同的处理步骤，形成在模拟电容器形成中的氧化硅膜上区域并插入氧化硅膜。

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