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1. 发明申请

US20070243701A1 Semiconductor device fabrication method using ultra-rapid thermal annealing 审中-公开
标题翻译：半导体器件制造方法采用超快速热退火
公开(公告)号：US20070243701A1
公开(公告)日：2007-10-18
申请号：US11783035
申请日：2007-04-05
申请人： Takayuki Ito , Kyoichi Suguro , Takaharu Itani , Yoshihiko Saito
发明人： Takayuki Ito , Kyoichi Suguro , Takaharu Itani , Yoshihiko Saito
IPC分类号： H01L21/425
CPC分类号： H01L21/2686 , H01L21/324 , H01L29/7833 , H01L29/7842
摘要： An impurity is ion-implanted into the major surface of an Si substrate having a bulk microdefect density of 5×106 to 5×107 cm−3, a bulk microdefect size smaller than 100 nm, and a dissolved oxygen concentration of 1.1×1018 to 1.2×1018 cm−3. The Si substrate then undergoes ultra-rapid thermal annealing whose heating/cooling rate is higher than 1×105° C./sec, thereby electrically activating the impurity to form at least a partial impurity diffusion layer of a semiconductor element.
摘要翻译：将杂质离子注入到具有体积微密度为5×10 -6至5×10 -7 cm -3以下的Si衬底的主表面中，体积微观尺寸小于100nm，溶解氧浓度为1.1×10 18至1.2×10 -8 cm -3。然后，Si衬底经历其加热/冷却速率高于1×10 5℃/秒的超快速热退火，从而电激活杂质以形成半导体的至少部分杂质扩散层元件。

2. 发明授权

US07279405B2 Fabrication method for semiconductor device and manufacturing apparatus for the same 有权
标题翻译：半导体装置及其制造装置的制造方法
公开(公告)号：US07279405B2
公开(公告)日：2007-10-09
申请号：US10980232
申请日：2004-11-04
申请人： Takaharu Itani , Takayuki Ito , Kyoichi Suguro
发明人： Takaharu Itani , Takayuki Ito , Kyoichi Suguro
IPC分类号： H01L21/425
CPC分类号： H01L21/26533 , H01L21/324 , H01L29/6659
摘要： A shallow p-n junction diffusion layer having a high activation rate of implanted ions, low resistivity, and a controlled leakage current is formed through annealing. Annealing after impurities have been doped is carried out through light irradiation. Those impurities are activated by annealing at least twice through light irradiation after doping impurities to a semiconductor substrate 11. The light radiations are characterized by usage of a W halogen lamp RTA or a flash lamp FLA except for the final light irradiation using a flash lamp FLA. Impurity diffusion maybe controlled to a minimum, and crystal defects, which have developed in an impurity doping process, may be sufficiently reduced when forming ion implanted layers in a source and a drain extension region of the MOSFET or ion implanted layers in a source and a drain region.
摘要翻译：通过退火形成具有注入离子的高激活速率，低电阻率和受控的漏电流的浅p-n结扩散层。通过光照射进行杂质掺杂后的退火。这些杂质通过在将杂质掺杂到半导体衬底11之后通过光照射退火至少两次来激活。光辐射的特征在于使用W卤素灯RTA或闪光灯FLA，除了使用闪光灯FLA的最终光照射。杂质扩散可以被控制到最小，并且当在MOSFET的源极和漏极延伸区域中形成离子注入层时，在杂质掺杂过程中已经发展出的晶体缺陷可以被充分地减小，或者源中的离子注入层和漏区。

3. 发明授权

US08211785B2 Fabrication method for semiconductor device including flash lamp annealing processes 有权
标题翻译：包括闪光灯退火工艺的半导体器件的制造方法
公开(公告)号：US08211785B2
公开(公告)日：2012-07-03
申请号：US11819776
申请日：2007-06-29
申请人： Takaharu Itani , Takayuki Ito , Kyoichi Suguro
发明人： Takaharu Itani , Takayuki Ito , Kyoichi Suguro
IPC分类号： H01L21/425
CPC分类号： H01L21/26533 , H01L21/324 , H01L29/6659
摘要： A shallow p-n junction diffusion layer having a high activation rate of implanted ions, low resistivity, and a controlled leakage current is formed through annealing. Annealing after impurities have been doped is carried out through light irradiation. Those impurities are activated by annealing at least twice through light irradiation after doping impurities to a semiconductor substrate 11. The light radiations are characterized by usage of a W halogen lamp RTA or a flash lamp FLA except for the final light irradiation using a flash lamp FLA. Impurity diffusion may be controlled to a minimum, and crystal defects, which have developed in an impurity doping process, may be sufficiently reduced when forming ion implanted layers in a source and a drain extension region of the MOSFET or ion implanted layers in a source and a drain region.
摘要翻译：通过退火形成具有注入离子的高激活速率，低电阻率和受控的漏电流的浅p-n结扩散层。通过光照射进行杂质掺杂后的退火。这些杂质通过在将杂质掺杂到半导体衬底11之后通过光照射退火至少两次来激活。光辐射的特征在于使用W卤素灯RTA或闪光灯FLA，除了使用闪光灯FLA的最终光照射。杂质扩散可以被控制到最小，并且当在源的源极和漏极延伸区域中形成离子注入层时，或者在源中的离子注入层形成离子注入层时，杂质掺杂过程中已经形成的晶体缺陷可以被充分地减小，以及漏极区域。

4. 发明授权

US07084068B2 Annealing furnace, manufacturing apparatus, annealing method and manufacturing method of electronic device 失效
标题翻译：退火炉，制造装置，退火方法和电子装置的制造方法
公开(公告)号：US07084068B2
公开(公告)日：2006-08-01
申请号：US10661564
申请日：2003-09-15
申请人： Kyoichi Suguro , Takayuki Ito , Takaharu Itani
发明人： Kyoichi Suguro , Takayuki Ito , Takaharu Itani
IPC分类号： H01L21/302 , H01L21/461 , C23C16/00
CPC分类号： H01L21/28185 , H01L21/02046 , H01L21/02233 , H01L21/02247 , H01L21/28202 , H01L21/28211 , H01L21/28238 , H01L21/3144 , H01L21/32 , H01L21/67115 , H01L21/67155 , H01L21/823462 , H01L29/513 , H01L29/518
摘要： An annealing furnace, includes a processing chamber configured to store a substrate; a susceptor located in the processing chamber so as to load the substrate and having an auxiliary heater for heating the substrate at 650° C. or less, the susceptor having a surface being made of quartz; a gas supply system configured to supply a gas required for a thermal processing on the substrate in parallel to a surface of the substrate; a transparent window located on an upper part of the processing chamber facing the susceptor; and a main heater configured to irradiate a pulsed light on the surface of the substrate to heat the substrate from the transparent window, the pulsed light having a pulse duration of approximately 0.1 ms to 200 ms and having a plurality of emission wavelengths.
摘要翻译：一种退火炉，包括：配置成存储基板的处理室; 位于所述处理室中的基座，以便加载所述基板并具有用于在650℃以下加热所述基板的辅助加热器，所述基座具有由石英制成的表面; 气体供给系统，被配置为平行于所述基板的表面在所述基板上供给热处理所需的气体; 位于处理室的与感受器相对的上部的透明窗口; 以及主加热器，其被配置为在所述基板的表面上照射脉冲光以从所述透明窗加热所述基板，所述脉冲光具有约0.1ms至200ms的脉冲持续时间并且具有多个发射波长。

5. 发明申请

US20080260501A1 Fabrication method for semiconductor device and manufacturing apparatus for the same 有权
标题翻译：半导体装置及其制造装置的制造方法
公开(公告)号：US20080260501A1
公开(公告)日：2008-10-23
申请号：US11819776
申请日：2007-06-29
申请人： Takaharu Itani , Takayuki Ito , Kyoichi Suguro
发明人： Takaharu Itani , Takayuki Ito , Kyoichi Suguro
IPC分类号： H01L21/677
CPC分类号： H01L21/26533 , H01L21/324 , H01L29/6659
摘要： A shallow p-n junction diffusion layer having a high activation rate of implanted ions, low resistivity, and a controlled leakage current is formed through annealing. Annealing after impurities have been doped is carried out through light irradiation. Those impurities are activated by annealing at least twice through light irradiation after doping impurities to a semiconductor substrate 11. The light radiations are characterized by usage of a W halogen lamp RTA or a flash lamp FLA except for the final light irradiation using a flash lamp FLA. Impurity diffusion may be controlled to a minimum, and crystal defects, which have developed in an impurity doping process, may be sufficiently reduced when forming ion implanted layers in a source and a drain extension region of the MOSFET or ion implanted layers in a source and a drain region.
摘要翻译：通过退火形成具有注入离子的高激活速率，低电阻率和受控的漏电流的浅p-n结扩散层。通过光照射进行杂质掺杂后的退火。通过在将杂质掺杂到半导体衬底11之后通过光照射退火至少两次来激活这些杂质。除了使用闪光灯FLA的最终光照射之外，光辐射的特征在于使用W卤素灯RTA或闪光灯FLA。杂质扩散可以被控制到最小，并且当在源的源极和漏极延伸区域中形成离子注入层或在源中的离子注入层形成离子注入层时，可以充分减少在杂质掺杂过程中发展的晶体缺陷，以及漏极区域。

6. 发明申请

US20050124123A1 Fabrication method for semiconductor device and manufacturing apparatus for the same 有权
标题翻译：半导体装置及其制造装置的制造方法
公开(公告)号：US20050124123A1
公开(公告)日：2005-06-09
申请号：US10980232
申请日：2004-11-04
申请人： Takaharu Itani , Takayuki Ito , Kyoichi Suguro
发明人： Takaharu Itani , Takayuki Ito , Kyoichi Suguro
IPC分类号： H01L21/265 , H01L21/324 , H01L21/336 , H01L29/78 , F27B3/20 , F27B7/34 , F27B9/36 , H01L21/26 , H01L21/42 , H01L21/477
CPC分类号： H01L21/26533 , H01L21/324 , H01L29/6659
摘要： A shallow p-n junction diffusion layer having a high activation rate of implanted ions, low resistivity, and a controlled leakage current is formed through annealing. Annealing after impurities have been doped is carried out through light irradiation. Those impurities are activated by annealing at least twice through light irradiation after doping impurities to a semiconductor substrate 11. The light radiations are characterized by usage of a W halogen lamp RTA or a flash lamp FLA except for the final light irradiation using a flash lamp FLA. Impurity diffusion maybe controlled to a minimum, and crystal defects, which have developed in an impurity doping process, may be sufficiently reduced when forming ion implanted layers in a source and a drain extension region of the MOSFET or ion implanted layers in a source and a drain region.
摘要翻译：通过退火形成具有注入离子的高激活速率，低电阻率和受控的漏电流的浅p-n结扩散层。通过光照射进行杂质掺杂后的退火。这些杂质通过在将杂质掺杂到半导体衬底11之后通过光照射退火至少两次来激活。光辐射的特征在于使用W卤素灯RTA或闪光灯FLA，除了使用闪光灯FLA的最终光照射。杂质扩散可以被控制到最小，并且当在MOSFET的源极和漏极延伸区域中形成离子注入层时，在杂质掺杂过程中已经发展出的晶体缺陷可以被充分地减小，或者源中的离子注入层和漏区。

7. 发明申请

US20070215918A1 Semiconductor device with extension structure and method for fabricating the same 有权
标题翻译：具有延伸结构的半导体器件及其制造方法
公开(公告)号：US20070215918A1
公开(公告)日：2007-09-20
申请号：US11704924
申请日：2007-02-12
申请人： Takayuki Ito , Kyoichi Suguro , Kouji Matsuo
发明人： Takayuki Ito , Kyoichi Suguro , Kouji Matsuo
IPC分类号： H01L29/76
CPC分类号： H01L21/823857 , H01L21/823814 , H01L21/823842
摘要： A semiconductor device includes a semiconductor region, a source region, a drain region, a source extension region a drain extension region, a first gate insulation film, a second gate insulation film, and a gate electrode. The source region, drain region, source extension region and drain extension region are formed in a surface portion of the semiconductor region. The first gate insulation film is formed on the semiconductor region between the source extension region and the drain extension region. The first gate insulation film is formed of a silicon oxide film or a silicon oxynitride film having a nitrogen concentration of 15 atomic % or less. The second gate insulation film is formed on the first gate insulation film and contains nitrogen at a concentration of between 20 atomic % and 57 atomic %. The gate electrode is formed on the second gate insulation film.
摘要翻译：半导体器件包括半导体区域，源极区域，漏极区域，源极延伸区域，漏极延伸区域，第一栅极绝缘膜，第二栅极绝缘膜和栅极电极。源极区域，漏极区域，源极延伸区域和漏极延伸区域形成在半导体区域的表面部分中。第一栅极绝缘膜形成在源极延伸区域和漏极延伸区域之间的半导体区域上。第一栅极绝缘膜由氮浓度为15原子％以下的氧化硅膜或氮氧化硅膜形成。第二栅极绝缘膜形成在第一栅极绝缘膜上，并且含有浓度为20原子％至57原子％之间的氮。栅电极形成在第二栅绝缘膜上。

8. 发明授权

US07157340B2 Method of fabrication of semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US07157340B2
公开(公告)日：2007-01-02
申请号：US11052861
申请日：2005-02-09
申请人： Takayuki Ito , Kyoichi Suguro , Kanna Tomiie , Kazuya Ouchi
发明人： Takayuki Ito , Kyoichi Suguro , Kanna Tomiie , Kazuya Ouchi
IPC分类号： H01L21/336 , H01L21/331 , H01L21/332
CPC分类号： H01L21/823814 , H01L21/26513 , H01L21/2686 , H01L29/6659
摘要： A manufacturing method of a semiconductor device, the method including implanting impurity ions into a silicon layer and irradiating a pulsed light having a pulse width of 100 milliseconds or less and a rise time of 0.3 milliseconds or more onto the silicon layer thereby activating the impurity ions. The rise time is defined as a time interval of a leading edge between an instant at which the pulsed light starts to rise and an instant at which the pulsed light reaches a peak energy.
摘要翻译：一种半导体器件的制造方法，所述方法包括将杂质离子注入到硅层中，并将脉冲宽度为100毫秒或更短的脉冲光和0.3毫秒或更长的上升时间照射到硅层上，从而激活杂质离子。上升时间被定义为脉冲光开始上升的瞬间与脉冲光达到峰值能量的瞬间之间的前沿的时间间隔。

9. 发明授权

US07122448B2 Annealing apparatus, annealing method, and manufacturing method of a semiconductor device 有权
标题翻译：退火装置，退火方法以及半导体装置的制造方法
公开(公告)号：US07122448B2
公开(公告)日：2006-10-17
申请号：US10926306
申请日：2004-08-26
申请人： Takayuki Ito , Kyoichi Suguro
发明人： Takayuki Ito , Kyoichi Suguro
IPC分类号： H01L21/301 , H01L21/326
CPC分类号： H01L21/67115 , H01L21/26513 , H01L21/324
摘要： An annealing apparatus, includes a substrate stage placing a semiconductor substrate; a light source facing the substrate stage, configured to irradiate a pulsed light at a pulse width of approximately 0.1 ms to 100 ms on a surface of the semiconductor substrate; and a mask configured to selectively reduce intensity of the light transmitting a peripheral region along an outer edge of the semiconductor substrate, so as to define an irradiation region by the peripheral region.
摘要翻译：退火设备包括：放置半导体衬底的衬底台; 面对所述衬底台的光源，被配置为在所述半导体衬底的表面上照射约0.1ms至100ms的脉冲宽度的脉冲光; 以及掩模，其被配置为选择性地降低沿着半导体衬底的外边缘传输周边区域的光的强度，以便通过周边区域限定照射区域。

10. 发明申请

US20050227463A1 Doping method and manufacturing method for a semiconductor device 有权
标题翻译：掺杂方法和半导体器件的制造方法
公开(公告)号：US20050227463A1
公开(公告)日：2005-10-13
申请号：US11097259
申请日：2005-04-04
申请人： Takayuki Ito , Kyoichi Suguro
发明人： Takayuki Ito , Kyoichi Suguro
IPC分类号： H01L21/336 , H01L21/425 , H01L21/8238
CPC分类号： H01L21/2236 , H01L21/823814 , Y10S438/918 , Y10S438/964
摘要： A doping method includes implanting first impurity ions into a semiconductor substrate, so as to form a damaged region in the vicinity of a surface of the semiconductor substrate, the first impurity ions not contributing to electric conductivity; implanting second impurity ions into the semiconductor substrate through the damaged region, the second impurity ions having an atomic weight larger than the first impurity ions and contributing to the electric conductivity; and heating the surface of the semiconductor substrate with a light having a pulse width of about 0.1 ms to about 100 ms, so as to activate the second impurity ions.
摘要翻译：掺杂方法包括将第一杂质离子注入到半导体衬底中，以在半导体衬底的表面附近形成损伤区域，不对导电性有贡献的第一杂质离子; 通过损伤区域将第二杂质离子注入到半导体衬底中，第二杂质离子的原子量大于第一杂质离子并有助于导电性; 并用脉冲宽度为约0.1ms至约100ms的光来加热半导体衬底的表面，以激活第二杂质离子。

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