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1. 发明授权

US08211785B2 Fabrication method for semiconductor device including flash lamp annealing processes 有权
标题翻译：包括闪光灯退火工艺的半导体器件的制造方法
公开(公告)号：US08211785B2
公开(公告)日：2012-07-03
申请号：US11819776
申请日：2007-06-29
申请人： Takaharu Itani , Takayuki Ito , Kyoichi Suguro
发明人： Takaharu Itani , Takayuki Ito , Kyoichi Suguro
IPC分类号： H01L21/425
CPC分类号： H01L21/26533 , H01L21/324 , H01L29/6659
摘要： A shallow p-n junction diffusion layer having a high activation rate of implanted ions, low resistivity, and a controlled leakage current is formed through annealing. Annealing after impurities have been doped is carried out through light irradiation. Those impurities are activated by annealing at least twice through light irradiation after doping impurities to a semiconductor substrate 11. The light radiations are characterized by usage of a W halogen lamp RTA or a flash lamp FLA except for the final light irradiation using a flash lamp FLA. Impurity diffusion may be controlled to a minimum, and crystal defects, which have developed in an impurity doping process, may be sufficiently reduced when forming ion implanted layers in a source and a drain extension region of the MOSFET or ion implanted layers in a source and a drain region.
摘要翻译：通过退火形成具有注入离子的高激活速率，低电阻率和受控的漏电流的浅p-n结扩散层。通过光照射进行杂质掺杂后的退火。这些杂质通过在将杂质掺杂到半导体衬底11之后通过光照射退火至少两次来激活。光辐射的特征在于使用W卤素灯RTA或闪光灯FLA，除了使用闪光灯FLA的最终光照射。杂质扩散可以被控制到最小，并且当在源的源极和漏极延伸区域中形成离子注入层时，或者在源中的离子注入层形成离子注入层时，杂质掺杂过程中已经形成的晶体缺陷可以被充分地减小，以及漏极区域。

2. 发明授权

US07989903B2 Semiconductor device with extension structure and method for fabricating the same 有权
标题翻译：具有延伸结构的半导体器件及其制造方法
公开(公告)号：US07989903B2
公开(公告)日：2011-08-02
申请号：US12757658
申请日：2010-04-09
申请人： Takayuki Ito , Kyoichi Suguro , Kouji Matsuo
发明人： Takayuki Ito , Kyoichi Suguro , Kouji Matsuo
IPC分类号： H01L21/02
CPC分类号： H01L21/823857 , H01L21/823814 , H01L21/823842
摘要： A semiconductor device includes a semiconductor region, a source region, a drain region, a source extension region a drain extension region, a first gate insulation film, a second gate insulation film, and a gate electrode. The source region, drain region, source extension region and drain extension region are formed in a surface portion of the semiconductor region. The first gate insulation film is formed on the semiconductor region between the source extension region and the drain extension region. The first gate insulation film is formed of a silicon oxide film or a silicon oxynitride film having a nitrogen concentration of 15 atomic % or less. The second gate insulation film is formed on the first gate insulation film and contains nitrogen at a concentration of between 20 atomic % and 57 atomic %. The gate electrode is formed on the second gate insulation film.
摘要翻译：半导体器件包括半导体区域，源极区域，漏极区域，源极延伸区域，漏极延伸区域，第一栅极绝缘膜，第二栅极绝缘膜和栅极电极。源极区域，漏极区域，源极延伸区域和漏极延伸区域形成在半导体区域的表面部分中。第一栅极绝缘膜形成在源极延伸区域和漏极延伸区域之间的半导体区域上。第一栅极绝缘膜由氮浓度为15原子％以下的氧化硅膜或氮氧化硅膜形成。第二栅极绝缘膜形成在第一栅极绝缘膜上，并且含有浓度为20原子％至57原子％之间的氮。栅电极形成在第二栅绝缘膜上。

3. 发明申请

US20100055859A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20100055859A1
公开(公告)日：2010-03-04
申请号：US12591085
申请日：2009-11-06
申请人： Takayuki Ito , Toshihiko Iinuma , Kyoichi Suguro
发明人： Takayuki Ito , Toshihiko Iinuma , Kyoichi Suguro
IPC分类号： H01L21/336 , H01L21/425
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/2686 , H01L29/6653 , H01L29/66575 , H01L29/6659
摘要： Disclosed is a method for manufacturing a semiconductor device comprising implanting ions of an impurity element into a semiconductor region, implanting, into the semiconductor region, ions of a predetermined element which is a group IV element or an element having the same conductivity type as the impurity element and larger in mass number than the impurity element, and irradiating a region into which the impurity element and the predetermined element are implanted with light to anneal the region, the light having an emission intensity distribution, a maximum point of the distribution existing in a wavelength region of not more than 600 nm.
摘要翻译：公开了一种制造半导体器件的方法，包括将杂质元素的离子注入到半导体区域中，将作为IV族元素的预定元素或与杂质相同的导电类型的元素的离子注入半导体区域元素，并且质量数大于杂质元素，并且用光照射杂质元素和预定元素被注入的区域以使该区域退火，该光具有发光强度分布，存在于a的分布的最大点波长区域不大于600nm。

4. 发明授权

US07026205B2 Method for manufacturing semiconductor device, including multiple heat treatment 有权
标题翻译：制造半导体器件的方法，包括多次热处理
公开(公告)号：US07026205B2
公开(公告)日：2006-04-11
申请号：US10815931
申请日：2004-04-02
申请人： Takayuki Ito , Kyoichi Suguro
发明人： Takayuki Ito , Kyoichi Suguro
IPC分类号： H01L21/8238 , H01L21/8234 , H01L21/336
CPC分类号： H01L21/823842
摘要： A semiconductor device manufacturing method having forming first and second insulating gate portions spaced from each other on a semiconductor substrate, selectively implanting the first conductivity type impurity ions to the first gate electrode and a surface layer of the semiconductor substrate adjacent to the first insulating gate portion, selectively implanting the second conductivity type impurity ions to the second gate electrode and the surface layer adjacent to the second insulating gate portion, after implanting the first and second conductivity types impurity ions, pre-annealing at a first substrate temperature, and after the pre-annealing, main-activating for the first and second types impurity ions at a second substrate temperature higher than the first substrate temperature for a treatment period shorter than a period of the pre-annealing.
摘要翻译：一种半导体器件制造方法，其具有形成在半导体衬底上彼此间隔开的第一和第二绝缘栅极部分，选择性地将第一导电类型杂质离子注入到第一栅电极和与第一绝缘栅极部分相邻的半导体衬底的表面层在将第一和第二导电类型的杂质离子注入到第二栅极电极和与第二绝缘栅极部分相邻的表面层之后，在第一衬底温度下进行预退火之后，以及在第一衬底温度之后，选择性地将第二导电型杂质离子注入在第一衬底温度高于第一衬底温度的第二衬底温度下处理短于预退火周期的处理期间，对第一和第二类杂质离子进行主要激活。

5. 发明申请

US20050062107A1 Semiconductor and method of manufacturing the same 有权
标题翻译：半导体及其制造方法
公开(公告)号：US20050062107A1
公开(公告)日：2005-03-24
申请号：US10924909
申请日：2004-08-25
申请人： Takayuki Ito , Kyoichi Suguro
发明人： Takayuki Ito , Kyoichi Suguro
IPC分类号： H01L21/265 , H01L21/00 , H01L21/22 , H01L21/28 , H01L21/324 , H01L21/336 , H01L23/62
CPC分类号： H01L21/26506 , H01L21/28052 , H01L29/665 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor comprises a substrate including a single crystal semiconductor region, and a pattern including a line pattern provided on the substrate, the line pattern having a longitudinal direction differing from a crystal orientation of the single crystal semiconductor region.
摘要翻译：半导体包括包括单晶半导体区域的衬底和包括设置在衬底上的线图案的图案，该线图案具有与单晶半导体区域的晶体取向不同的纵向方向。

6. 发明授权

US07781848B2 Semiconductor device with extension structure and method for fabricating the same 有权
标题翻译：具有延伸结构的半导体器件及其制造方法
公开(公告)号：US07781848B2
公开(公告)日：2010-08-24
申请号：US11704924
申请日：2007-02-12
申请人： Takayuki Ito , Kyoichi Suguro , Kouji Matsuo
发明人： Takayuki Ito , Kyoichi Suguro , Kouji Matsuo
IPC分类号： H01L29/78
CPC分类号： H01L21/823857 , H01L21/823814 , H01L21/823842
摘要： A semiconductor device includes a semiconductor region, a source region, a drain region, a source extension region a drain extension region, a first gate insulation film, a second gate insulation film, and a gate electrode. The source region, drain region, source extension region and drain extension region are formed in a surface portion of the semiconductor region. The first gate insulation film is formed on the semiconductor region between the source extension region and the drain extension region. The first gate insulation film is formed of a silicon oxide film or a silicon oxynitride film having a nitrogen concentration of 15 atomic % or less. The second gate insulation film is formed on the first gate insulation film and contains nitrogen at a concentration of between 20 atomic % and 57 atomic %. The gate electrode is formed on the second gate insulation film.
摘要翻译：半导体器件包括半导体区域，源极区域，漏极区域，源极延伸区域，漏极延伸区域，第一栅极绝缘膜，第二栅极绝缘膜和栅极电极。源极区域，漏极区域，源极延伸区域和漏极延伸区域形成在半导体区域的表面部分中。第一栅极绝缘膜形成在源极延伸区域和漏极延伸区域之间的半导体区域上。第一栅极绝缘膜由氮浓度为15原子％以下的氧化硅膜或氮氧化硅膜形成。第二栅极绝缘膜形成在第一栅极绝缘膜上，并且含有浓度为20原子％至57原子％之间的氮。栅电极形成在第二栅绝缘膜上。

7. 发明申请

US20100193874A1 SEMICONDUCTOR DEVICE WITH EXTENSION STRUCTURE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：具有延伸结构的半导体器件及其制造方法
公开(公告)号：US20100193874A1
公开(公告)日：2010-08-05
申请号：US12757658
申请日：2010-04-09
申请人： Takayuki Ito , Kyoichi Suguro , Kouji Matsuo
发明人： Takayuki Ito , Kyoichi Suguro , Kouji Matsuo
IPC分类号： H01L27/092
CPC分类号： H01L21/823857 , H01L21/823814 , H01L21/823842
摘要： A semiconductor device includes a semiconductor region, a source region, a drain region, a source extension region a drain extension region, a first gate insulation film, a second gate insulation film, and a gate electrode. The source region, drain region, source extension region and drain extension region are formed in a surface portion of the semiconductor region. The first gate insulation film is formed on the semiconductor region between the source extension region and the drain extension region. The first gate insulation film is formed of a silicon oxide film or a silicon oxynitride film having a nitrogen concentration of 15 atomic % or less. The second gate insulation film is formed on the first gate insulation film and contains nitrogen at a concentration of between 20 atomic % and 57 atomic %. The gate electrode is formed on the second gate insulation film.
摘要翻译：半导体器件包括半导体区域，源极区域，漏极区域，源极延伸区域，漏极延伸区域，第一栅极绝缘膜，第二栅极绝缘膜和栅极电极。源极区域，漏极区域，源极延伸区域和漏极延伸区域形成在半导体区域的表面部分中。第一栅极绝缘膜形成在源极延伸区域和漏极延伸区域之间的半导体区域上。第一栅极绝缘膜由氮浓度为15原子％以下的氧化硅膜或氮氧化硅膜形成。第二栅极绝缘膜形成在第一栅极绝缘膜上，并且含有浓度为20原子％至57原子％之间的氮。栅电极形成在第二栅绝缘膜上。

8. 发明授权

US07501332B2 Doping method and manufacturing method for a semiconductor device 有权
标题翻译：掺杂方法和半导体器件的制造方法
公开(公告)号：US07501332B2
公开(公告)日：2009-03-10
申请号：US11097259
申请日：2005-04-04
申请人： Takayuki Ito , Kyoichi Suguro
发明人： Takayuki Ito , Kyoichi Suguro
IPC分类号： H01L21/425
CPC分类号： H01L21/2236 , H01L21/823814 , Y10S438/918 , Y10S438/964
摘要： A doping method includes implanting first impurity ions into a semiconductor substrate, so as to form a damaged region in the vicinity of a surface of the semiconductor substrate, the first impurity ions not contributing to electric conductivity; implanting second impurity ions into the semiconductor substrate through the damaged region, the second impurity ions having an atomic weight larger than the first impurity ions and contributing to the electric conductivity; and heating the surface of the semiconductor substrate with a light having a pulse width of about 0.1 ms to about 100 ms, so as to activate the second impurity ions.
摘要翻译：掺杂方法包括将第一杂质离子注入到半导体衬底中，以在半导体衬底的表面附近形成损伤区域，不对导电性有贡献的第一杂质离子; 通过损伤区域将第二杂质离子注入到半导体衬底中，第二杂质离子的原子量大于第一杂质离子并有助于导电性; 并用脉冲宽度为约0.1ms至约100ms的光来加热半导体衬底的表面，以激活第二杂质离子。

9. 发明申请

US20060216875A1 Method for annealing and method for manufacturing a semiconductor device 审中-公开
标题翻译：退火方法及半导体装置的制造方法
公开(公告)号：US20060216875A1
公开(公告)日：2006-09-28
申请号：US11389212
申请日：2006-03-27
申请人： Takayuki Ito , Kouji Matsuo , Naoki Tamaoki , Yoshinori Honguh , Kyoichi Suguro
发明人： Takayuki Ito , Kouji Matsuo , Naoki Tamaoki , Yoshinori Honguh , Kyoichi Suguro
IPC分类号： H01L21/84
CPC分类号： H01L21/324 , H01L21/268 , H01L21/823814 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： A method for annealing a semiconductor substrate by light irradiation, includes depositing a translucent film with a predetermined thickness on a semiconductor substrate. The translucent film has a refractive index that is smaller than that of the semiconductor substrate. The thickness is defined by a peak wavelength of the light and the refractive index of the translucent film. The semiconductor substrate is heated in a temperature range of about 300° C. to about 600° C. A surface of the semiconductor substrate is heated with the light which has a pulse width of about 0.1 ms to about 100 ms.
摘要翻译：通过光照射对半导体衬底进行退火的方法包括在半导体衬底上沉积预定厚度的半透明膜。半透明膜的折射率小于半导体基板的折射率。厚度由光的峰值波长和半透明膜的折射率决定。将半导体衬底在约300℃至约600℃的温度范围内加热。用脉冲宽度为约0.1ms至约100ms的光来加热半导体衬底的表面。

10. 发明授权

US07060581B2 Method for manufacturing a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US07060581B2
公开(公告)日：2006-06-13
申请号：US10960140
申请日：2004-10-08
申请人： Takayuki Ito , Kyoichi Suguro
发明人： Takayuki Ito , Kyoichi Suguro
IPC分类号： H01L21/336
CPC分类号： H01L21/823892 , H01L21/823807
摘要： A method for manufacturing a semiconductor device, includes forming a first impurity implanted layer in a semiconductor substrate by selectively implanting ions of a first impurity. A dummy pattern is formed on a surface of the semiconductor substrate above the first impurity implanted layer. A second impurity implanted layer is formed in the semiconductor substrate by implanting ions of a second impurity. An interlevel insulating film is buried on the surface of the semiconductor substrate so as to planarize at the level of the dummy pattern. Ions of the first and second impurities are activated by irradiating the semiconductor substrate with a pulsed light at a pulse width of 0.1 ms to 100 ms. An opening is formed by selectively removing the dummy pattern. A gate insulating film and a gate electrode are formed on the exposed surface of the semiconductor substrate.
摘要翻译：一种半导体器件的制造方法，包括通过选择性地注入第一杂质的离子，在半导体衬底中形成第一杂质注入层。在第一杂质注入层上方的半导体衬底的表面上形成虚设图形。通过注入第二杂质的离子，在半导体衬底中形成第二杂质注入层。在半导体衬底的表面上埋设层间绝缘膜，以在虚拟图案的水平面上平坦化。通过以0.1ms至100ms的脉冲宽度的脉冲光照射半导体衬底来激活第一和第二杂质的离子。通过选择性地去除虚拟图案形成开口。在半导体衬底的暴露表面上形成栅极绝缘膜和栅电极。

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