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1. 发明授权

US08985173B2 Manufacturing method and manufacturing apparatus of semiconductor substrate 有权
标题翻译：半导体衬底的制造方法和制造装置
公开(公告)号：US08985173B2
公开(公告)日：2015-03-24
申请号：US13110950
申请日：2011-05-19
申请人： Takatsugu Omata , Tomoaki Moriwaka , Hideto Ohnuma
发明人： Takatsugu Omata , Tomoaki Moriwaka , Hideto Ohnuma
IPC分类号： B32B37/00 , H01L21/18 , H01L21/762
CPC分类号： H01L21/187 , H01L21/76254 , Y10T156/17
摘要： It is an object to provide a homogeneous semiconductor substrate in which defective bonding is reduced. Such a semiconductor substrate can be formed by the steps of: disposing a first substrate in a substrate bonding chamber which includes a substrate supporting base where a plurality of openings is provided, substrate supporting mechanisms provided in the plurality of openings, and raising and lowering mechanisms which raise and lower the substrate supporting mechanisms; disposing a second substrate over the first substrate so as not to be in contact with the first substrate; and bonding the first substrate to the second substrate by using the raising and lowering mechanisms to raise the substrate supporting mechanisms.
摘要翻译：本发明的目的是提供一种均匀的半导体衬底，其中不良接合被降低。这样的半导体基板可以通过以下步骤形成：将第一基板设置在基板接合室中，该基板接合室包括设置有多个开口的基板支撑基座，设置在多个开口中的基板支撑机构，以及升降机构其升高和降低基板支撑机构; 将第二基板设置在所述第一基板上以不与所述第一基板接触; 以及通过使用升高和降低机构来将第一基板结合到第二基板以升高基板支撑机构。

2. 发明申请

US20110214610A1 MANUFACTURING METHOD AND MANUFACTURING APPARATUS OF SEMICONDUCTOR SUBSTRATE 审中-公开
标题翻译：半导体衬底的制造方法和制造设备
公开(公告)号：US20110214610A1
公开(公告)日：2011-09-08
申请号：US13110950
申请日：2011-05-19
申请人： Takatsugu Omata , Tomoaki Moriwaka , Hideto Ohnuma
发明人： Takatsugu Omata , Tomoaki Moriwaka , Hideto Ohnuma
IPC分类号： C23C16/458 , C23C16/02
CPC分类号： H01L21/187 , H01L21/76254 , Y10T156/17
摘要： It is an object to provide a homogeneous semiconductor substrate in which defective bonding is reduced. Such a semiconductor substrate can be formed by the steps of: disposing a first substrate in a substrate bonding chamber which includes a substrate supporting base where a plurality of openings is provided, substrate supporting mechanisms provided in the plurality of openings, and raising and lowering mechanisms which raise and lower the substrate supporting mechanisms; disposing a second substrate over the first substrate so as not to be in contact with the first substrate; and bonding the first substrate to the second substrate by using the raising and lowering mechanisms to raise the substrate supporting mechanisms.
摘要翻译：本发明的目的是提供一种均匀的半导体衬底，其中不良接合被降低。这样的半导体基板可以通过以下步骤形成：将第一基板设置在基板接合室中，该基板接合室包括设置有多个开口的基板支撑基座，设置在多个开口中的基板支撑机构，以及升降机构其升高和降低基板支撑机构; 将第二基板设置在所述第一基板上以不与所述第一基板接触; 以及通过使用升高和降低机构来将第一基板结合到第二基板以升高基板支撑机构。

3. 发明授权

US07947570B2 Manufacturing method and manufacturing apparatus of semiconductor substrate 有权
标题翻译：半导体衬底的制造方法和制造装置
公开(公告)号：US07947570B2
公开(公告)日：2011-05-24
申请号：US12350984
申请日：2009-01-09
申请人： Takatsugu Omata , Tomoaki Moriwaka , Hideto Ohnuma
发明人： Takatsugu Omata , Tomoaki Moriwaka , Hideto Ohnuma
IPC分类号： H01L21/77 , H01L21/78
CPC分类号： H01L21/187 , H01L21/76254 , Y10T156/17
摘要： It is an object to provide a homogeneous semiconductor substrate in which defective bonding is reduced. Such a semiconductor substrate can be formed by the steps of: disposing a first substrate in a substrate bonding chamber which includes a substrate supporting base where a plurality of openings is provided, substrate supporting mechanisms provided in the plurality of openings, and raising and lowering mechanisms which raise and lower the substrate supporting mechanisms; disposing a second substrate over the first substrate so as not to be in contact with the first substrate; and bonding the first substrate to the second substrate by using the raising and lowering mechanisms to raise the substrate supporting mechanisms.
摘要翻译：本发明的目的是提供一种均匀的半导体衬底，其中不良接合被降低。这样的半导体基板可以通过以下步骤形成：将第一基板设置在基板接合室中，该基板接合室包括设置有多个开口的基板支撑基座，设置在多个开口中的基板支撑机构，以及升降机构其升高和降低基板支撑机构; 将第二基板设置在所述第一基板上以不与所述第一基板接触; 以及通过使用升高和降低机构来将第一基板结合到第二基板以升高基板支撑机构。

4. 发明申请

US20110070692A1 HEAT TREATMENT APPARATUS, HEAT TREATMENT METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：热处理装置，热处理方法及制造半导体装置的方法
公开(公告)号：US20110070692A1
公开(公告)日：2011-03-24
申请号：US12888627
申请日：2010-09-23
申请人： Akihiro Narita , Hideto Ohnuma , Tomoaki Moriwaka , Shunpei Yamazaki
发明人： Akihiro Narita , Hideto Ohnuma , Tomoaki Moriwaka , Shunpei Yamazaki
IPC分类号： H01L21/34 , F27B5/16
CPC分类号： H01L21/67109 , F27B17/0025 , H01L21/02554 , H01L21/02565 , H01L21/6719
摘要： Provided is a heat treatment apparatus in which a large-sized substrate can be rapidly heated and rapidly cooled with high uniformity, and a heat treatment method using the heat treatment apparatus. The heat treatment apparatus includes: a first chamber of which one side is opened; a second chamber of which one side is opened; a device for moving the first and the second chambers; a heating device; a gas introduction port; a gas exhaust port; and a jig for longitudinally fixing a substrate, in which the substrate is rapidly heated while the first and the second chambers are connected, and rapidly cooled by separating the chambers to move the substrate away from a heat storage portion of the heating device or the like. Further, the heat treatment method includes the heat treatment apparatus, and a method for manufacturing a semiconductor device using an oxide semiconductor is included.
摘要翻译：提供一种热处理装置，其中大尺寸基板可以快速加热并且高均匀地快速冷却，并且使用热处理装置的热处理方法。热处理装置包括：一侧开放的第一室; 一侧打开的第二腔室; 用于移动第一和第二腔室的装置; 加热装置; 气体引入口; 排气口; 以及用于纵向固定基板的夹具，其中在连接第一和第二室时基板被快速加热，并且通过分离室来快速冷却以使基板远离加热装置等的储热部分移动。此外，热处理方法包括热处理装置，以及使用氧化物半导体的半导体装置的制造方法。

5. 发明授权

US08440941B2 Heat treatment apparatus, heat treatment method and method for manufacturing semiconductor device 有权
标题翻译：热处理装置，热处理方法以及半导体装置的制造方法
公开(公告)号：US08440941B2
公开(公告)日：2013-05-14
申请号：US12888627
申请日：2010-09-23
申请人： Akihiro Narita , Hideto Ohnuma , Tomoaki Moriwaka , Shunpei Yamazaki
发明人： Akihiro Narita , Hideto Ohnuma , Tomoaki Moriwaka , Shunpei Yamazaki
IPC分类号： F27D11/00 , B23K1/005 , H05B37/02 , H01L21/00
CPC分类号： H01L21/67109 , F27B17/0025 , H01L21/02554 , H01L21/02565 , H01L21/6719
摘要： Provided is a heat treatment apparatus in which a large-sized substrate can be rapidly heated and rapidly cooled with high uniformity, and a heat treatment method using the heat treatment apparatus. The heat treatment apparatus includes: a first chamber of which one side is opened; a second chamber of which one side is opened; a device for moving the first and the second chambers; a heating device; a gas introduction port; a gas exhaust port; and a jig for longitudinally fixing a substrate, in which the substrate is rapidly heated while the first and the second chambers are connected, and rapidly cooled by separating the chambers to move the substrate away from a heat storage portion of the heating device or the like. Further, the heat treatment method includes the heat treatment apparatus, and a method for manufacturing a semiconductor device using an oxide semiconductor is included.
摘要翻译：提供一种热处理装置，其中大尺寸基板可以快速加热并且高均匀地快速冷却，并且使用热处理装置的热处理方法。热处理装置包括：一侧开放的第一室; 一侧打开的第二腔室; 用于移动第一和第二腔室的装置; 加热装置; 气体引入口; 排气口; 以及用于纵向固定基板的夹具，其中在连接第一和第二室时基板被快速加热，并且通过分离室来快速冷却以使基板远离加热装置等的储热部分移动。此外，热处理方法包括热处理装置，以及使用氧化物半导体的半导体装置的制造方法。

6. 发明授权

US08574976B2 Semiconductor device and manufacturing method thereof 失效
公开(公告)号：US08574976B2
公开(公告)日：2013-11-05
申请号：US12904235
申请日：2010-10-14
申请人： Shunpei Yamazaki , Naoto Kusumoto , Hideto Ohnuma , Koichiro Tanaka
发明人： Shunpei Yamazaki , Naoto Kusumoto , Hideto Ohnuma , Koichiro Tanaka
IPC分类号： H01L21/00
CPC分类号： H01L27/127 , G02F1/13454 , H01L27/1203 , H01L27/1214 , H01L29/4908 , H01L29/66757 , H01L29/78696
摘要： A TFT having a high threshold voltage is connected to the source electrode of each TFT that constitutes a CMOS circuit. In another aspect, pixel thin-film transistors are constructed such that a thin-film transistor more distant from a gate line drive circuit has a lower threshold voltage. In a further aspect, a control film that is removable in a later step is formed on the surface of the channel forming region of a TFT, and doping is performed from above the control film.

7. 发明授权

US08471262B2 Semiconductor device and fabrication method thereof 有权
公开(公告)号：US08471262B2
公开(公告)日：2013-06-25
申请号：US13238754
申请日：2011-09-21
申请人： Shunpei Yamazaki , Satoshi Murakami , Jun Koyama , Yukio Tanaka , Hidehito Kitakado , Hideto Ohnuma
发明人： Shunpei Yamazaki , Satoshi Murakami , Jun Koyama , Yukio Tanaka , Hidehito Kitakado , Hideto Ohnuma
IPC分类号： H01L27/14
CPC分类号： G02F1/1368 , G02F1/133345 , G02F1/13454 , G02F1/136227 , G02F1/136286 , G02F2201/123 , G02F2202/104 , H01L27/12 , H01L27/1222 , H01L27/124 , H01L27/1248 , H01L27/1259 , H01L27/3248 , H01L27/3258 , H01L27/3262 , H01L27/3272 , H01L27/3276 , H01L29/458 , H01L29/78621 , H01L29/78627 , H01L29/78675 , H01L2029/7863 , H01L2227/323
摘要： This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant to hot carrier injection is achieved. LDD regions 717, 718, 719 and 720 not overlapping with a gate wiring are arranged in an n-channel TFT 804 forming a pixel unit. As a result, a TFT structure having a small OFF current value is achieved. In this instance, an element belonging to the Group 15 of the Periodic Table exists in a higher concentration in the LDD region 707 than in the LDD regions 717, 718, 719 and 720.

8. 发明授权

US08470648B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08470648B2
公开(公告)日：2013-06-25
申请号：US12899993
申请日：2010-10-07
申请人： Shunpei Yamazaki , Hideto Ohnuma , Tetsuya Kakehata
发明人： Shunpei Yamazaki , Hideto Ohnuma , Tetsuya Kakehata
IPC分类号： H01L21/762
CPC分类号： H01L27/1266 , H01L21/31662 , H01L21/76254 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/1203 , H01L27/1214 , H01L27/1229 , H01L29/66772 , H01L2224/16225 , H01L2224/16227 , H01L2224/32245 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2224/13099 , H01L2224/29099 , H01L2224/80001
摘要： A semiconductor device including a plurality of field-effect transistors which are stacked with a planarization layer interposed therebetween over a substrate having an insulating surface, in which semiconductor layers in the plurality of field-effect transistors are separated from semiconductor substrates, and the semiconductor layers are bonded to an insulating layer formed over the substrate having an insulating surface or an insulating layer formed over the planarization layer.
摘要翻译：一种半导体器件，包括多个场效应晶体管，所述多个场效应晶体管在其间具有绝缘表面的衬底上层叠有平坦化层，所述多个场效应晶体管中的半导体层与半导体衬底分离，并且所述半导体层被结合到形成在具有形成在平坦化层上的绝缘表面或绝缘层的衬底上的绝缘层。

9. 发明授权

US08324032B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08324032B2
公开(公告)日：2012-12-04
申请号：US13152492
申请日：2011-06-03
申请人： Hideto Ohnuma , Ichiro Uehara
发明人： Hideto Ohnuma , Ichiro Uehara
IPC分类号： H01L21/84
CPC分类号： H01L27/1288 , H01L21/28114 , H01L21/32136 , H01L21/32139 , H01L27/1214 , H01L29/42384 , H01L29/66598 , H01L29/66757 , H01L29/78621 , H01L29/78627 , H01L2029/7863 , Y10S438/949
摘要： Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order to perform formation of LDD structures and GOLD structures only by processes such as dry etching, the transistor structures all have the same structure, and it is difficult to form LDD structures, GOLD structures, and single drain structures separately for different circuits. By applying a photolithography process for forming gate electrodes to photomasks or reticles, in which supplemental patterns having a function of reducing, the intensity of light and composed of diffraction grating patterns or translucent films, are established, GOLD structure, LDD structure, and single drain structure transistors can be easily manufactured for different circuits through dry etching and ion injection process steps.
摘要翻译：通常以半导体器件中的LDD结构和GOLD结构的形式，以栅电极作为掩模进行自对准，但是栅电极具有两层结构的情况很多，成膜工艺和蚀刻工艺变得复杂。此外，为了仅通过诸如干蚀刻的工艺来形成LDD结构和GOLD结构，晶体管结构都具有相同的结构，并且难以分别形成用于不同电路的LDD结构，GOLD结构和单个漏极结构。通过对光栅掩模或掩模版形成栅极电极的光刻工艺，建立了具有降低光的强度并由衍射光栅图案或半透明膜构成的功能的补充图案，GOLD结构，LDD结构和单漏极通过干蚀刻和离子注入工艺步骤可以容易地为不同的电路制造结构晶体管。

10. 发明授权

US08273613B2 Semiconductor device and method of manufacture thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08273613B2
公开(公告)日：2012-09-25
申请号：US12621537
申请日：2009-11-19
申请人： Hongyong Zhang , Yasuhiko Takemura , Toshimitsu Konuma , Hideto Ohnuma , Naoaki Yamaguchi , Hideomi Suzawa , Hideki Uochi
发明人： Hongyong Zhang , Yasuhiko Takemura , Toshimitsu Konuma , Hideto Ohnuma , Naoaki Yamaguchi , Hideomi Suzawa , Hideki Uochi
IPC分类号： H01L21/84
CPC分类号： H01L27/127 , H01L27/1214 , H01L29/66757 , H01L29/78621 , H01L29/78627
摘要： There is provided a method by which lightly doped drain (LDD) regions can be formed easily and at good yields in source/drain regions in thin film transistors possessing gate electrodes covered with an oxide covering. A lightly doped drain (LDD) region is formed by introducing an impurity into an island-shaped silicon film in a self-aligning manner, with a gate electrode serving as a mask. First, low-concentration impurity regions are formed in the island-shaped silicon film by using rotation-tilt ion implantation to effect ion doping from an oblique direction relative to the substrate. Low-concentration impurity regions are also formed below the gate electrode at this time. After that, an impurity at a high concentration is introduced normally to the substrate, so forming high-concentration impurity regions. In the above process, a low-concentration impurity region remains below the gate electrode and constitutes a lightly doped drain region.
摘要翻译：提供了一种方法，通过该方法可以容易地形成轻掺杂漏极（LDD）区域，并且在具有覆盖有氧化物覆盖层的栅电极的薄膜晶体管中的源/漏区域中以良好的产率形成。通过以栅极电极作为掩模，以自对准的方式将杂质引入岛状硅膜中形成轻掺杂漏极（LDD）区域。首先，通过使用旋转 - 倾斜离子注入在岛状硅膜中形成低浓度杂质区，以相对于衬底从倾斜方向进行离子掺杂。此时也在栅电极下方形成低浓度杂质区。之后，将高浓度的杂质通常引入衬底，从而形成高浓度杂质区域。在上述过程中，低浓度杂质区域保留在栅电极下方并构成轻掺杂漏区。

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