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1. 发明授权

US08417548B2 Medical service support apparatus 有权
标题翻译：医疗服务支援设备
公开(公告)号：US08417548B2
公开(公告)日：2013-04-09
申请号：US13091833
申请日：2011-04-21
申请人： Hiroyuki Araki , Takashi Hosaka , Masakazu Omura , Yusuke Kato , Emiko Ouchi , Ryoichi Hosoya
发明人： Hiroyuki Araki , Takashi Hosaka , Masakazu Omura , Yusuke Kato , Emiko Ouchi , Ryoichi Hosoya
IPC分类号： G06Q50/00
CPC分类号： G06Q50/24 , G06F19/00 , G06F19/325 , G06Q50/22 , G16H50/70
摘要： A recording unit holds a plurality of examination data including the examination date of a performed examination. A search unit extracts examination data matching a set condition, of the plurality of examination data held in the recording unit. An output unit outputs a search result by the search unit. A first narrowing unit extracts examination data in which the examination date is included within a designated first period. A reference data determination unit classifies the examination data extracted by the first narrowing unit by an examinee and determines, for every examinee, one piece of the examination data to be a reference in accordance with a predetermined rule. A second narrowing unit sets, for every examinee, a second period designated in at least one of the past direction and the future direction starting from a reference date that is the examination date of the examination data determined by the reference data determination unit and extracts examination data in which the examination date is included within the second period.
摘要翻译：记录单元保存包括执行检查的检查日期的多个检查数据。搜索单元提取与保持在记录单元中的多个检查数据相匹配的设定条件的检查数据。输出单元通过搜索单元输出搜索结果。第一缩小单元提取在指定的第一周期内包括检查日期的检查数据。参考数据确定单元将由第一变窄单元提取的检查数据分类为受检者，并且根据预定规则为每个受检者确定一个检查数据作为参考。第二缩小单元针对每个受试者设定从作为由参考数据确定单元确定的检查数据的检查日期的参考日期开始的至少一个过去方向和未来方向指定的第二时段，并且提取检查在第二期间内包含审查日期的数据。

2. 发明授权

US5234863A Method of manufacturing doped contacts to semiconductor devices 失效
标题翻译：制造半导体器件的掺杂接触的方法
公开(公告)号：US5234863A
公开(公告)日：1993-08-10
申请号：US805116
申请日：1991-12-10
申请人： Takashi Hosaka
发明人： Takashi Hosaka
IPC分类号： H01L21/285 , H01L21/768
CPC分类号： H01L21/28525 , H01L21/76877 , H01L21/76879
摘要： The present invention relates to a method of forming contacts in contact holes used in the semiconductor devices. The object of the present invention is to flatten the contacts to contact holes of a size smaller than 1 .mu.m in order to decrease the contact resistance in the contact holes. After a contact hole is formed on an P.sup.+ diffused layer, a polycrystalline (or amorphous) silicon film containing P-type impurities is formed by a chemical vapor-phase deposition method to fill the contact hole. Then, the contact hole only is filled with the polycrystalline silicon film by an etch-back method. Contact to an N.sup.+ diffused layer is subsequently formed in the same manner using a silicon film containing N-type impurities, followed by an upper wiring. Since polycrystalline silicon film is formed by the vapor-phase deposition method maintaining good step-covering property, the contact hole is sufficiently filled. The polycrystalline silicon film containing impurities in a high concentration makes it possible to lower the contact resistance in the contact holes.
摘要翻译：本发明涉及在半导体器件中使用的接触孔中形成触点的方法。本发明的目的是为了降低接触孔中的接触电阻，使触点平坦化以小于1μm的尺寸的接触孔。在P +扩散层上形成接触孔后，通过化学气相沉积法形成包含P型杂质的多晶（或非晶）硅膜，以填充接触孔。然后，通过蚀刻方法仅在多孔硅膜上填充接触孔。随后使用含有N型杂质的硅膜，然后以上布线，以相同的方式形成与N +扩散层的接触。由于通过保持良好的阶梯覆盖性的气相沉积法形成多晶硅膜，因此充分填充接触孔。含有高浓度杂质的多晶硅膜可以降低接触孔中的接触电阻。

3. 发明授权

US4954867A Semiconductor device with silicon oxynitride over refractory metal gate electrode in LDD structure 失效
$Semiconductor device with silicon oxynitride over refractory metal gate electrode in LDD structure$
标题翻译：具有氮氧化硅的半导体器件在LDD结构中的难熔金属栅电极上
公开(公告)号：US4954867A
公开(公告)日：1990-09-04
申请号：US201052
申请日：1988-06-01
申请人： Takashi Hosaka
发明人： Takashi Hosaka
IPC分类号： H01L21/336 , H01L21/32 , H01L23/29 , H01L29/49 , H01L29/78
CPC分类号： H01L29/78 , H01L21/32 , H01L23/291 , H01L29/495 , H01L29/4983 , H01L2924/0002 , Y10S148/114
摘要： A semiconductor device uses a high melting point metal such as tungsten, molybdenum, etc. at its gate electrode and wirings for higher operation speed. In particular, the top and the side of the gate electrode and wirings are covered by a layer of silicon oxynitride whereby the gate electrode and the wiring are protected from oxidation and deterioration which may be cause by heat treatment in an oxidative atmosphere and ion implantation.
摘要翻译：半导体器件在其栅电极处使用诸如钨，钼等的高熔点金属和用于更高操作速度的布线。特别地，栅电极和布线的顶部和侧面被氮氧化硅层覆盖，从而保护栅电极和布线免受在氧化气氛中的热处理和离子注入引起的氧化和劣化。

4. 发明授权

US06475897B1 Semiconductor device and method of forming semiconductor device 有权
标题翻译：半导体器件及半导体器件的形成方法
公开(公告)号：US06475897B1
公开(公告)日：2002-11-05
申请号：US09639709
申请日：2000-08-14
申请人： Takashi Hosaka
发明人： Takashi Hosaka
IPC分类号： H01L2930
CPC分类号： H01L24/13 , H01L24/11 , H01L2224/05001 , H01L2224/05124 , H01L2224/05147 , H01L2224/05573 , H01L2224/05624 , H01L2224/05647 , H01L2224/1134 , H01L2224/13022 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13164 , H01L2224/16 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2924/0105 , H01L2224/13099 , H01L2924/013
摘要： A semiconductor device, such as an IC package, having the same size as an IC chip and having improved qualities is manufactured at a low cost by a particular manufacturing method. The semiconductor device has stepped-projection bumps bonded to electrode pads on a semiconductor substrate in which a semiconductor element is formed. A column portion and a portion in a horizontal portion of each stepped-projection bump are exposed while the other portion of the bump is covered with a protective material. When windows of the protective material corresponding to the column portions are formed, the windows are patterned by using a masking material based on a photoetching method, and the protective material is removed by etching.
摘要翻译：通过特定的制造方法以低成本制造具有与IC芯片相同尺寸并且具有改进的品质的诸如IC封装的半导体器件。半导体器件具有接合到其中形成半导体元件的半导体衬底上的电极焊盘的阶梯式凸起凸块。每个阶梯式凸起凸起的柱部分和水平部分中的一部分被暴露，而凸块的另一部分被保护材料覆盖。当形成对应于柱部分的保护材料的窗口时，通过使用基于光刻方法的掩模材料对窗口进行图案化，并且通过蚀刻去除保护材料。

5. 发明授权

US06329274B1 Method of producing semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US06329274B1
公开(公告)日：2001-12-11
申请号：US07995325
申请日：1992-12-28
申请人： Naoto Inoue , Kenji Aoki , Takashi Hosaka
发明人： Naoto Inoue , Kenji Aoki , Takashi Hosaka
IPC分类号： H01L2128
CPC分类号： H01L21/76897 , H01L21/2254 , H01L21/28512 , H01L21/28525 , H01L21/76802
摘要： For forming electrical interlayer contact in a semiconductor device, an insulating film is formed on a first electrically conductive layer and then a contact hole is formed in the insulating film to expose a part of the first electroconductive, an activated surface of the exposed part is formed in the contact hole, a gas containing an impurity component is supplied to form an impurity adsorption film on the activated surface, and the contact hole is filled with a second electrically conductive layer which electrically contacts the first layer through the contact hole.
摘要翻译：为了在半导体器件中形成电中间层接触，在第一导电层上形成绝缘膜，然后在绝缘膜中形成接触孔以暴露第一导电部分，形成暴露部分的活化表面在接触孔中，供给包含杂质成分的气体，以在活化表面上形成杂质吸附膜，并且接触孔填充有通过接触孔与第一层电接触的第二导电层。

6. 发明授权

US5210043A Process for producing semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US5210043A
公开(公告)日：1993-05-11
申请号：US588553
申请日：1990-09-26
申请人： Takashi Hosaka
发明人： Takashi Hosaka
IPC分类号： H01L21/265 , H01L21/225 , H01L21/28 , H01L21/285
CPC分类号： H01L21/2257 , H01L21/28518 , Y10S148/018
摘要： A process for producing a semiconductor device having a structure in which a silicide film is in contact with an impurity diffusion layer inside a semiconductor substrate through a contact hole, in that, after the formation of the silicide film, an element of the same conductivity type as that of the impurity diffusion layer is implanted by ion implantation in the vicinity of the interface between the silicide film and the impurity diffusion layer through the silicide film.
摘要翻译：一种半导体器件的制造方法，其具有通过接触孔使硅化物膜与半导体衬底内的杂质扩散层接触的结构，其中，在形成硅化物膜之后，具有相同导电型的元件通过离子注入在硅化物膜和杂质扩散层之间的界面附近通过硅化物膜注入杂质扩散层。

7. 发明授权

US5001527A Semiconductor device with thin insulation film 失效
标题翻译：具有薄绝缘膜的半导体器件
公开(公告)号：US5001527A
公开(公告)日：1991-03-19
申请号：US569375
申请日：1990-08-13
申请人： Takashi Hosaka
发明人： Takashi Hosaka
IPC分类号： H01L29/43 , H01L21/28 , H01L21/316 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L21/8247 , H01L23/52 , H01L23/522 , H01L27/04 , H01L29/49 , H01L29/51 , H01L29/788 , H01L29/792 , H01L29/92
CPC分类号： H01L21/02164 , H01L21/02211 , H01L21/02271 , H01L21/31608 , H01L28/40 , H01L29/4933 , H01L29/517 , H01L29/518
摘要： In the step of forming a thin insulation film with the thickness of less than 1,000 .ANG. on the polycide electrode and wiring after formiung the polycide electrode and wiring, a semiconductor device having preferable insulation performance and high reliability is formed by using a silicon oxide film (SiO.sub.2) formed by a chemical vapor deposition process using a dichlorosilane (SiH.sub.2 Cl.sub.2) gas and a nitrous oxide (N.sub.2 O) gas under a reduced pressure of from 0.1 mbar to 2 mbar and at a temperature from 700.degree. C. to 950.degree. C. as the insulation film.
摘要翻译：在形成多晶硅电极和布线之后，在多晶硅电极和布线上形成厚度小于1000的薄绝缘膜的步骤中，通过使用氧化硅膜（具有绝缘性能和高可靠性）形成具有优选的绝缘性能和高可靠性的半导体器件 SiO 2），其通过使用二氯硅烷（SiH 2 Cl 2）气体和一氧化二氮（N 2 O）气体在0.1mbar至2mbar的减压下和在700℃至950℃的温度下通过化学气相沉积法形成，如绝缘膜。

8. 发明授权

US10804087B2 Ultra-compact mass analysis device and ultra-compact particle acceleration device 有权
公开(公告)号：US10804087B2
公开(公告)日：2020-10-13
申请号：US16274773
申请日：2019-02-13
申请人： Takashi Hosaka
发明人： Takashi Hosaka
IPC分类号： H01J49/06 , H01J49/42 , H01J49/38 , H01J49/32 , H01J49/00 , H05H13/04 , H05H9/00 , H01J49/20 , H05H7/04 , H05H5/03 , G01N27/62 , H01J49/22 , H05H7/22
摘要： A mass analyzer includes a main substrate, an upper substrate adhered to the main substrate, and a lower substrate. A mass analysis room (cavity) is formed in the main substrate and penetrates from an upper surface of the first main substrate to a lower surface of the first main substrate. A vertical direction (Z direction) to the main substrate by the upper substrate, both sides of the lower substrate, a travelling direction (X direction) of charged particles and a right angle to the Z direction by the main substrate, and both sides of a right-angled direction (Y to Z direction) and the X direction by a side surface of the main substrate are surrounded. A central hole is open in the side plate of the main substrate that the charged particles enter. The charged particles enter the mass analysis room through the central hole formed in the first main substrate.

9. 发明授权

US10249483B2 Ultra-compact mass analysis device and ultra-compact particle acceleration device 有权
公开(公告)号：US10249483B2
公开(公告)日：2019-04-02
申请号：US15329153
申请日：2015-07-29
申请人： Takashi Hosaka
发明人： Takashi Hosaka
IPC分类号： H01J49/06 , H01J49/20 , H01J49/22 , H01J49/42 , G01N27/62 , H05H5/03 , H05H7/04 , H05H7/22 , H05H9/00 , H05H13/04 , H01J49/00 , H01J49/32 , H01J49/38
摘要： A mass analyzer includes a main substrate, an upper substrate adhered to the main substrate, and a lower substrate. A mass analysis room (cavity) is formed in the main substrate and penetrates from an upper surface of the first main substrate to a lower surface of the first main substrate. A vertical direction (Z direction) to the main substrate by the upper substrate, both sides of the lower substrate, a travelling direction (X direction) of charged particles and a right angle to the Z direction by the main substrate, and both sides of a right-angled direction (Y to Z direction) and the X direction by a side surface of the main substrate are surrounded. A central hole is open in the side plate of the main substrate that the charged particles enter. The charged particles enter the mass analysis room through the central hole formed in the first main substrate.

10. 发明授权

US06528354B1 Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06528354B1
公开(公告)日：2003-03-04
申请号：US09941146
申请日：2001-08-28
申请人： Takashi Hosaka
发明人： Takashi Hosaka
IPC分类号： H01L2150
CPC分类号： H01L21/568 , H01L21/561 , H01L21/565 , H01L21/6835 , H01L24/97 , H01L2224/48091 , H01L2224/97 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/09701 , H01L2924/14 , H01L2924/15787 , H01L2924/3511 , H01L2224/85 , H01L2924/00014 , H01L2924/00
摘要： In the manufacture of semiconductor devices in which a plurality of semiconductor chips are mounted to a substrate, warping of the substrate is prevented by covering a first surface of the substrate with a first resin layer, covering a second surface of the substrate opposite the first surface with a continuous film and covering the continuous film with a second resin layer. Stresses applied to the substrate by the first and second resin layers cancel each other out to prevent warping of the substrate. The second resin layer is removed by peeling the.continuous film, so that individual chip die may be removed by dicing the substrate.
摘要翻译：在其中将多个半导体芯片安装到基板的半导体器件的制造中，通过用第一树脂层覆盖基板的第一表面来防止基板翘曲，覆盖基板的与第一表面相对的第二表面连续薄膜并用第二树脂层覆盖连续薄膜。通过第一和第二树脂层施加到基板的应力相互抵消以防止基板翘曲。通过剥离连续膜来除去第二树脂层，从而可以通过切割基板来除去单独的芯片芯片。

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