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1. 发明授权

US10804087B2 Ultra-compact mass analysis device and ultra-compact particle acceleration device 有权
公开(公告)号：US10804087B2
公开(公告)日：2020-10-13
申请号：US16274773
申请日：2019-02-13
申请人： Takashi Hosaka
发明人： Takashi Hosaka
IPC分类号： H01J49/06 , H01J49/42 , H01J49/38 , H01J49/32 , H01J49/00 , H05H13/04 , H05H9/00 , H01J49/20 , H05H7/04 , H05H5/03 , G01N27/62 , H01J49/22 , H05H7/22
摘要： A mass analyzer includes a main substrate, an upper substrate adhered to the main substrate, and a lower substrate. A mass analysis room (cavity) is formed in the main substrate and penetrates from an upper surface of the first main substrate to a lower surface of the first main substrate. A vertical direction (Z direction) to the main substrate by the upper substrate, both sides of the lower substrate, a travelling direction (X direction) of charged particles and a right angle to the Z direction by the main substrate, and both sides of a right-angled direction (Y to Z direction) and the X direction by a side surface of the main substrate are surrounded. A central hole is open in the side plate of the main substrate that the charged particles enter. The charged particles enter the mass analysis room through the central hole formed in the first main substrate.

2. 发明申请

US20190198306A1 ULTRA-COMPACT MASS ANALYSIS DEVICE AND ULTRA-COMPACT PARTICLE ACCELERATION DEVICE 审中-公开
公开(公告)号：US20190198306A1
公开(公告)日：2019-06-27
申请号：US16274773
申请日：2019-02-13
申请人： Takashi HOSAKA
发明人： Takashi HOSAKA
IPC分类号： H01J49/06 , H01J49/42 , H01J49/38 , H01J49/32 , H01J49/00 , H05H13/04 , H05H9/00 , H01J49/20 , H05H7/04 , H05H5/03 , G01N27/62 , H01J49/22 , H05H7/22
摘要： A mass analyzer includes a main substrate, an upper substrate adhered to the main substrate, and a lower substrate. A mass analysis room (cavity) is formed in the main substrate and penetrates from an upper surface of the first main substrate to a lower surface of the first main substrate. A vertical direction (Z direction) to the main substrate by the upper substrate, both sides of the lower substrate, a travelling direction (X direction) of charged particles and a right angle to the Z direction by the main substrate, and both sides of a right-angled direction (Y to Z direction) and the X direction by a side surface of the main substrate are surrounded. A central hole is open in the side plate of the main substrate that the charged particles enter. The charged particles enter the mass analysis room through the central hole formed in the first main substrate.

3. 发明授权

US10249483B2 Ultra-compact mass analysis device and ultra-compact particle acceleration device 有权
公开(公告)号：US10249483B2
公开(公告)日：2019-04-02
申请号：US15329153
申请日：2015-07-29
申请人： Takashi Hosaka
发明人： Takashi Hosaka
IPC分类号： H01J49/06 , H01J49/20 , H01J49/22 , H01J49/42 , G01N27/62 , H05H5/03 , H05H7/04 , H05H7/22 , H05H9/00 , H05H13/04 , H01J49/00 , H01J49/32 , H01J49/38
摘要： A mass analyzer includes a main substrate, an upper substrate adhered to the main substrate, and a lower substrate. A mass analysis room (cavity) is formed in the main substrate and penetrates from an upper surface of the first main substrate to a lower surface of the first main substrate. A vertical direction (Z direction) to the main substrate by the upper substrate, both sides of the lower substrate, a travelling direction (X direction) of charged particles and a right angle to the Z direction by the main substrate, and both sides of a right-angled direction (Y to Z direction) and the X direction by a side surface of the main substrate are surrounded. A central hole is open in the side plate of the main substrate that the charged particles enter. The charged particles enter the mass analysis room through the central hole formed in the first main substrate.

4. 发明授权

US06528354B1 Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06528354B1
公开(公告)日：2003-03-04
申请号：US09941146
申请日：2001-08-28
申请人： Takashi Hosaka
发明人： Takashi Hosaka
IPC分类号： H01L2150
CPC分类号： H01L21/568 , H01L21/561 , H01L21/565 , H01L21/6835 , H01L24/97 , H01L2224/48091 , H01L2224/97 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/09701 , H01L2924/14 , H01L2924/15787 , H01L2924/3511 , H01L2224/85 , H01L2924/00014 , H01L2924/00
摘要： In the manufacture of semiconductor devices in which a plurality of semiconductor chips are mounted to a substrate, warping of the substrate is prevented by covering a first surface of the substrate with a first resin layer, covering a second surface of the substrate opposite the first surface with a continuous film and covering the continuous film with a second resin layer. Stresses applied to the substrate by the first and second resin layers cancel each other out to prevent warping of the substrate. The second resin layer is removed by peeling the.continuous film, so that individual chip die may be removed by dicing the substrate.
摘要翻译：在其中将多个半导体芯片安装到基板的半导体器件的制造中，通过用第一树脂层覆盖基板的第一表面来防止基板翘曲，覆盖基板的与第一表面相对的第二表面连续薄膜并用第二树脂层覆盖连续薄膜。通过第一和第二树脂层施加到基板的应力相互抵消以防止基板翘曲。通过剥离连续膜来除去第二树脂层，从而可以通过切割基板来除去单独的芯片芯片。

5. 发明授权

US5030588A Method of making semiconductor device with film resistor 失效
标题翻译：制造具有薄膜电阻的半导体器件的方法
公开(公告)号：US5030588A
公开(公告)日：1991-07-09
申请号：US332810
申请日：1989-04-03
申请人： Takashi Hosaka
发明人： Takashi Hosaka
IPC分类号： H01L21/3205 , H01L21/02 , H01L21/822 , H01L23/52 , H01L27/04
CPC分类号： H01L28/24
摘要： A method of making a semiconductor device having a film resistive element. A resistive film is deposited over a substrate formed with a first contact hole open to an under-layer electrode region disposed in or on the substrate. The resistive layer is selectively etched to form the film resistive element and at the same time to leave portion of the resistive film disposed in and around the first contact hole. An inter-layer insulating film is then formed over the substrate. The inter-layer insulating film is selectively etched to form a second contact hole open to the film resistive element and at the same time to remove at least portion of the inter-layer insulating film disposed in and around the first contact hole. An over-layer electrode pattern film is formed in contact with the resistive film left in the first and second contact holes.
摘要翻译：一种制造具有膜电阻元件的半导体器件的方法。电阻膜沉积在形成有第一接触孔的衬底上，该第一接触孔设置在衬底中或衬底上的下层电极区。选择性地蚀刻电阻层以形成膜电阻元件，同时留下布置在第一接触孔中和周围的电阻膜的部分。然后在衬底上形成层间绝缘膜。选择性地蚀刻层间绝缘膜以形成通向薄膜电阻元件的第二接触孔，同时去除设置在第一接触孔中和周围的层间绝缘膜的至少一部分。形成与第一和第二接触孔中留下的电阻膜接触的覆盖层电极图案膜。

6. 发明授权

US08417548B2 Medical service support apparatus 有权
标题翻译：医疗服务支援设备
公开(公告)号：US08417548B2
公开(公告)日：2013-04-09
申请号：US13091833
申请日：2011-04-21
申请人： Hiroyuki Araki , Takashi Hosaka , Masakazu Omura , Yusuke Kato , Emiko Ouchi , Ryoichi Hosoya
发明人： Hiroyuki Araki , Takashi Hosaka , Masakazu Omura , Yusuke Kato , Emiko Ouchi , Ryoichi Hosoya
IPC分类号： G06Q50/00
CPC分类号： G06Q50/24 , G06F19/00 , G06F19/325 , G06Q50/22 , G16H50/70
摘要： A recording unit holds a plurality of examination data including the examination date of a performed examination. A search unit extracts examination data matching a set condition, of the plurality of examination data held in the recording unit. An output unit outputs a search result by the search unit. A first narrowing unit extracts examination data in which the examination date is included within a designated first period. A reference data determination unit classifies the examination data extracted by the first narrowing unit by an examinee and determines, for every examinee, one piece of the examination data to be a reference in accordance with a predetermined rule. A second narrowing unit sets, for every examinee, a second period designated in at least one of the past direction and the future direction starting from a reference date that is the examination date of the examination data determined by the reference data determination unit and extracts examination data in which the examination date is included within the second period.
摘要翻译：记录单元保存包括执行检查的检查日期的多个检查数据。搜索单元提取与保持在记录单元中的多个检查数据相匹配的设定条件的检查数据。输出单元通过搜索单元输出搜索结果。第一缩小单元提取在指定的第一周期内包括检查日期的检查数据。参考数据确定单元将由第一变窄单元提取的检查数据分类为受检者，并且根据预定规则为每个受检者确定一个检查数据作为参考。第二缩小单元针对每个受试者设定从作为由参考数据确定单元确定的检查数据的检查日期的参考日期开始的至少一个过去方向和未来方向指定的第二时段，并且提取检查在第二期间内包含审查日期的数据。

7. 发明授权

US5234863A Method of manufacturing doped contacts to semiconductor devices 失效
标题翻译：制造半导体器件的掺杂接触的方法
公开(公告)号：US5234863A
公开(公告)日：1993-08-10
申请号：US805116
申请日：1991-12-10
申请人： Takashi Hosaka
发明人： Takashi Hosaka
IPC分类号： H01L21/285 , H01L21/768
CPC分类号： H01L21/28525 , H01L21/76877 , H01L21/76879
摘要： The present invention relates to a method of forming contacts in contact holes used in the semiconductor devices. The object of the present invention is to flatten the contacts to contact holes of a size smaller than 1 .mu.m in order to decrease the contact resistance in the contact holes. After a contact hole is formed on an P.sup.+ diffused layer, a polycrystalline (or amorphous) silicon film containing P-type impurities is formed by a chemical vapor-phase deposition method to fill the contact hole. Then, the contact hole only is filled with the polycrystalline silicon film by an etch-back method. Contact to an N.sup.+ diffused layer is subsequently formed in the same manner using a silicon film containing N-type impurities, followed by an upper wiring. Since polycrystalline silicon film is formed by the vapor-phase deposition method maintaining good step-covering property, the contact hole is sufficiently filled. The polycrystalline silicon film containing impurities in a high concentration makes it possible to lower the contact resistance in the contact holes.
摘要翻译：本发明涉及在半导体器件中使用的接触孔中形成触点的方法。本发明的目的是为了降低接触孔中的接触电阻，使触点平坦化以小于1μm的尺寸的接触孔。在P +扩散层上形成接触孔后，通过化学气相沉积法形成包含P型杂质的多晶（或非晶）硅膜，以填充接触孔。然后，通过蚀刻方法仅在多孔硅膜上填充接触孔。随后使用含有N型杂质的硅膜，然后以上布线，以相同的方式形成与N +扩散层的接触。由于通过保持良好的阶梯覆盖性的气相沉积法形成多晶硅膜，因此充分填充接触孔。含有高浓度杂质的多晶硅膜可以降低接触孔中的接触电阻。

8. 发明授权

US4954867A Semiconductor device with silicon oxynitride over refractory metal gate electrode in LDD structure 失效
$Semiconductor device with silicon oxynitride over refractory metal gate electrode in LDD structure$
标题翻译：具有氮氧化硅的半导体器件在LDD结构中的难熔金属栅电极上
公开(公告)号：US4954867A
公开(公告)日：1990-09-04
申请号：US201052
申请日：1988-06-01
申请人： Takashi Hosaka
发明人： Takashi Hosaka
IPC分类号： H01L21/336 , H01L21/32 , H01L23/29 , H01L29/49 , H01L29/78
CPC分类号： H01L29/78 , H01L21/32 , H01L23/291 , H01L29/495 , H01L29/4983 , H01L2924/0002 , Y10S148/114
摘要： A semiconductor device uses a high melting point metal such as tungsten, molybdenum, etc. at its gate electrode and wirings for higher operation speed. In particular, the top and the side of the gate electrode and wirings are covered by a layer of silicon oxynitride whereby the gate electrode and the wiring are protected from oxidation and deterioration which may be cause by heat treatment in an oxidative atmosphere and ion implantation.
摘要翻译：半导体器件在其栅电极处使用诸如钨，钼等的高熔点金属和用于更高操作速度的布线。特别地，栅电极和布线的顶部和侧面被氮氧化硅层覆盖，从而保护栅电极和布线免受在氧化气氛中的热处理和离子注入引起的氧化和劣化。

9. 发明申请

US20170330739A1 ULTRA-COMPACT MASS ANALYSIS DEVICE AND ULTRA-COMPACT PARTICLE ACCELERATION DEVICE 审中-公开
公开(公告)号：US20170330739A1
公开(公告)日：2017-11-16
申请号：US15329153
申请日：2015-07-29
申请人： Takashi HOSAKA
发明人： Takashi HOSAKA
IPC分类号： H01J49/06 , H01J49/20 , H01J49/22 , H01J49/42
CPC分类号： H01J49/06 , G01N27/62 , H01J49/0018 , H01J49/20 , H01J49/22 , H01J49/326 , H01J49/38 , H01J49/4205 , H01J49/4215 , H05H5/03 , H05H7/04 , H05H7/22 , H05H9/00 , H05H13/04
摘要： A mass analyzer includes a main substrate, an upper substrate adhered to the main substrate, and a lower substrate. A mass analysis room (cavity) is formed in the main substrate and penetrates from an upper surface of the first main substrate to a lower surface of the first main substrate. A vertical direction (Z direction) to the main substrate by the upper substrate, both sides of the lower substrate, a travelling direction (X direction) of charged particles and a right angle to the Z direction by the main substrate, and both sides of a right-angled direction (Y to Z direction) and the X direction by a side surface of the main substrate are surrounded. A central hole is open in the side plate of the main substrate that the charged particles enter. The charged particles enter the mass analysis room through the central hole formed in the first main substrate.

10. 发明申请

US20050143840A1 Controller managing system 审中-公开
标题翻译：控制器管理系统
公开(公告)号：US20050143840A1
公开(公告)日：2005-06-30
申请号：US11019391
申请日：2004-12-23
申请人： Sadao Matsukura , Takashi Hosaka , Norinaga Mutai
发明人： Sadao Matsukura , Takashi Hosaka , Norinaga Mutai
IPC分类号： G05B19/418 , G05B19/042 , G05B15/02 , G05B11/01 , G05B19/18 , G06F1/26 , G06F1/28 , G06F1/30
CPC分类号： G05B19/0423 , Y02P90/087
摘要： A controller managing system that enables a computer of a managing device to efficiently perform communication processing with a plurality of controllers. These controllers are connected via a network. to the monitoring computer of the managing device. The monitoring computer performs a power status determination task and a monitoring task. Each controller transmits power-ON information representing a power ON state to the monitoring computer at prescribed intervals. When the power status determination task cannot receive the power-ON information within a predetermined time period from either one of the controllers, it is determined that the power supply to that controller is OFF. The monitoring task skips the controller that is determined as being in a power OFF state; so as not to receive data therefrom, and communicates with the next controller that is in a power ON state. Since the controller whose power is OFF is skipped so as not to perform data reception communication therewith, time for wasteful timeout processing is unnecessary and efficient communication can be achieved.
摘要翻译：一种控制器管理系统，其使得管理设备的计算机能够有效地执行与多个控制器的通信处理。这些控制器通过网络连接。到管理设备的监视计算机。监视计算机执行电源状态确定任务和监视任务。每个控制器以规定的间隔向监视计算机发送表示电源接通状态的通电信息。当电源状态确定任务在从任一个控制器的预定时间段内不能接收到电源接通信息时，确定到该控制器的电源为OFF。监视任务跳过确定为处于电源关闭状态的控制器; 从而不从其接收数据，并且与处于电源接通状态的下一个控制器进行通信。由于跳过功率为OFF的控制器，以便不进行与其的数据接收通信，因此不需要浪费超时处理的时间，并且可以实现有效的通信。

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