专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120249225A1 CHARGE PUMP CIRCUIT 审中-公开
标题翻译：充电泵电路
公开(公告)号：US20120249225A1
公开(公告)日：2012-10-04
申请号：US13524927
申请日：2012-06-15
申请人： Takanobu Suzuki , Susumu Tanida
发明人： Takanobu Suzuki , Susumu Tanida
IPC分类号： G05F1/10
CPC分类号： H02M3/073 , H02M1/36 , H02M1/44
摘要： There is provided a charge pump circuit which can prevent EMI noise of a frequency component independent of an operation clock frequency from occurring at the time of a change from a disable state to an enable state. The charge pump circuit includes a detection signal synchronization circuit which outputs a synchronization detection signal generated by synchronizing a detection signal outputted from a level detection circuit to a clock signal outputted from an oscillator circuit. The synchronization detection signal is used as a pump enable signal, and a first pump capacitance and a second pump capacitance in a pump circuit body are charged and discharged in response to the synchronization detection signal and the clock signal outputted from the oscillator circuit.
摘要翻译：提供了一种电荷泵电路，其可以防止在从禁用状态改变到使能状态时发生与操作时钟频率无关的频率分量的EMI噪声。电荷泵电路包括检测信号同步电路，其输出通过使从电平检测电路输出的检测信号与从振荡器电路输出的时钟信号同步而产生的同步检测信号。同步检测信号用作泵使能信号，并且响应于从振荡器电路输出的同步检测信号和时钟信号，在泵电路体中的第一泵电容和第二泵电容被充电和放电。

2. 发明申请

US20090237148A1 CHARGE PUMP CIRCUIT 有权
标题翻译：充电泵电路
公开(公告)号：US20090237148A1
公开(公告)日：2009-09-24
申请号：US12354319
申请日：2009-01-15
申请人： Takanobu Suzuki , Susumu Tanida
发明人： Takanobu Suzuki , Susumu Tanida
IPC分类号： G05F1/10
CPC分类号： H02M3/073 , H02M1/36 , H02M1/44
摘要： There is provided a charge pump circuit which can prevent EMI noise of a frequency component independent of an operation clock frequency from occurring at the time of a change from a disable state to an enable state. The charge pump circuit includes a detection signal synchronization circuit which outputs a synchronization detection signal generated by synchronizing a detection signal outputted from a level detection circuit to a clock signal outputted from an oscillator circuit. The synchronization detection signal is used as a pump enable signal, and a first pump capacitance and a second pump capacitance in a pump circuit body are charged and discharged in response to the synchronization detection signal and the clock signal outputted from the oscillator circuit.
摘要翻译：提供了一种电荷泵电路，其可以防止在从禁用状态改变到使能状态时发生与操作时钟频率无关的频率分量的EMI噪声。电荷泵电路包括检测信号同步电路，其输出通过使从电平检测电路输出的检测信号与从振荡器电路输出的时钟信号同步而产生的同步检测信号。同步检测信号用作泵使能信号，并且响应于从振荡器电路输出的同步检测信号和时钟信号，在泵电路体中的第一泵电容和第二泵电容被充电和放电。

3. 发明授权

US08248154B2 Charge pump circuit 有权
标题翻译：电荷泵电路
公开(公告)号：US08248154B2
公开(公告)日：2012-08-21
申请号：US13012311
申请日：2011-01-24
申请人： Takanobu Suzuki , Susumu Tanida
发明人： Takanobu Suzuki , Susumu Tanida
IPC分类号： G05F1/10
CPC分类号： H02M3/073 , H02M1/36 , H02M1/44
摘要： There is provided a charge pump circuit which can prevent EMI noise of a frequency component independent of an operation clock frequency from occurring at the time of a change from a disable state to an enable state. The charge pump circuit includes a detection signal synchronization circuit which outputs a synchronization detection signal generated by synchronizing a detection signal outputted from a level detection circuit to a clock signal outputted from an oscillator circuit. The synchronization detection signal is used as a pump enable signal, and a first pump capacitance and a second pump capacitance in a pump circuit body are charged and discharged in response to the synchronization detection signal and the clock signal outputted from the oscillator circuit.
摘要翻译：提供了一种电荷泵电路，其可以防止在从禁用状态改变到使能状态时发生与操作时钟频率无关的频率分量的EMI噪声。电荷泵电路包括检测信号同步电路，其输出通过使从电平检测电路输出的检测信号与从振荡器电路输出的时钟信号同步而产生的同步检测信号。同步检测信号用作泵使能信号，并且响应于从振荡器电路输出的同步检测信号和时钟信号，在泵电路体中的第一泵电容和第二泵电容被充电和放电。

4. 发明授权

US07902909B2 Charge pump circuit 有权
标题翻译：电荷泵电路
公开(公告)号：US07902909B2
公开(公告)日：2011-03-08
申请号：US12354319
申请日：2009-01-15
申请人： Takanobu Suzuki , Susumu Tanida
发明人： Takanobu Suzuki , Susumu Tanida
IPC分类号： G05F1/10
CPC分类号： H02M3/073 , H02M1/36 , H02M1/44
摘要： There is provided a charge pump circuit which can prevent EMI noise of a frequency component independent of an operation clock frequency from occurring at the time of a change from a disable state to an enable state. The charge pump circuit includes a detection signal synchronization circuit which outputs a synchronization detection signal generated by synchronizing a detection signal outputted from a level detection circuit to a clock signal outputted from an oscillator circuit. The synchronization detection signal is used as a pump enable signal, and a first pump capacitance and a second pump capacitance in a pump circuit body are charged and discharged in response to the synchronization detection signal and the clock signal outputted from the oscillator circuit.
摘要翻译：提供了一种电荷泵电路，其可以防止在从禁用状态改变到使能状态时发生与操作时钟频率无关的频率分量的EMI噪声。电荷泵电路包括检测信号同步电路，其输出通过使从电平检测电路输出的检测信号与从振荡器电路输出的时钟信号同步而产生的同步检测信号。同步检测信号用作泵使能信号，并且响应于从振荡器电路输出的同步检测信号和时钟信号，在泵电路体中的第一泵电容和第二泵电容被充电和放电。

5. 发明授权

US06798679B2 Semiconductor memory module 失效
标题翻译：半导体存储器模块
公开(公告)号：US06798679B2
公开(公告)日：2004-09-28
申请号：US10286756
申请日：2002-11-04
申请人： Yasuhiro Matsumoto , Shinji Tanaka , Seiji Sawada , Susumu Tanida , Takahiko Fukiage
发明人： Yasuhiro Matsumoto , Shinji Tanaka , Seiji Sawada , Susumu Tanida , Takahiko Fukiage
IPC分类号： G11C504
CPC分类号： H01L23/50 , B82Y10/00 , G11C5/04 , G11C29/70 , G11C29/832 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L2224/04042 , H01L2224/05553 , H01L2224/05599 , H01L2224/06136 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48699 , H01L2224/48799 , H01L2224/49171 , H01L2224/85399 , H01L2225/1005 , H01L2225/1023 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/10161 , H01L2924/12042 , H01L2924/181 , H01L2924/19043 , H01L2924/30105 , H01L2924/00 , H01L2924/00012
摘要： A bare chip is provided with a pad for activation/deactivation control to which a deactivation control signal for converting a bare chip that has been detected as being defective into the deactivated condition is inputted. When a deactivation control signal is inputted to the pad for activation/deactivation control, internal circuit prevent a signal that has been inputted from the pad for data input/output control from being inputted to an internal circuit located further inside than the input buffer circuit. Thereby, the bare chip that has been detected as being defective can be converted to the deactivated condition. As a result, a semiconductor memory module can be obtained that can be repaired by newly mounting a good function chip without allowing the bare chip that has been detected as being defective to interfere with the functions of the semiconductor memory module.
摘要翻译：裸芯片设置有用于激活/去激活控制的焊盘，其中输入用于将已经被检测为有缺陷的裸芯片转换为去激活状态的去激活控制信号。当去激活控制信号被输入到焊盘进行激活/去激活控制时，内部电路防止从焊盘输入的用于数据输入/输出控制的信号被输入到比输入缓冲电路更靠内部的内部电路。因此，可以将被检测为缺陷的裸芯片转换为去激活状态。结果，可以获得可以通过新安装好的功能芯片来修复的半导体存储器模块，而不允许已经被检测到的裸芯片干扰半导体存储器模块的功能。

6. 发明授权

US6031782A Semiconductor memory device provided with an interface circuit consuming a reduced amount of current consumption 失效
标题翻译：具有消耗电流消耗量的接口电路的半导体存储器件
公开(公告)号：US6031782A
公开(公告)日：2000-02-29
申请号：US124514
申请日：1998-07-29
申请人： Hisao Kobashi , Mikio Sakurai , Susumu Tanida
发明人： Hisao Kobashi , Mikio Sakurai , Susumu Tanida
IPC分类号： G11C11/41 , G11C7/00 , G11C7/22 , G11C11/403 , G11C11/406 , G11C11/407 , G11C11/4076 , G11C11/409 , G11C11/417 , H03F3/45
CPC分类号： G11C11/4076 , G11C11/406 , G11C7/22
摘要： A clock buffer in a semiconductor memory device includes two kinds of interface circuits, i.e., an LVTTL interface and an SSTL interface. When the semiconductor memory device is set to a specific mode (self-refresh mode) for suppressing a power consumption, the LVTTL is used for taking in an external signal. In a mode other than the self-refresh mode, the SSTL interface is used to take in an externally supplied signal. Thereby, a current can be suppressed in the specific mode.
摘要翻译：半导体存储器件中的时钟缓冲器包括两种接口电路，即LVTTL接口和SSTL接口。当半导体存储器件被设置为用于抑制功耗的特定模式（自刷新模式）时，LVTTL用于获取外部信号。在自刷新模式以外的模式下，SSTL接口用于接收外部提供的信号。由此，可以在特定模式中抑制电流。

7. 发明授权

US5694352A Semiconductor memory device having layout area of periphery of output pad reduced 失效
标题翻译：具有减少输出焊盘周边布局区域的半导体存储器件
公开(公告)号：US5694352A
公开(公告)日：1997-12-02
申请号：US676705
申请日：1996-07-08
申请人： Susumu Tanida , Yasuhiko Tsukikawa , Kiyohiro Furutani , Takayuki Miyamoto
发明人： Susumu Tanida , Yasuhiko Tsukikawa , Kiyohiro Furutani , Takayuki Miyamoto
IPC分类号： G11C11/41 , G11C5/02 , G11C7/10 , G11C11/401 , H01L21/8242 , H01L27/108 , G11C5/06
CPC分类号： G11C7/10 , G11C5/025
摘要： A semiconductor memory device includes four memory cell arrays, four output pads formed in a linear manner at the center of a semiconductor substrate, four output control circuits for generating readout data signals and control signals, four signal generation circuits responsive to the readout data signals for generating complementary pairs of data signals, and responsive to the control signals, four signal line groups including four signal lines connected between the output control circuits and the signal generation circuits, four output drivers responsive to pairs of data signals for supplying data to the output pads, and four signal line pairs connected between the signal generation circuits and output drivers. Signal generation circuits of great size are arranged at the center of the semiconductor substrate where the layout margin is great, and only the output driver is arranged in the proximity of the output pad where the layout margin is small. Therefore, the chip area is reduced. Access is speeded since the signal lines forming the signal line group are shorter in length, though greater in number, than the signal lines forming the signal line pair.
摘要翻译：半导体存储器件包括四个存储单元阵列，在半导体衬底的中心处以线性方式形成的四个输出焊盘，用于产生读出数据信号和控制信号的四个输出控制电路，响应读出数据信号的四个信号发生电路，产生互补的数据信号对，并且响应于控制信号，四个信号线组包括连接在输出控制电路和信号发生电路之间的四条信号线，四个输出驱动器响应于数据信号对，用于向输出焊盘提供数据和连接在信号发生电路和输出驱动器之间的四个信号线对。大尺寸的信号发生电路配置在半导体基板的中央处，其中布局裕量大，只有输出驱动器布置在布局边距较小的输出焊盘附近。因此，芯片面积减少。由于形成信号线组的信号线的长度比形成信号线对的信号线的数量更多，所以访问速度加快。

8. 发明授权

US06337814B1 Semiconductor memory device having reference potential generating circuit 失效
标题翻译：具有参考电位发生电路的半导体存储器件
公开(公告)号：US06337814B1
公开(公告)日：2002-01-08
申请号：US09909977
申请日：2001-07-23
申请人： Susumu Tanida , Masanori Hayashikoshi
发明人： Susumu Tanida , Masanori Hayashikoshi
IPC分类号： G11C714
CPC分类号： G11C29/12 , G11C5/147
摘要： A test mode reference potential generating circuit outputs a reference potential from an output node by activation of a test mode signal. When a sample signal is in an activated state, a transfer gate is turned on, and a capacitor stores the reference potential. When the test is being conducted, the transfer gate is turned off by inactivation of the sample signal, and thus the reference potential stored in the capacitor is output from a node. Thus, the semiconductor memory device according to the present invention can generate a stable reference potential during the test mode.
摘要翻译：测试模式参考电位产生电路通过激活测试模式信号从输出节点输出参考电位。当采样信号处于激活状态时，传输栅极导通，电容器存储参考电位。当进行测试时，通过采样信号的失活来关闭传输门，从而从节点输出存储在电容器中的参考电位。因此，根据本发明的半导体存储器件可以在测试模式期间产生稳定的参考电位。

9. 发明授权

US6034904A Semiconductor memory device having selection circuit for arbitrarily setting a word line to selected state at high speed in test mode 失效
标题翻译：具有选择电路的半导体存储器件，用于在测试模式中高速地将字线任意设置为选定状态
公开(公告)号：US6034904A
公开(公告)日：2000-03-07
申请号：US35989
申请日：1998-03-06
申请人： Osamu Kuromiya , Susumu Tanida , Goro Hayakawa
发明人： Osamu Kuromiya , Susumu Tanida , Goro Hayakawa
IPC分类号： G01R31/28 , G11C11/401 , G11C29/12 , G11C29/14 , G11C29/50 , G11C8/00
CPC分类号： G11C29/50 , G11C29/14 , G11C11/401
摘要： A semiconductor memory device includes a control circuit, a test mode control circuit, an internal period setting circuit and an address latch circuit. The control circuit detects whether test mode is designated or not. The test mode control circuit detects whether or not self disturb test mode is designated. The internal period setting circuit repeatedly generates a clock signal of a prescribed period when the test mode and the self disturb test mode are designated. Simultaneously, the address latch circuit latches an address at a fall of a row address strobe signal. The row decoder is activated in response to the clock signal, and repeatedly sets the word line corresponding to the latched address to the selected state.
摘要翻译：半导体存储器件包括控制电路，测试模式控制电路，内部周期设置电路和地址锁存电路。控制电路检测是否指定测试模式。测试模式控制电路检测是否指定了自身干扰测试模式。当指定测试模式和自我干扰测试模式时，内部周期设置电路重复地产生规定周期的时钟信号。同时，地址锁存电路在行地址选通信号的下降时锁存地址。行解码器响应于时钟信号被激活，并且将对应于锁存地址的字线重复设置为所选择的状态。

10. 发明授权

US5905690A Synchronous semiconductor device having circuitry capable of surely resetting test mode 失效
标题翻译：具有能够可靠地复位测试模式的电路的同步半导体器件
公开(公告)号：US5905690A
公开(公告)日：1999-05-18
申请号：US058987
申请日：1998-04-13
申请人： Mikio Sakurai , Susumu Tanida , Yasuhiko Tsukikawa , Masaya Nakano , Takahiko Fukiage
发明人： Mikio Sakurai , Susumu Tanida , Yasuhiko Tsukikawa , Masaya Nakano , Takahiko Fukiage
IPC分类号： G11C11/407 , G01R31/317 , G11C11/401 , G11C29/14 , G11C8/00
CPC分类号： G01R31/31701
摘要： A reset signal generating circuit in a synchronous semiconductor memory device outputs a reset signal ZPOR1 in response to a power on reset signal ZPOR generated immediately after power on and an initialize command (for example, a precharge command) executed for initialization after power on. A test mode register included in a mode setting circuit receives as a reset signal, the reset signal ZPOR1. Consequently, a test mode signal output attains to an NOP state, or output of the test mode signal is stopped.
摘要翻译：同步半导体存储装置中的复位信号发生电路响应于上电后立即产生的上电复位信号ZPOR和上电后初始化执行的初始化指令（例如，预充电指令），输出复位信号ZPOR1。包括在模式设置电路中的测试模式寄存器作为复位信号接收复位信号ZPOR1。因此，测试模式信号输出达到NOP状态，或停止测试模式信号的输出。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式