专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5694352A Semiconductor memory device having layout area of periphery of output pad reduced 失效
标题翻译：具有减少输出焊盘周边布局区域的半导体存储器件
公开(公告)号：US5694352A
公开(公告)日：1997-12-02
申请号：US676705
申请日：1996-07-08
申请人： Susumu Tanida , Yasuhiko Tsukikawa , Kiyohiro Furutani , Takayuki Miyamoto
发明人： Susumu Tanida , Yasuhiko Tsukikawa , Kiyohiro Furutani , Takayuki Miyamoto
IPC分类号： G11C11/41 , G11C5/02 , G11C7/10 , G11C11/401 , H01L21/8242 , H01L27/108 , G11C5/06
CPC分类号： G11C7/10 , G11C5/025
摘要： A semiconductor memory device includes four memory cell arrays, four output pads formed in a linear manner at the center of a semiconductor substrate, four output control circuits for generating readout data signals and control signals, four signal generation circuits responsive to the readout data signals for generating complementary pairs of data signals, and responsive to the control signals, four signal line groups including four signal lines connected between the output control circuits and the signal generation circuits, four output drivers responsive to pairs of data signals for supplying data to the output pads, and four signal line pairs connected between the signal generation circuits and output drivers. Signal generation circuits of great size are arranged at the center of the semiconductor substrate where the layout margin is great, and only the output driver is arranged in the proximity of the output pad where the layout margin is small. Therefore, the chip area is reduced. Access is speeded since the signal lines forming the signal line group are shorter in length, though greater in number, than the signal lines forming the signal line pair.
摘要翻译：半导体存储器件包括四个存储单元阵列，在半导体衬底的中心处以线性方式形成的四个输出焊盘，用于产生读出数据信号和控制信号的四个输出控制电路，响应读出数据信号的四个信号发生电路，产生互补的数据信号对，并且响应于控制信号，四个信号线组包括连接在输出控制电路和信号发生电路之间的四条信号线，四个输出驱动器响应于数据信号对，用于向输出焊盘提供数据和连接在信号发生电路和输出驱动器之间的四个信号线对。大尺寸的信号发生电路配置在半导体基板的中央处，其中布局裕量大，只有输出驱动器布置在布局边距较小的输出焊盘附近。因此，芯片面积减少。由于形成信号线组的信号线的长度比形成信号线对的信号线的数量更多，所以访问速度加快。

2. 发明授权

US06777920B2 Internal power-supply potential generating circuit 失效
标题翻译：内部电源电位发生电路
公开(公告)号：US06777920B2
公开(公告)日：2004-08-17
申请号：US10247337
申请日：2002-09-20
申请人： Kiyohiro Furutani , Takeshi Hamamoto , Susumu Tanida
发明人： Kiyohiro Furutani , Takeshi Hamamoto , Susumu Tanida
IPC分类号： G05F140
CPC分类号： G05F1/465
摘要： The internal power-supply potential generating circuit includes a reference potential generating circuit having small dependency on an external power-supply potential and on a temperature, an MOS transistor for pull up, a level shifter producing a potential lower than a reference potential by a prescribed voltage to a first node and producing a potential lower than an internal power-supply potential by a voltage of the sum of the prescribed potential and an offset potential to a second node, and a differential amplifier bringing an MOS transistor out of conduction in response to the potential of the second node reaching the potential of the first node. Thus, the reference potential may be set lower by the offset voltage, allowing stable reference potential and internal power-supply potential to be obtained even if the external power-supply potential is lowered.
摘要翻译：内部电源电位产生电路包括对外部电源电位和温度具有较小依赖性的参考电位产生电路，用于上拉的MOS晶体管，产生低于参考电位的电位的电平转换器电压到第一节点，并且通过对第二节点的预定电位和偏移电位之和的电压产生低于内部电源电位的电位;以及差分放大器，使得MOS晶体管响应于第二节点的潜力达到第一节点的潜力。因此，即使外部电源电位降低，也可以将偏置电压设定为较低的基准电位，能够获得稳定的基准电位和内部电源电位。

3. 发明授权

US08300480B2 Semiconductor device having sense amplifiers supplied with an over-drive voltage in a normal mode and supplied with a step-down voltage in a refresh mode 有权
标题翻译：具有以正常模式提供过驱动电压并在刷新模式下被提供降压电压的读出放大器的半导体器件
公开(公告)号：US08300480B2
公开(公告)日：2012-10-30
申请号：US12897399
申请日：2010-10-04
申请人： Kiyohiro Furutani
发明人： Kiyohiro Furutani
IPC分类号： G11C7/08
CPC分类号： G11C11/4074 , G11C7/02 , G11C11/406 , G11C11/40615 , G11C2211/4068
摘要： A semiconductor device which has a sense amplifier and is supplied with an external power supply voltage includes a drive signal line connected to the sense amplifier, a step up circuit generating a first voltage from the external power supply voltage, the first voltage being higher than the external power supply voltage, and a step down circuit lowering the external power supply voltage into a second voltage. For enabling the sense amplifier to perform sensing operation in a normal mode involving external access, the first voltage is applied to the drive signal line in an initial stage of the sensing operation, and thereafter the second voltage is applied to the drive signal line. In a refresh mode not involving external access, the step up circuit is shut down, and the second voltage is applied to the drive signal line from the initial stage of the sensing operation.
摘要翻译：具有读出放大器并被提供有外部电源电压的半导体器件包括连接到读出放大器的驱动信号线，从外部电源电压产生第一电压的升压电路，第一电压高于外部电源电压和降压电路将外部电源电压降低到第二电压。为了使得读出放大器能够在涉及外部访问的正常模式下执行感测操作，在感测操作的初始阶段将第一电压施加到驱动信号线，此后将第二电压施加到驱动信号线。在不涉及外部访问的刷新模式下，升压电路被关闭，并且第二电压从感测操作的初始阶段施加到驱动信号线。

4. 发明申请

US20100157713A1 Semiconductor device with refresh control circuit 失效
标题翻译：具有刷新控制电路的半导体器件
公开(公告)号：US20100157713A1
公开(公告)日：2010-06-24
申请号：US12654109
申请日：2009-12-10
申请人： Kiyohiro Furutani
发明人： Kiyohiro Furutani
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C11/406 , G11C8/06 , G11C8/08 , G11C8/18 , G11C11/40615 , G11C2211/4067
摘要： In a semiconductor device including a row-based control circuit applied with a current reduction circuit having a standby state and an active state, a refresh control circuit generates a refresh request signal every predetermined time interval on a self-refresh mode and time-sequentially generates an internal active signal at N times in connection with the refresh request signal once. The row-based control circuit time-sequentially refreshes information of memory cells on the based of the internal active signal at the N times. The refresh control circuit inactivates the row-based control circuit by making the current reduction circuit the standby state.
摘要翻译：在包括具有待机状态和活动状态的电流降低电路的基于行的控制电路的半导体器件中，刷新控制电路在自刷新模式下以预定的时间间隔生成刷新请求信号，并且时间顺序地产生与刷新请求信号一次的N次内部有效信号。基于行的控制电路基于N次内部有效信号时间顺序刷新存储单元的信息。刷新控制电路通过使电流还原电路处于待机状态来使基于行的控制电路失活。

5. 发明授权

US07542363B2 Semiconductor memory device enhancing reliability in data reading 有权
标题翻译：半导体存储器件提高了数据读取的可靠性
公开(公告)号：US07542363B2
公开(公告)日：2009-06-02
申请号：US11082926
申请日：2005-03-18
申请人： Takashi Kubo , Takashi Itoh , Yasuhiro Kashiwazaki , Taku Ogura , Kiyohiro Furutani
发明人： Takashi Kubo , Takashi Itoh , Yasuhiro Kashiwazaki , Taku Ogura , Kiyohiro Furutani
IPC分类号： G11C7/02
CPC分类号： G11C11/5642 , G11C5/145 , G11C7/06 , G11C7/12 , G11C16/24 , G11C16/26 , G11C16/30 , G11C2207/065 , G11C2207/2227 , G11C2211/5634 , G11C2211/5645
摘要： An internal voltage generating circuit generates and supplies a boosted voltage higher than an internal power supply voltage, as an operating power supply voltage, to a sense amplifier in a read circuit for reading data of a memory cell. A bit line precharge current supplied via an internal data line is produced from the internal power supply voltage. It is possible to provide a nonvolatile semiconductor memory device, which can perform a precise sense operation and an accurate reading of data even under a low power supply voltage condition.
摘要翻译：内部电压产生电路产生并提供高于作为工作电源电压的内部电源电压的升压电压到用于读取存储器单元的数据的读取电路中的读出放大器。从内部电源电压产生经由内部数据线提供的位线预充电电流。可以提供一种非易失性半导体存储器件，即使在低电源电压条件下也能进行精确的读出操作和数据的精确读取。

6. 发明申请

US20070285146A1 Semiconductor device with pump circuit 有权
公开(公告)号：US20070285146A1
公开(公告)日：2007-12-13
申请号：US11822184
申请日：2007-07-03
申请人： Minoru Senda , Kiyohiro Furutani , Taku Ogura , Shigehiro Kuge , Satoshi Kawasaki , Tadaaki Yamauchi
发明人： Minoru Senda , Kiyohiro Furutani , Taku Ogura , Shigehiro Kuge , Satoshi Kawasaki , Tadaaki Yamauchi
IPC分类号： H03K3/00
CPC分类号： G11C16/30 , G11C5/145 , G11C16/04 , H02M3/073 , H02M2003/071 , H02M2003/075 , H02M2003/077 , H03K3/356113
摘要： In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of −9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.

7. 发明申请

US20050213387A1 Semiconductor memory device enhancing reliability in data reading 有权
标题翻译：半导体存储器件提高了数据读取的可靠性
公开(公告)号：US20050213387A1
公开(公告)日：2005-09-29
申请号：US11082926
申请日：2005-03-18
申请人： Takashi Kubo , Takashi Itoh , Yasuhiro Kashiwazaki , Taku Ogura , Kiyohiro Furutani
发明人： Takashi Kubo , Takashi Itoh , Yasuhiro Kashiwazaki , Taku Ogura , Kiyohiro Furutani
IPC分类号： G11C16/06 , G11C5/14 , G11C7/06 , G11C7/12 , G11C11/34 , G11C11/56 , G11C16/02 , G11C16/24 , G11C16/26 , G11C16/30
CPC分类号： G11C11/5642 , G11C5/145 , G11C7/06 , G11C7/12 , G11C16/24 , G11C16/26 , G11C16/30 , G11C2207/065 , G11C2207/2227 , G11C2211/5634 , G11C2211/5645
摘要： An internal voltage generating circuit generates and supplies a boosted voltage higher than an internal power supply voltage, as an operating power supply voltage, to a sense amplifier in a read circuit for reading data of a memory cell. A bit line precharge current supplied via an internal data line is produced from the internal power supply voltage. It is possible to provide a nonvolatile semiconductor memory device, which can perform a precise sense operation and an accurate reading of data even under a low power supply voltage condition.
摘要翻译：内部电压产生电路产生并提供高于作为工作电源电压的内部电源电压的升压电压到用于读取存储器单元的数据的读取电路中的读出放大器。从内部电源电压产生经由内部数据线提供的位线预充电电流。可以提供一种非易失性半导体存储器件，即使在低电源电压条件下也能进行精确的读出操作和数据的精确读取。

8. 发明授权

US06753720B2 Internal high voltage generation circuit capable of stably generating internal high voltage and circuit element therefor 失效
标题翻译：能够稳定地产生内部高电压的内部高压发生电路及其电路元件
公开(公告)号：US06753720B2
公开(公告)日：2004-06-22
申请号：US10302849
申请日：2002-11-25
申请人： Takashi Kono , Katsuyoshi Mitsui , Kiyohiro Furutani
发明人： Takashi Kono , Katsuyoshi Mitsui , Kiyohiro Furutani
IPC分类号： G05F110
CPC分类号： G05F1/465 , G11C5/143 , G11C5/145
摘要： In order to stably generate a high voltage of a prescribed level, a Vpp detection circuit which is activated in response to an activation signal for comparing the high voltage with a reference voltage is forcibly brought into an active state for a prescribed period under control of an initial control circuit.
摘要翻译：为了稳定地产生规定电平的高电压，响应用于将高电压与基准电压进行比较的激活信号而被激活的Vpp检测电路在控制下被强制地进入活动状态初始控制电路。

9. 发明授权

US06477109B2 Synchronous semiconductor memory device allowing data to be satisfactorily rewritten therein 失效
标题翻译：允许在其中令人满意地重写数据的同步半导体存储器件
公开(公告)号：US06477109B2
公开(公告)日：2002-11-05
申请号：US09922669
申请日：2001-08-07
申请人： Kiyohiro Furutani , Yasuhiro Konishi
发明人： Kiyohiro Furutani , Yasuhiro Konishi
IPC分类号： G11C700
CPC分类号： G11C7/109 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/225 , G11C11/4076
摘要： In a SDRAM, there is introduced a control signal going active low following a passage of a predetermined period of time after a sense amplifier activation signal goes active high. When a signal going high during a burst period goes low and the control signal also goes low, a word line is dropped, non-selected low. As such, paired bit lines can have a potential difference sufficiently amplified to allow data to be satisfactorily rewritten into a memory cell.
摘要翻译：在SDRAM中，在读出放大器激活信号变为高电平之后经过预定时间段后引入控制信号变为有效低电平。当突发期间的信号变为高电平，并且控制信号也变低时，字线被丢弃，未选择为低电平。这样，成对的位线可以具有充分放大的电位差，以使数据能够令人满意地重写到存储单元中。

10. 发明授权

US06400621B2 Semiconductor memory device and method of checking same for defect 失效
标题翻译：半导体存储器件及其检查方法为缺陷
公开(公告)号：US06400621B2
公开(公告)日：2002-06-04
申请号：US09912518
申请日：2001-07-26
申请人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
发明人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
IPC分类号： G11C700
CPC分类号： G11C29/24
摘要： A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.
摘要翻译：一种半导体存储器件，包括用于在测试模式下选择正常行中的存储单元的第一测试行解码器（9a），用于选择备用存储单元行的第二测试行解码器（9b），用于选择的第一测试列解码器正常列中的存储单元，以及用于选择备用存储单元列的第二测试列解码器（10b）。控制电路（11）可以通过使用控制信号（SRT）和控制信号（SCT）来执行行和列解码器的四个组合之间的切换。所有备用存储器单元在修补缺陷存储器单元以进行产量增强之前被测试。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式