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    • 5. 发明申请
    • IMAGE PROCESSING CIRCUIT
    • 图像处理电路
    • US20110242091A1
    • 2011-10-06
    • US12879937
    • 2010-09-10
    • Hitoshi KobayashiTatsuo SaishuYoshiyuki Kokojima
    • Hitoshi KobayashiTatsuo SaishuYoshiyuki Kokojima
    • G06T15/00
    • G09G5/399G06T1/60G09G3/003H04N13/161H04N13/31
    • An image processing circuit includes a first memory, a second memory, a write unit and a read unit. The first and second memories alternately store sub pixels of an input image including a plurality of parallax images corresponding to different view point directions. The write unit writes the sub pixels to one of the first and second memories. The read unit reads the sub pixels as an output image from the other of the first and second memories. Each of the first and second memories stores sub pixels for a plurality of successive lines. While the write unit writes the sub pixels of the input image to one of the first and second memories, the read unit reads the sub pixels of the output image from the other of the first and second memories. The first and the second memories are alternately changed.
    • 图像处理电路包括第一存储器,第二存储器,写入单元和读取单元。 第一和第二存储器交替地存储包括对应于不同视点方向的多个视差图像的输入图像的子像素。 写单元将子像素写入第一和第二存储器之一。 读取单元从第一和第二存储器中的另一个读取作为输出图像的子像素。 第一和第二存储器中的每一个存储多个连续行的子像素。 当写入单元将输入图像的子像素写入第一和第二存储器之一时,读取单元从第一和第二存储器中的另一个读取输出图像的子像素。 第一和第二存储器交替地改变。
    • 9. 发明授权
    • Cascade-type variable-order delta-sigma modulator
    • 级联型可变阶Δ-Σ调制器
    • US07319420B2
    • 2008-01-15
    • US11338651
    • 2006-01-25
    • Masato NakakitaFumihito InukaiHitoshi Kobayashi
    • Masato NakakitaFumihito InukaiHitoshi Kobayashi
    • H03M3/00
    • H03M3/394H03M3/414
    • A cascade-type variable-order delta-sigma modulator with low power consumption that can change the number of stages of the quantization loops, which are connected in a cascade configuration, to an optimum number depending on peripheral circuitries in a configuration as simple as possible. The present invention includes first to nth stages of delta-sigma modulating type quantization loops (n is an integer equal to or more than 2) connected in a cascade configuration, and a noise rejecting circuit. Each quantization loop quantizes an input signal, outputs the quantization result, and feeds back the quantization result to itself. The noise rejecting circuit rejects a quantization noise of the first stage of quantization loop, and comprises (n−1) selectors for activating and de-activating the respective output signals of the second and succeeding stages of the quantization loops in compliance with the control signal.
    • 具有低功耗的级联型可变阶Δ-Σ调制器,其可以将串联配置中连接的量化循环的级数改变为最佳数量,这取决于尽可能简单的配置中的外设电路 。 本发明包括以级联配置连接的Δ-Σ调制型量化环(n为等于或大于2的整数)的第一至第N级,以及噪声抑制电路。 每个量化环对输入信号进行量化,输出量化结果,并将量化结果反馈给自身。 噪声抑制电路拒绝量化环路的第一级的量化噪声,并且包括用于根据控制信号激活和去激活量化环路的第二级和后级的各个输出信号的(n-1)个选择器 。