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1. 发明申请

US20110140768A1 INTERNAL VOLTAGE GENERATOR 有权
标题翻译：内部电压发生器
公开(公告)号：US20110140768A1
公开(公告)日：2011-06-16
申请号：US12647875
申请日：2009-12-28
申请人： Taek-Sang SONG , Dae-Han KWON , Jun-Woo LEE
发明人： Taek-Sang SONG , Dae-Han KWON , Jun-Woo LEE
IPC分类号： G05F1/10
CPC分类号： G05F1/56
摘要： An internal voltage generator includes: a detection unit configured to detect a level of an internal voltage in comparison to a reference voltage; a first driving unit configured to discharge an internal voltage terminal, through which the internal voltage is outputted, in response to an output signal of the detection unit; a current detection unit configured to detect a discharge current flowing through the first driving unit; and a second driving unit configured to charge the internal voltage terminal in response to an output signal of the current detection unit.
摘要翻译：内部电压发生器包括：检测单元，被配置为与参考电压相比检测内部电压的电平; 第一驱动单元，被配置为响应于所述检测单元的输出信号，对输出所述内部电压的内部电压端子进行放电; 电流检测单元，被配置为检测流过所述第一驱动单元的放电电流; 以及第二驱动单元，其被配置为响应于所述电流检测单元的输出信号对所述内部电压端子进行充电。

2. 发明申请

US20110121860A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20110121860A1
公开(公告)日：2011-05-26
申请号：US12648477
申请日：2009-12-29
申请人： Taek-Sang SONG , Dae-Han Kwon , Jun-Woo Lee
发明人： Taek-Sang SONG , Dae-Han Kwon , Jun-Woo Lee
IPC分类号： H03K19/0175 , H03K19/094
CPC分类号： H03K19/017509 , H03K19/018514 , H03K19/018528
摘要： A semiconductor device includes a swing level shifting unit configured to use a first power supply voltage as a power supply voltage, receive a CML clock swinging around a first voltage level, and shift a swing reference voltage level of the CML clock to a second voltage level lower than the first voltage level, and a CML clock transfer buffering unit configured to use a second power supply voltage as a power supply voltage and buffer the CML clock, which is transferred from the swing level shifting unit and swings around the second voltage level.
摘要翻译：一种半导体器件包括：摆动电平移位单元，被配置为使用第一电源电压作为电源电压，接收围绕第一电压电平摆动的CML时钟，并将CML时钟的摆幅参考电压电平移位到第二电压电平低于第一电压电平的CML时钟传送缓冲单元，以及CML时钟传送缓冲单元，被配置为使用第二电源电压作为电源电压，并缓冲从摆动电平移位单元传送的CML时钟，并围绕第二电压电平摆动。

3. 发明申请

US20110181332A1 RING OSCILLATOR FOR GENERATING OSCILLATING CLOCK SIGNAL 有权
标题翻译：用于产生振荡时钟信号的振荡器
公开(公告)号：US20110181332A1
公开(公告)日：2011-07-28
申请号：US13081119
申请日：2011-04-06
申请人： Taek-Sang SONG , Dae-Han Kwon , Dae-Kun Yoon
发明人： Taek-Sang SONG , Dae-Han Kwon , Dae-Kun Yoon
IPC分类号： H03H11/22
CPC分类号： H03K3/0322 , H03K23/542
摘要： A ring oscillator including a plurality of buffer units, each of which has a cross-coupled structure, for generating clock signals using a bias voltage having a predetermined voltage level applied thereto, wherein the clock signals have a swing width corresponding to the bias voltage.
摘要翻译：一种环形振荡器，包括多个缓冲单元，每个缓冲单元具有交叉耦合结构，用于使用施加有预定电压电平的偏置电压来产生时钟信号，其中时钟信号具有对应于偏置电压的摆幅宽度。

4. 发明申请

US20090322399A1 CLOCK GENERATING CIRCUIT AND CLOCK GENERATING METHOD THEREOF 有权
标题翻译：时钟发生电路及其产生方法
公开(公告)号：US20090322399A1
公开(公告)日：2009-12-31
申请号：US12325346
申请日：2008-12-01
申请人： Dae-Han KWON , Taek-Sang SONG
发明人： Dae-Han KWON , Taek-Sang SONG
IPC分类号： G06F1/06
CPC分类号： G06F1/06
摘要： A clock generating circuit, including a pulse generating unit to generate a plurality of pulse signals based on a reference clock, the pulse signals each having the same period, a phase difference between the adjacent pulse signals being a first phase difference; and a multi-phase clock generating unit to generate a plurality of multi-phase clocks, a phase difference between the adjacent multi-phase clocks being equal to a second phase difference between pulse signals of a pulse signal pair, based on a plurality of unit-phase clock generating units receiving the pulse signal pairs.
摘要翻译：一种时钟发生电路，包括：脉冲发生单元，用于基于参考时钟产生多个脉冲信号;每个脉冲信号具有相同的周期;相邻脉冲信号之间的相位差是第一相位差; 以及多相时钟发生单元，用于生成多个多相时钟，相邻的多相时钟之间的相位差等于脉冲信号对的脉冲信号之间的第二相位差，基于多个单位接收脉冲信号对的相位时钟发生单元。

5. 发明申请

US20110273937A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20110273937A1
公开(公告)日：2011-11-10
申请号：US13186366
申请日：2011-07-19
申请人： Dae-Kun YOON , Dae-Han KWON , Taek-Sang SONG
发明人： Dae-Kun YOON , Dae-Han KWON , Taek-Sang SONG
IPC分类号： G11C8/18
CPC分类号： G11C7/22 , G11C7/1066 , G11C7/1072 , G11C7/222 , H03L7/0814
摘要： A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of the edge detector to detect whether clocks of the same pair have a phase difference of 180 degrees and detect whether clocks of different pairs have a phase difference of 90 degrees, a control signal generator configured to generate a control signal for controlling phases of the clocks according to an output signal of the comparator, and a phase corrector configured to correct phases of the clocks in response to the control signal.
摘要翻译：半导体存储器件包括边缘检测器，被配置为接收两对互补时钟以检测时钟的边沿;比较器，被配置为比较边缘检测器的输出信号，以检测同一对的时钟是否具有180度的相位差;以及检测不同对的时钟是否具有90度的相位差，控制信号发生器被配置为根据比较器的输出信号产生用于控制时钟相位的控制信号;以及相位校正器，被配置为校正时钟的相位响应于控制信号。

6. 发明申请

US20090322394A1 RING OSCILLATOR AND MULTI-PHASE CLOCK CORRECTION CIRCUIT USING THE SAME 审中-公开
标题翻译：环振荡器和多相时钟校正电路
公开(公告)号：US20090322394A1
公开(公告)日：2009-12-31
申请号：US12266608
申请日：2008-11-07
申请人： Taek-Sang SONG , Dae-Han Kwon , Dae-Kun Yoon
发明人： Taek-Sang SONG , Dae-Han Kwon , Dae-Kun Yoon
IPC分类号： H03K5/12 , H03K3/03
CPC分类号： H03K3/0322 , H03K23/542
摘要： A ring oscillator including a plurality of buffer units, each of which has a cross-coupled structure, for generating clock signals using a bias voltage having a predetermined voltage level applied thereto, wherein the clock signals have a swing width corresponding to the bias voltage.
摘要翻译：一种环形振荡器，包括多个缓冲单元，每个缓冲单元具有交叉耦合结构，用于使用施加有预定电压电平的偏置电压来产生时钟信号，其中时钟信号具有对应于偏置电压的摆幅宽度。

7. 发明申请

US20120262323A1 BUFFER CONTROL CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME 有权
标题翻译：缓冲器控制电路和集成电路，包括它们
公开(公告)号：US20120262323A1
公开(公告)日：2012-10-18
申请号：US13333983
申请日：2011-12-21
申请人： Taek-Sang SONG , Dae-Han Kwon
发明人： Taek-Sang SONG , Dae-Han Kwon
IPC分类号： H04L17/02
CPC分类号： H03K5/2481 , H03K19/0027 , H03K19/0948
摘要： A buffer control circuit includes a current supply unit configured to supply current and adjust the current in response to codes, an amplifying buffer configured to operate using the current and output a value obtained by comparing a reference potential and the reference potential, a second buffer configured to buffer an output of the first buffer, and a code generation unit configured to generate the codes in response to an output of the second buffer.
摘要翻译：缓冲器控制电路包括：电流供给单元，被配置为响应于代码提供电流并调节电流;放大缓冲器，被配置为使用电流进行操作并输出通过比较参考电位和参考电位获得的值;配置的第二缓冲器以缓冲第一缓冲器的输出;以及代码生成单元，被配置为响应于第二缓冲器的输出而生成代码。

8. 发明申请

US20110204943A1 DELAY CELL AND PHASE LOCKED LOOP USING THE SAME 有权
标题翻译：延迟细胞和相位锁定环使用它
公开(公告)号：US20110204943A1
公开(公告)日：2011-08-25
申请号：US13102938
申请日：2011-05-06
申请人： Taek-Sang SONG , Kyung-Hoon KIM , Dae-Han KWON
发明人： Taek-Sang SONG , Kyung-Hoon KIM , Dae-Han KWON
IPC分类号： H03L7/08
CPC分类号： H03L7/0995 , H03K3/0322 , H03K5/133 , H03K2005/00208 , H03K2005/00234 , H03L2207/06
摘要： A phase locked loop that generates an internal clock by controlling a delay time of a delay cell according to conditions of PVT, thereby improving a jitter characteristic of the internal clock. The delay cell includes a first current controller for controlling first and second currents in response to a control voltage, and a second current controller for controlling the first and second currents in response to frequency range selection signals. The phase locked loop includes a phase comparator for comparing a reference clock with a feedback clock, a control voltage generator for generating a control voltage corresponding to an output of the phase comparator, and a voltage controlled oscillator for generating an internal clock having a frequency in response to the control voltage and one or more frequency range control signals, wherein the feedback clock is generated using the internal clock.
摘要翻译：通过根据PVT的条件控制延迟单元的延迟时间来产生内部时钟的锁相环，从而提高内部时钟的抖动特性。延迟单元包括响应于控制电压控制第一和第二电流的第一电流控制器，以及响应频率范围选择信号控制第一和第二电流的第二电流控制器。锁相环包括用于将参考时钟与反馈时钟进行比较的相位比较器，用于产生对应于相位比较器的输出的控制电压的控制电压发生器和用于产生具有频率的内部时钟的压控振荡器响应于控制电压和一个或多个频率范围控制信号，其中使用内部时钟产生反馈时钟。

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