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1. 发明授权

US6154829A Cascaded arithmetic pipeline data processor 失效
标题翻译：级联算术流水线数据处理器
公开(公告)号：US6154829A
公开(公告)日：2000-11-28
申请号：US174562
申请日：1998-10-19
申请人： Yoshiteru Mino , Tadashi Okamoto , Hiroshi Kadota
发明人： Yoshiteru Mino , Tadashi Okamoto , Hiroshi Kadota
IPC分类号： G06F9/38 , G06F7/38
CPC分类号： G06F9/3861 , G06F9/3867 , G06F9/3869 , G06F9/3875
摘要： Five processing units, namely one data memory, three arithmetic units, and one data memory, are connected together in a cascade arrangement so as to form a single arithmetic pipeline. Likewise, five control devices are connected together in a cascade arrangement and a control signal requesting that a series of data processing operations should start is sent to the first stage control device. Each control device starts to send a micro instruction to a corresponding processing unit upon detection of a processing start request bit in the received control signal and sends a signal which lags the control signal by a delay time equal to a number of cycles required to complete a processing operation of the processing unit, to the next stage control device. The first stage control device is provided with a loop counter operable to count the number of times processing is repeated and automatically generates a processing start request and a processing end request to the next stage control device.
摘要翻译：五个处理单元，即一个数据存储器，三个运算单元和一个数据存储器，以级联布置连接在一起，以形成单个运算管线。类似地，五个控制装置以级联布置连接在一起，并且要求将一系列数据处理操作开始的控制信号发送到第一级控制装置。每个控制装置在检测到所接收的控制信号中的处理开始请求位后，开始向对应的处理单元发送微指令，并发送一个延迟时间等于完成一个控制信号所需周期的延迟时间的信号处理单元的处理操作，到下一级控制装置。第一级控制装置设置有循环计数器，用于对重复处理的次数进行计数，并且自动地向下一级控制装置生成处理开始请求和处理结束请求。

2. 发明授权

US06230175B1 Reconfigurable digit-serial arithmetic system having a plurality of digit-serial arithmetic units 失效
标题翻译：具有多个数字串行运算单元的可重构数字串行运算系统
公开(公告)号：US06230175B1
公开(公告)日：2001-05-08
申请号：US09188388
申请日：1998-11-10
申请人： Tadashi Okamoto , Hiroshi Kadota , Yoshiteru Mino
发明人： Tadashi Okamoto , Hiroshi Kadota , Yoshiteru Mino
IPC分类号： G06F1531
CPC分类号： G06F7/5324 , G06F7/49994 , G06F7/504 , G06F7/57 , G06F2207/386
摘要： A bus for data transmission, bus switches for slicing the bus, and four arithmetic blocks are provided to perform a series of fixed-point arithmetic operations. Each of the four arithmetic blocks has a plurality of digit-serial arithmetic units, namely a multiplier, an adder/subtracter, and a shifter. Each of the digit-serial arithmetic units has the functions of receiving a plurality of input digits representative of an input operand and a digit position indicator of each of the input digits and providing a plurality of result digits representative of an arithmetic result of the input operand and a digit position indicator of each of the result digits to any other one of the plurality of digit-serial arithmetic units. Particularly, the digit-serial adder/subtracter contains therein a selector for input switching so that the digit-serial adder/subtracter can perform butterfly arithmetic.
摘要翻译：提供用于数据传输的总线，用于分割总线的总线开关和四个运算块，以执行一系列定点算术运算。四个算术块中的每一个具有多个数字串行运算单元，即乘法器，加法器/减法器和移位器。每个数字串行运算单元具有接收表示每个输入数字的输入操作数和数字位置指示符的多个输入数字的功能，并提供表示输入操作数的算术结果的多个结果数字以及每个结果数字的数字位置指示符到多个数字串行运算单元中的任何另一个。特别地，数字串联加法器/减法器包含用于输入切换的选择器，使得数字串行加法器/减法器可以执行蝴蝶运算。

3. 发明授权

US06125438A Data processor 失效
标题翻译：数据处理器
公开(公告)号：US06125438A
公开(公告)日：2000-09-26
申请号：US63009
申请日：1998-04-21
申请人： Tadashi Okamoto , Hiroshi Kadota , Yoshiteru Mino
发明人： Tadashi Okamoto , Hiroshi Kadota , Yoshiteru Mino
IPC分类号： G06F15/78 , G06F15/00
CPC分类号： G06F15/7857 , G06F15/7864
摘要： A data processor of the invention includes plural memories, plural arithmetic units, a data transfer unit and a network. The data transfer unit transfers various data to predetermined memories, and switches the connections between the memories and the arithmetic units by using the network. The control unit adds a processability judgement signal to a data read from a predetermined memory in reading the data, so as to make a pair of the data and the processability judgement signal. Each of the arithmetic units receives the data and the processability judgement signal, conducts predetermined processing on the received data, delays the received processability judgement signal by the number of cycles equal to its own processing cycle, and outputs resultant data obtained through the processing and the delayed processability judgement signal. Accordingly, in storing ultimate resultant data in a predetermined storage unit, the storage unit stores the ultimate resultant data as effective data on the basis of the processability judgement signal added to the resultant data. The data processor attains wide application and can be applied to various types of multimedia applications by switching the connections between the memories and the arithmetic units by using the network.
摘要翻译：本发明的数据处理器包括多个存储器，多个运算单元，数据传送单元和网络。数据传送单元将各种数据传送到预定存储器，并且通过使用网络来切换存储器和算术单元之间的连接。控制单元在读取数据时，对从预定存储器读取的数据添加可处理性判断信号，以便形成一对数据和加工性判定信号。每个算术单元接收数据和可处理性判断信号，对接收到的数据进行预定的处理，将接收到的加工性判断信号延迟等于其自身的处理周期的周期数，并输出通过处理获得的结果数据和延迟加工性判断信号。因此，在将最终结果数据存储在预定存储单元中时，存储单元基于加到结果数据的加工性判断信号将最终结果数据存储为有效数据。数据处理器具有广泛的应用，可以通过使用网络切换存储器和算术单元之间的连接来应用于各种类型的多媒体应用。

4. 发明授权

US5754618A Image processing apparatus and image processing method for favorably enhancing continuous boundaries which are affected by noise 失效
标题翻译：图像处理装置和图像处理方法，有利于增强受噪声影响的连续边界
公开(公告)号：US5754618A
公开(公告)日：1998-05-19
申请号：US772756
申请日：1996-12-23
申请人： Tadashi Okamoto , Yoshiteru Mino , Hiroshi Kadota
发明人： Tadashi Okamoto , Yoshiteru Mino , Hiroshi Kadota
IPC分类号： G06T5/20 , G06K9/00
CPC分类号： G06T5/20 , A61B8/13 , A61B8/483 , Y10S378/901
摘要： An image processing apparatus which performs a process which enhances incongruous pixel values in an original image, including an object pixel selecting unit for selecting an object pixel out of pixels which compose the original image, a plurality n of filter units, each of which extracts pixel values of a set of pixels, including the selected object pixel, on one of a predetermined surface and a predetermined line which pass through the object pixel, out of pixels in a predetermined range, wherein each predetermined surface and predetermined line is at a different inclination, a relative size comparing unit for comparing pixels values of each set of pixels extracted by each filter unit and specifying a filter unit whose pixel values best approximate to a predetermined standard, and a first pixel value enhancing unit for enhancing a pixel value of the object pixel based on only the pixel values of the specified filter unit.
摘要翻译：一种图像处理装置，其执行增强原始图像中的不协调像素值的处理，包括用于选择构成原始图像的像素中的对象像素的对象像素选择单元，其中每个滤色器单元提取像素在预定范围内的像素中，在预定表面和穿过对象像素的预定线之一上的包括所选择的对象像素的一组像素的值，其中每个预定表面和预定线处于不同的倾斜度相对尺寸比较单元，用于比较由每个滤波器单元提取的每组像素的像素值，并指定最佳近似于预定标准的像素值的滤波器单元;以及第一像素值增强单元，用于增强对象的像素值仅基于指定滤波器单元的像素值的像素。

5. 发明授权

US4879687A Memory device having valid bit storage units to be reset in batch 失效
标题翻译：具有有效位存储单元的存储器件将被批量复位
公开(公告)号：US4879687A
公开(公告)日：1989-11-07
申请号：US59763
申请日：1987-06-08
申请人： Tadashi Okamoto , Hiroshi Kadota , Jiro Miyake , Ichiro Okabayashi , Yoshinori Maeda
发明人： Tadashi Okamoto , Hiroshi Kadota , Jiro Miyake , Ichiro Okabayashi , Yoshinori Maeda
IPC分类号： G06F12/16 , G06F12/08 , G11C7/00 , G11C7/10 , G11C7/20 , G11C11/41
CPC分类号： G11C11/41 , G06F12/0891 , G11C7/1006 , G11C7/20
摘要： A memory device includes plural word data storing rows. Each word data storing row is composed of a plurality of data bit cells for storing the word data, and a valid bit cell for indicating the validity of data. The valid bit cell has a reset circuit composed of FETs, and the reset circuits are connected to one reset line. By applying a reset signal to one reset line, plural valid bit cells are reset as a batch.
摘要翻译：存储装置包括多个字数据存储行。每个字数据存储行由用于存储字数据的多个数据位单元和用于指示数据有效性的有效位单元组成。有效位单元具有由FET组成的复位电路，并且复位电路连接到一个复位线。通过将复位信号施加到一个复位线，多个有效位单元被重新分批。

6. 发明授权

US4910668A Address conversion apparatus 失效
标题翻译：地址转换装置
公开(公告)号：US4910668A
公开(公告)日：1990-03-20
申请号：US100561
申请日：1987-09-24
申请人： Tadashi Okamoto , Hiroshi Kadota , Masaitsu Nakajima
发明人： Tadashi Okamoto , Hiroshi Kadota , Masaitsu Nakajima
IPC分类号： G06F12/10 , G06F12/12 , G11C15/04
CPC分类号： G06F12/1036 , G06F12/123
摘要： An address conversion apparatus includes a content addressable memory for storing a plurality of logical addresses, and a random access memory for storing a plurality of physical addresses corresponding to the logical addresses. When an input logical address is received, a search is conducted to find the same logical address stored in the memory. When the same logical address is found, the content addressable memory causes the random access memory to output a corresponding physical address. The content addressable memory includes a plurality of logical address storage units. Each unit has a plurality of data bit cells for storing address data and a process identification number cell for storing a process identification number. Thereby, a plurality of logical addresses which correspond to different processes are stored in the single content addressable memory.
摘要翻译：地址转换装置包括用于存储多个逻辑地址的内容可寻址存储器和用于存储对应于逻辑地址的多个物理地址的随机存取存储器。当接收到输入逻辑地址时，进行搜索以找到存储在存储器中的相同逻辑地址。当找到相同的逻辑地址时，内容可寻址存储器使随机存取存储器输出相应的物理地址。内容可寻址存储器包括多个逻辑地址存储单元。每个单元具有用于存储地址数据的多个数据位单元和用于存储处理标识号的处理标识号单元。因此，与单个内容可寻址存储器中存储对应于不同进程的多个逻辑地址。

7. 发明授权

US07921281B2 Processor and program execution method capable of efficient program execution 有权
标题翻译：处理器和程序执行方法能够高效地执行程序
公开(公告)号：US07921281B2
公开(公告)日：2011-04-05
申请号：US12110513
申请日：2008-04-28
申请人： Kazushi Kurata , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazuya Furukawa , Shigeki Fujii , Toshio Sugimura
发明人： Kazushi Kurata , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazuya Furukawa , Shigeki Fujii , Toshio Sugimura
IPC分类号： G06F9/48 , G06F9/52
CPC分类号： G06F9/4881 , G06F9/3851 , G06F9/3867 , G06F9/462
摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.
摘要翻译：一种处理器，用于使用存储在与所述程序一对一的存储器中的多个寄存器值组来顺序地执行多个程序。处理器包括多个寄存器组; 选择/切换单元，其可操作以选择所述多个寄存器组中的一个作为程序执行所基于的执行目标寄存器组，并且每当经过第一预定时间时切换所述选择目标; 恢复单元，其可操作以在每次执行切换时将所述寄存器值组中的一个恢复为未被选择为所述执行目标寄存器组的寄存器组之一; 保存单元，其可操作以通过重写与寄存器值相对应的存储器中的寄存器值组来在恢复之前保存用于恢复的寄存器组中的值; 以及程序执行单元，其可操作以在每次执行切换时执行与执行目标寄存器组中的寄存器值组相对应的程序。

8. 发明申请

US20080209162A1 PROCESSOR AND PROGRAM EXECUTION METHOD CAPABLE OF EFFICIENT PROGRAM EXECUTION 有权
公开(公告)号：US20080209162A1
公开(公告)日：2008-08-28
申请号：US12110491
申请日：2008-04-28
申请人： Kazuya Furukawa , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazushi Kurata , Shigeki Fujii , Toshio Sugimura
发明人： Kazuya Furukawa , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazushi Kurata , Shigeki Fujii , Toshio Sugimura
IPC分类号： G06F9/30
CPC分类号： G06F9/4881 , G06F9/3851 , G06F9/3867 , G06F9/462
摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

9. 发明申请

US20050102440A1 Circuit group control system 审中-公开
公开(公告)号：US20050102440A1
公开(公告)日：2005-05-12
申请号：US11009607
申请日：2004-12-08
申请人： Nobuo Higaki , Tetsuya Tanaka , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura
发明人： Nobuo Higaki , Tetsuya Tanaka , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura
IPC分类号： G06F9/38 , G06F3/00 , G06F9/46 , G06F9/48 , G06F13/28 , G06F15/16 , G06F15/167 , G06F15/80
CPC分类号： G06F9/4843
摘要： A circuit group control system which receives from a master processor a first command sequence and a second command sequence each of which is composed of a plurality of commands, each command being to be executed by one of a plurality of circuits, and causes any available circuits to execute the commands one by one in order of arrangement in each command sequence. The circuit group control system achieves concurrent execution of a plurality of command sequences by causing a circuit (a second circuit) to execute a command in the second command sequence while another circuit (a first circuit) is executing another command in the first command sequence.

10. 发明授权

US07930520B2 Processor and program execution method capable of efficient program execution 有权
公开(公告)号：US07930520B2
公开(公告)日：2011-04-19
申请号：US12110539
申请日：2008-04-28
申请人： Kazushi Kurata , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazuya Furukawa , Shigeki Fujii , Toshio Sugimura
发明人： Kazushi Kurata , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazuya Furukawa , Shigeki Fujii , Toshio Sugimura
IPC分类号： G06F9/30 , G06F9/44 , G06F1/32
CPC分类号： G06F9/4881 , G06F9/3851 , G06F9/3867 , G06F9/462
摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

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