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1. 发明授权

US06314441B1 Robust method for providing tap leakage in adaptive equalizer systems 失效
标题翻译：在自适应均衡器系统中提供抽头泄漏的鲁棒方法
公开(公告)号：US06314441B1
公开(公告)日：2001-11-06
申请号：US08841749
申请日：1997-04-30
申请人： Kalavai Janardhan Raghunath
发明人： Kalavai Janardhan Raghunath
IPC分类号： G06F1531
CPC分类号： H04L25/03012 , H04L2025/03375 , H04L2025/03471 , H04L2025/03617 , H04L2025/03681
摘要： A method is described for producing coefficient leakage in an adaptive filter/equalizer without the need for using an adder/subtractor for each coefficient. Specifically, a method is provided for incrementally reducing the magnitude of one or more coefficients in an adaptive filter/equalizer solely through a defined manipulation of certain bits in that coefficient, such bit manipulation being carried out on a periodic basis. The period for such bit manipulation will generally track the frequency of adaptation iteration for such a filter/equalizer.
摘要翻译：描述了一种用于在自适应滤波器/均衡器中产生系数泄漏的方法，而不需要对每个系数使用加法器/减法器。具体地，提供了一种仅通过对该系数中的某些位的定义的操纵逐渐减小自适应滤波器/均衡器中的一个或多个系数的幅度的方法，这样的位操作是在周期性的基础上执行的。这种位操作的周期通常将跟踪这种滤波器/均衡器的适应性迭代的频率。

2. 发明授权

US06263290B1 Process and machine for signal waveform analysis 失效
标题翻译：信号波形分析的过程和机器
公开(公告)号：US06263290B1
公开(公告)日：2001-07-17
申请号：US08393307
申请日：1995-02-22
申请人： Michael K. Williams , Daniel J. Coffey
发明人： Michael K. Williams , Daniel J. Coffey
IPC分类号： G06F1531
CPC分类号： G01R23/16
摘要： Highly accurate time interval measurement is achieved for an electrical waveform. The electrical waveform is sampled and converted to a series of voltages, and the series of voltages is interpolated in order to form a time tag list, using interpolations that are optimized for time interval measurement and analysis. The time tag list accurately represents the times at which particular events of interest occur, and is used to generate displays and results analysis such as adjacent cycle jitter and accurate differential triggering and analysis.
摘要翻译：对电波形进行高精度的时间间隔测量。电波形被采样并转换为一系列电压，并且使用针对时间间隔测量和分析优化的内插，内插一系列电压以形成时间标签列表。时间标签列表准确地表示感兴趣的特定事件发生的时间，并用于生成显示和结果分析，例如相邻周期抖动和精确的差分触发和分析。

3. 发明授权

US06230175B1 Reconfigurable digit-serial arithmetic system having a plurality of digit-serial arithmetic units 失效
标题翻译：具有多个数字串行运算单元的可重构数字串行运算系统
公开(公告)号：US06230175B1
公开(公告)日：2001-05-08
申请号：US09188388
申请日：1998-11-10
申请人： Tadashi Okamoto , Hiroshi Kadota , Yoshiteru Mino
发明人： Tadashi Okamoto , Hiroshi Kadota , Yoshiteru Mino
IPC分类号： G06F1531
CPC分类号： G06F7/5324 , G06F7/49994 , G06F7/504 , G06F7/57 , G06F2207/386
摘要： A bus for data transmission, bus switches for slicing the bus, and four arithmetic blocks are provided to perform a series of fixed-point arithmetic operations. Each of the four arithmetic blocks has a plurality of digit-serial arithmetic units, namely a multiplier, an adder/subtracter, and a shifter. Each of the digit-serial arithmetic units has the functions of receiving a plurality of input digits representative of an input operand and a digit position indicator of each of the input digits and providing a plurality of result digits representative of an arithmetic result of the input operand and a digit position indicator of each of the result digits to any other one of the plurality of digit-serial arithmetic units. Particularly, the digit-serial adder/subtracter contains therein a selector for input switching so that the digit-serial adder/subtracter can perform butterfly arithmetic.
摘要翻译：提供用于数据传输的总线，用于分割总线的总线开关和四个运算块，以执行一系列定点算术运算。四个算术块中的每一个具有多个数字串行运算单元，即乘法器，加法器/减法器和移位器。每个数字串行运算单元具有接收表示每个输入数字的输入操作数和数字位置指示符的多个输入数字的功能，并提供表示输入操作数的算术结果的多个结果数字以及每个结果数字的数字位置指示符到多个数字串行运算单元中的任何另一个。特别地，数字串联加法器/减法器包含用于输入切换的选择器，使得数字串行加法器/减法器可以执行蝴蝶运算。

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