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1. 发明申请

US20160064223A1 METHOD OF FORMING METAL GATE ELECTRODE 有权
标题翻译：形成金属电极电极的方法
公开(公告)号：US20160064223A1
公开(公告)日：2016-03-03
申请号：US14936939
申请日：2015-11-10
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Cheng-Hao HOU , Peng-Soon LIM , Da-Yuan LEE , Xiong-Fei YU , Chun-Yuan CHOU , Fan-Yi HSU , Jian-Hao CHEN , Kuang-Yuan HSU
IPC分类号： H01L21/28 , H01L29/66
CPC分类号： H01L21/28026 , H01L21/28088 , H01L29/401 , H01L29/4966 , H01L29/51 , H01L29/66477 , H01L29/66545 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： An aspect of this description relates to a method that includes partially filling an opening in a dielectric material with a high-dielectric-constant material. The method also includes partially filling the opening with a first metal material over the high-dielectric-constant material. The method further includes filling the opening with a capping layer over the first metal material. The method additionally includes partially removing the first metal material and the capping layer in the opening using a wet etching process in a solution including one or more of H2O2, NH4OH, HCl, H2SO4 or diluted HF. The method also includes fully removing the remaining capping layer in the opening using a wet etching process in a solution includes one or more of NH4OH or diluted HF. The method further includes depositing a second metal material in the opening over the remaining first metal material.
摘要翻译：本说明书的一个方面涉及一种方法，其包括用高介电常数材料部分地填充电介质材料中的开口。该方法还包括用高介电常数材料上的第一金属材料部分地填充开口。该方法还包括用第一金属材料上的覆盖层填充开口。该方法还包括在包括H 2 O 2，NH 4 OH，HCl，H 2 SO 4或稀释的HF中的一种或多种的溶液中使用湿法蚀刻工艺部分去除开口中的第一金属材料和封盖层。该方法还包括在溶液中使用湿蚀刻工艺完全去除开口中的剩余覆盖层，其中包括一种或多种NH 4 OH或稀释的HF。该方法还包括在剩余的第一金属材料上的开口中沉积第二金属材料。

2. 发明申请

US20140295659A1 METHOD OF MAKING A GATE STRUCTURE 有权
标题翻译：制作门结构的方法
公开(公告)号：US20140295659A1
公开(公告)日：2014-10-02
申请号：US14300867
申请日：2014-06-10
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Peng-Soon LIM , Da-Yuan LEE , Kuang-Yuan HSU
IPC分类号： H01L29/49 , H01L29/51
CPC分类号： H01L29/4966 , H01L21/28008 , H01L21/823842 , H01L29/495 , H01L29/4983 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： A method of making a gate structure includes forming a trench in a dielectric layer. The method further includes forming a gate dielectric layer in the trench. The gate dielectric layer defines an opening in the dielectric layer. The method includes forming a gate electrode in the opening. Forming the gate electrode includes filling a width of a bottom portion of the opening with a first metal material. The first metal material has a recess. Forming the gate electrode includes filling an entire width of a top portion of the opening with a homogeneous second metal material. The homogeneous second metal material has a protrusion extending into the recess, and a maximum width of the homogeneous second metal material is equal to a maximum width of the first metal material. A top surface of the gate dielectric layer is co-planar with a top surface of the homogeneous second metal material.
摘要翻译：制造栅极结构的方法包括在电介质层中形成沟槽。该方法还包括在沟槽中形成栅极电介质层。栅极电介质层在电介质层中限定开口。该方法包括在开口中形成栅电极。形成栅电极包括用第一金属材料填充开口的底部的宽度。第一金属材料具有凹部。形成栅极电极包括用均匀的第二金属材料填充开口的顶部的整个宽度。均匀的第二金属材料具有延伸到凹部中的突起，并且均匀的第二金属材料的最大宽度等于第一金属材料的最大宽度。栅极电介质层的顶表面与均匀的第二金属材料的顶表面共面。

3. 发明申请

US20150140765A1 METHOD OF FABRICATING A GATE DIELECTRIC LAYER 有权
标题翻译：制造栅极介电层的方法
公开(公告)号：US20150140765A1
公开(公告)日：2015-05-21
申请号：US14585802
申请日：2014-12-30
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Wei-Yang LEE , Xiong-Fei YU , Da-Yuan LEE , Kuang-Yuan HSU
IPC分类号： H01L29/66 , H01L29/51
CPC分类号： H01L29/66477 , H01L21/28185 , H01L21/823857 , H01L29/42368 , H01L29/513 , H01L29/66545
摘要： A method of making a semiconductor device, the method includes forming an active region in a substrate. The method further includes forming a first gate structure over the active region, where the forming the first gate structure includes forming a first interfacial layer. An entirety of a top surface of the first interfacial layer is a curved convex surface. Furthermore, the method includes forming a first high-k dielectric over the first interfacial layer. Additionally, the method includes forming a first gate electrode over a first portion of the first high-k dielectric and surrounded by a second portion of the first high-k dielectric.
摘要翻译：一种制造半导体器件的方法，所述方法包括在衬底中形成有源区。该方法还包括在有源区上形成第一栅极结构，其中形成第一栅极结构包括形成第一界面层。第一界面层的整个顶面是弯曲的凸面。此外，该方法包括在第一界面层上形成第一高k电介质。另外，该方法包括在第一高k电介质的第一部分上形成第一栅极，并被第一高k电介质的第二部分包围。

4. 发明申请

US20140004694A1 METAL GATE ELECTRODE OF A FIELD EFFECT TRANSISTOR 有权
标题翻译：场效应晶体管的金属栅极电极
公开(公告)号：US20140004694A1
公开(公告)日：2014-01-02
申请号：US14018087
申请日：2013-09-04
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Cheng-Hao HOU , Peng-Soon LIM , Da-Yuan LEE , Xiong-Fei YU , Chun-Yuan CHOU , Fan-Yi HSU , Jian-Hao CHEN , Kuang-Yuan HSU
IPC分类号： H01L29/40
CPC分类号： H01L21/28026 , H01L21/28088 , H01L29/401 , H01L29/4966 , H01L29/51 , H01L29/66477 , H01L29/66545 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a metal gate electrode of a field effect transistor includes forming a dielectric layer over an active region, and forming an opening in the dielectric layer. The method further includes partially filling the opening with a high-dielectric-constant material, partially filling the opening with a conformal first metal material over the high-dielectric-constant material, and filling the opening with a capping layer over the first metal material. The method further includes partially removing the first metal material and capping layer in the opening using a wet etching process. The method further includes fully removing the remaining capping layer in the opening using a wet etching process. The method further includes depositing a second metal material in the opening over the remaining first metal material, and planarizing the second metal material.
摘要翻译：制造场效应晶体管的金属栅电极的方法包括在有源区上形成电介质层，并在电介质层中形成开口。该方法还包括用高介电常数材料部分地填充开口，用高介电常数材料上的共形第一金属材料部分地填充开口，并且在第一金属材料上用覆盖层填充开口。该方法还包括使用湿蚀刻工艺部分去除开口中的第一金属材料和封盖层。该方法还包括使用湿蚀刻工艺完全去除开口中的剩余盖层。该方法还包括在剩余的第一金属材料上的开口中沉积第二金属材料，以及平坦化第二金属材料。

5. 发明公开

US20240379806A1 SEMICONDUCTOR DEVICES HAVING SILICIDE LAYER 审中-公开
公开(公告)号：US20240379806A1
公开(公告)日：2024-11-14
申请号：US18784139
申请日：2024-07-25
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chia-Ming HSU , Pei-Yu CHOU , Chih-Pin TSAO , Kuang-Yuan HSU , Jyh-Huei CHEN
IPC分类号： H01L29/45 , H01L21/02 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L21/8234 , H01L23/485 , H01L23/532 , H01L27/088 , H01L29/417 , H01L29/66 , H01L29/78
CPC分类号： H01L29/45 , H01L21/32053 , H01L21/76802 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76867 , H01L21/76877 , H01L21/76889 , H01L21/76897 , H01L21/823418 , H01L23/485 , H01L23/53209 , H01L23/53238 , H01L23/53266 , H01L27/0886 , H01L29/41791 , H01L29/665 , H01L29/66795 , H01L21/0214 , H01L21/02167 , H01L21/0217 , H01L21/28518 , H01L21/76805 , H01L21/76843 , H01L21/76855 , H01L29/7848
摘要： A semiconductor device includes a source/drain region, a source/drain silicide layer formed on the source/drain region, and a first contact disposed over the source/drain silicide layer. The first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.

6. 发明申请

US20170287913A1 SEMICONDUCTOR DEVICE WITH METAL GATE 审中-公开
公开(公告)号：US20170287913A1
公开(公告)日：2017-10-05
申请号：US15626348
申请日：2017-06-19
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Da-Yuan LEE , Kuang-Yuan HSU
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/66 , H01L29/51 , H01L29/49 , H01L29/78
CPC分类号： H01L27/0922 , H01L21/823842 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/78
摘要： A semiconductor device including a first gate structure is disposed on the semiconductor substrate. The first gate structure includes a gate dielectric layer, a layer, a first work function metal, a second work function metal, and a fill metal. A second gate structure is also disposed on the semiconductor substrate. The second gate structure includes the gate dielectric layer, a second work function metal, and the fill metal. In an embodiment, the second gate structure also includes an etch stop layer.

7. 发明申请

US20220181143A1 APPARATUS FOR MANUFACTURING A THIN FILM AND A METHOD THEREFOR 有权
公开(公告)号：US20220181143A1
公开(公告)日：2022-06-09
申请号：US17592091
申请日：2022-02-03
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
发明人： Tsai-Fu HSIAO , Kuang-Yuan HSU , Pei-Ren JENG , Tze-Liang LEE
IPC分类号： H01L21/02 , C23C16/455 , H01L21/687 , H01L21/677 , H01L21/67 , C23C16/54
摘要： An apparatus includes a vacuum chamber, a wafer transfer mechanism, a first gas source, a second gas source and a reuse gas pipe. The vacuum chamber is divided into at least three reaction regions including a first reaction region, a second reaction region and a third reaction region. The wafer transfer mechanism is structured to transfer a wafer from the first reaction region to the third reaction region via the second reaction region. The first gas source supplies a first gas to the first reaction region via a first gas pipe, and a second gas source supplies a second gas to the second reaction region via a second gas pipe. The reuse gas pipe is connected between the first reaction region and the third reaction region for supplying an unused first gas collected in the first reaction region to the third reaction region.

8. 发明申请

US20140291777A1 BUFFER LAYER ON SEMICONDUCTOR DEVICES 审中-公开
标题翻译：半导体器件上的缓冲层
公开(公告)号：US20140291777A1
公开(公告)日：2014-10-02
申请号：US14303045
申请日：2014-06-12
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Cheng-Hao HOU , Wei-Yang LEE , Xiong-Fei YU , Kuang-Yuan HSU
IPC分类号： H01L29/51 , H01L29/49
CPC分类号： H01L29/517 , H01L21/28088 , H01L29/4941 , H01L29/495 , H01L29/4958 , H01L29/4966 , H01L29/513 , H01L29/7833
摘要： A semiconductor device including a substrate having a source region, a drain region, and a channel region disposed between the source region and the drain region. Additionally, the semiconductor device includes a high-k dielectric layer formed over the channel region, an n-metal formed over the high-k dielectric layer and a barrier layer formed between the high-k dielectric layer and the n-metal, the barrier layer including a layer of annealed silicon.
摘要翻译：一种半导体器件，包括具有源区域，漏极区域和设置在源极区域和漏极区域之间的沟道区域的衬底。另外，半导体器件包括在沟道区上形成的高k电介质层，在高k电介质层上形成的n型金属和形成在高k电介质层和n型金属之间的势垒层，势垒层层包括退火硅层。

9. 发明公开

US20230170397A1 SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME 审中-公开
公开(公告)号：US20230170397A1
公开(公告)日：2023-06-01
申请号：US18103306
申请日：2023-01-30
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chia-Ming HSU , Pei-Yu CHOU , Chih-Pin TSAO , Kuang-Yuan HSU , Jyh-Huei CHEN
IPC分类号： H01L29/45 , H01L23/485 , H01L21/768 , H01L29/66 , H01L29/417 , H01L23/532 , H01L21/3205 , H01L21/8234 , H01L27/088
CPC分类号： H01L29/45 , H01L21/32053 , H01L21/76802 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76867 , H01L21/76877 , H01L21/76889 , H01L21/76897 , H01L21/823418 , H01L23/485 , H01L23/53209 , H01L23/53238 , H01L23/53266 , H01L27/0886 , H01L29/665 , H01L29/41791 , H01L29/66795 , H01L21/28518 , H01L21/76805 , H01L21/76855
摘要： A semiconductor device includes a source/drain region, a source/drain silicide layer formed on the source/drain region, and a first contact disposed over the source/drain silicide layer. The first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.

10. 发明申请

US20150357435A1 METHOD OF MAKING A GATE STRUCTURE 有权
标题翻译：制作门结构的方法
公开(公告)号：US20150357435A1
公开(公告)日：2015-12-10
申请号：US14829258
申请日：2015-08-18
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Peng-Soon LIM , Da-Yuan LEE , Kuang-Yuan HSU
IPC分类号： H01L29/66 , H01L21/28
CPC分类号： H01L29/4966 , H01L21/28008 , H01L21/823842 , H01L29/495 , H01L29/4983 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： A method of making a gate structure includes forming a gate electrode in an opening defined by a gate dielectric layer having a top surface. Forming the gate electrode includes filling a width of a bottom portion of the opening with a first metal material having a first resistance. Forming the gate electrode further includes defining a recess in the first metal material. Forming the gate electrode further includes filling an entire width of a top portion of the opening and the recess with a homogeneous second metal material having a second resistance less than the first resistance, wherein a maximum width of the homogeneous second metal material is equal to a maximum width of the first metal material, and the top surface of the gate dielectric layer is co-planar with a top surface of the homogeneous second metal material.
摘要翻译：制造栅极结构的方法包括在由具有顶表面的栅极介电层限定的开口中形成栅电极。形成栅电极包括用具有第一电阻的第一金属材料填充开口的底部的宽度。形成栅电极还包括在第一金属材料中限定凹陷。形成栅电极还包括用具有小于第一电阻的第二电阻的均匀的第二金属材料填充开口的顶部的整个宽度和凹部，其中均匀的第二金属材料的最大宽度等于第一金属材料的最大宽度和栅极电介质层的顶表面与均匀的第二金属材料的顶表面共面。

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