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1. 发明申请

US20070285146A1 Semiconductor device with pump circuit 有权
公开(公告)号：US20070285146A1
公开(公告)日：2007-12-13
申请号：US11822184
申请日：2007-07-03
申请人： Minoru Senda , Kiyohiro Furutani , Taku Ogura , Shigehiro Kuge , Satoshi Kawasaki , Tadaaki Yamauchi
发明人： Minoru Senda , Kiyohiro Furutani , Taku Ogura , Shigehiro Kuge , Satoshi Kawasaki , Tadaaki Yamauchi
IPC分类号： H03K3/00
CPC分类号： G11C16/30 , G11C5/145 , G11C16/04 , H02M3/073 , H02M2003/071 , H02M2003/075 , H02M2003/077 , H03K3/356113
摘要： In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of −9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.

2. 发明授权

US07365578B2 Semiconductor device with pump circuit 有权
标题翻译：带泵电路的半导体器件
公开(公告)号：US07365578B2
公开(公告)日：2008-04-29
申请号：US11822184
申请日：2007-07-03
申请人： Minoru Senda , Kiyohiro Furutani , Taku Ogura , Shigehiro Kuge , Satoshi Kawasaki , Tadaaki Yamauchi
发明人： Minoru Senda , Kiyohiro Furutani , Taku Ogura , Shigehiro Kuge , Satoshi Kawasaki , Tadaaki Yamauchi
IPC分类号： H03K3/00
CPC分类号： G11C16/30 , G11C5/145 , G11C16/04 , H02M3/073 , H02M2003/071 , H02M2003/075 , H02M2003/077 , H03K3/356113
摘要： In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of −9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.
摘要翻译：在本半导体器件中，正的驱动泵电路由外部电源电位EXVDD（例如1.8V）驱动以产生正电压VPC（例如2.4V）。用于内部操作的负泵电路由正电压VPC驱动以产生对于字线的擦除或类似的内部操作所需的负电压VNA（例如-9.2V）。用于内部操作的负泵电路可以具有较少数量的泵级，并且因此消耗比通过外部电源电压EXVDD（例如1.8V）驱动电路时更小的面积。

3. 发明授权

US07180362B2 Semiconductor device with pump circuit 有权
公开(公告)号：US07180362B2
公开(公告)日：2007-02-20
申请号：US10941004
申请日：2004-09-15
申请人： Minoru Senda , Kiyohiro Furutani , Taku Ogura , Shigehiro Kuge , Satoshi Kawasaki , Tadaaki Yamauchi
发明人： Minoru Senda , Kiyohiro Furutani , Taku Ogura , Shigehiro Kuge , Satoshi Kawasaki , Tadaaki Yamauchi
IPC分类号： G05F1/10
CPC分类号： G11C16/30 , G11C5/145 , G11C16/04 , H02M3/073 , H02M2003/071 , H02M2003/075 , H02M2003/077 , H03K3/356113
摘要： In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of −9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.

4. 发明申请

US20050057288A1 Semiconductor device with pump circuit 有权
标题翻译：带泵电路的半导体器件
公开(公告)号：US20050057288A1
公开(公告)日：2005-03-17
申请号：US10941004
申请日：2004-09-15
申请人： Minoru Senda , Kiyohiro Furutani , Taku Ogura , Shigehiro Kuge , Satoshi Kawasaki , Tadaaki Yamauchi
发明人： Minoru Senda , Kiyohiro Furutani , Taku Ogura , Shigehiro Kuge , Satoshi Kawasaki , Tadaaki Yamauchi
IPC分类号： G11C16/06 , G11C5/14 , G11C16/04 , G11C16/30 , H01L21/822 , H01L21/8247 , H01L27/04 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , H02M3/07 , H03L7/06
CPC分类号： G11C16/30 , G11C5/145 , G11C16/04 , H02M3/073 , H02M2003/071 , H02M2003/075 , H02M2003/077 , H03K3/356113
摘要： In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of −9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.
摘要翻译：在本半导体器件中，正的驱动泵电路由外部电源电位EXVDD（例如1.8V）驱动以产生正电压VPC（例如2.4V）。用于内部操作的负泵电路由正电压VPC驱动以产生对于字线的擦除或类似的内部操作所需的负电压VNA（例如-9.2V）。用于内部操作的负泵电路可以具有较少数量的泵级，并且因此消耗比通过外部电源电压EXVDD（例如1.8V）驱动电路时更小的面积。

5. 发明申请

US20070120592A1 Semiconductor device with pump circuit 有权
公开(公告)号：US20070120592A1
公开(公告)日：2007-05-31
申请号：US11699427
申请日：2007-01-30
申请人： Minoru Senda , Kiyohiro Furutani , Taku Ogura , Shigehiro Kuge , Satoshi Kawasaki , Tadaaki Yamauchi
发明人： Minoru Senda , Kiyohiro Furutani , Taku Ogura , Shigehiro Kuge , Satoshi Kawasaki , Tadaaki Yamauchi
IPC分类号： G05F1/10
CPC分类号： G11C16/30 , G11C5/145 , G11C16/04 , H02M3/073 , H02M2003/071 , H02M2003/075 , H02M2003/077 , H03K3/356113
摘要： In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of −9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.

6. 发明授权

US07268612B2 Semiconductor device with pump circuit 有权
标题翻译：带泵电路的半导体器件
公开(公告)号：US07268612B2
公开(公告)日：2007-09-11
申请号：US11699427
申请日：2007-01-30
申请人： Minoru Senda , Kiyohiro Furutani , Taku Ogura , Shigehiro Kuge , Satoshi Kawasaki , Tadaaki Yamauchi
发明人： Minoru Senda , Kiyohiro Furutani , Taku Ogura , Shigehiro Kuge , Satoshi Kawasaki , Tadaaki Yamauchi
IPC分类号： G05F1/10
CPC分类号： G11C16/30 , G11C5/145 , G11C16/04 , H02M3/073 , H02M2003/071 , H02M2003/075 , H02M2003/077 , H03K3/356113
摘要： In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of −9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.
摘要翻译：在本半导体器件中，正的驱动泵电路由外部电源电位EXVDD（例如1.8V）驱动以产生正电压VPC（例如2.4V）。用于内部操作的负泵电路由正电压VPC驱动以产生对于字线的擦除或类似的内部操作所需的负电压VNA（例如-9.2V）。用于内部操作的负泵电路可以具有较少数量的泵级，并且因此消耗比通过外部电源电压EXVDD（例如1.8V）驱动电路时更小的面积。

7. 发明授权

US06781900B2 Semiconductor memory device with enhanced reliability 失效
标题翻译：具有增强可靠性的半导体存储器件
公开(公告)号：US06781900B2
公开(公告)日：2004-08-24
申请号：US10234256
申请日：2002-09-05
申请人： Kiyohiro Furutani , Takeshi Hamamoto , Takashi Kubo , Shigehiro Kuge
发明人： Kiyohiro Furutani , Takeshi Hamamoto , Takashi Kubo , Shigehiro Kuge
IPC分类号： G11C2900
CPC分类号： G11C29/027 , G11C29/02
摘要： The semiconductor memory device has a formal mode and a test mode as operating modes. The program circuit includes a fuse element in which an address using a spare memory cell instead of a defective memory cell is programmed. The program circuit confirms a disconnection state of a fuse in a condition severer in the test mode than that in the normal mode. An anomaly is notified to outside by a detection circuit in a case where results are different between the test mode and the normal mode. In a case where a fuse is not completely blown, such a fuse can also be detected in the test mode to exclude a defective chip.
摘要翻译：半导体存储器件具有作为工作模式的形式模式和测试模式。该程序电路包括熔丝元件，其中使用备用存储单元而不是有缺陷存储单元的地址被编程。程序电路确认在测试模式下比在正常模式下更严格的状态下的熔断器的断开状态。在测试模式和正常模式之间的结果不同的情况下，通过检测电路将异常通知给外部。在保险丝没有完全熔断的情况下，也可以在测试模式中检测这样的保险丝以排除有缺陷的芯片。

8. 发明授权

US06962827B1 Semiconductor device capable of shortening test time and suppressing increase in chip area, and method of manufacturing semiconductor integrated circuit device 失效
标题翻译：能够缩短测试时间并抑制芯片面积增加的半导体器件，以及半导体集成电路器件的制造方法
公开(公告)号：US06962827B1
公开(公告)日：2005-11-08
申请号：US10640322
申请日：2003-08-14
申请人： Katsuya Furue , Shigeru Kikuda , Kiyohiro Furutani , Tetsushi Tanizaki , Shigehiro Kuge , Takashi Kono
发明人： Katsuya Furue , Shigeru Kikuda , Kiyohiro Furutani , Tetsushi Tanizaki , Shigehiro Kuge , Takashi Kono
IPC分类号： G01R31/28 , G01R31/3185 , G11C29/00 , G11C29/12 , G11C29/56 , H01L21/66 , H01L23/544
CPC分类号： H01L22/34 , G11C29/006 , G11C29/12 , G11C2029/0403 , H01L2924/0002 , H01L2924/00
摘要： A plurality of semiconductor integrated circuits and a plurality of TEG circuits are aligned and provided on a substrate. In the TEG circuit, a built-in test circuit is provided in a region which faces a semiconductor integrated circuit across a dicing line region. The built-in test circuit and the semiconductor integrated circuit are connected by an interconnection which is provided on the dicing line region. The interconnection is cut for isolation into chips.
摘要翻译：多个半导体集成电路和多个TEG电路对准并设置在基板上。在TEG电路中，在穿过切割线区域的面向半导体集成电路的区域中提供内置测试电路。内置测试电路和半导体集成电路通过设置在切割线区域上的互连来连接。互连被切割以分离成芯片。

9. 发明授权

US07042769B2 Semiconductor memory device capable of accurate and stable operation 有权
标题翻译：半导体存储器件能够准确稳定运行
公开(公告)号：US07042769B2
公开(公告)日：2006-05-09
申请号：US10938615
申请日：2004-09-13
申请人： Tadaaki Yamauchi , Kiyohiro Furutani
发明人： Tadaaki Yamauchi , Kiyohiro Furutani
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/109 , G11C7/10 , G11C7/1078 , G11C7/1087 , G11C7/1093
摘要： An external clock generating circuit generates a mode indicating signal at the “H” level and generates an external clock signal synchronized with a write command buffer signal, when a semiconductor memory device is not in an internal operation mode. When the semiconductor memory device enters an internal operation mode and the mode indicating signal makes a transition from “H” to “L”, the external clock signal is fixed at the “L” level. The external clock signal is not supplied to an external CUI, and the external CUI is set in a state in which reception of any external command is prohibited. Until the end of asynchronous reset, the mode indicating signal is kept at the “L” level, and thereafter raised to the “H” level, so that malfunction caused by an input of an external command during asynchronous reset period can be avoided.
摘要翻译：当半导体存储器件不处于内部操作模式时，外部时钟产生电路产生“H”电平的模式指示信号并产生与写入命令缓冲器信号同步的外部时钟信号。当半导体存储器件进入内部操作模式并且模式指示信号从“H”转变为“L”时，外部时钟信号固定在“L”电平。外部时钟信号不提供给外部CUI，外部CUI被设置为禁止接收任何外部命令的状态。直到异步复位结束为止，模式指示信号保持在“L”电平，然后升至“H”电平，从而避免在异步复位期间由外部指令输入引起的故障。

10. 发明授权

US07542363B2 Semiconductor memory device enhancing reliability in data reading 有权
标题翻译：半导体存储器件提高了数据读取的可靠性
公开(公告)号：US07542363B2
公开(公告)日：2009-06-02
申请号：US11082926
申请日：2005-03-18
申请人： Takashi Kubo , Takashi Itoh , Yasuhiro Kashiwazaki , Taku Ogura , Kiyohiro Furutani
发明人： Takashi Kubo , Takashi Itoh , Yasuhiro Kashiwazaki , Taku Ogura , Kiyohiro Furutani
IPC分类号： G11C7/02
CPC分类号： G11C11/5642 , G11C5/145 , G11C7/06 , G11C7/12 , G11C16/24 , G11C16/26 , G11C16/30 , G11C2207/065 , G11C2207/2227 , G11C2211/5634 , G11C2211/5645
摘要： An internal voltage generating circuit generates and supplies a boosted voltage higher than an internal power supply voltage, as an operating power supply voltage, to a sense amplifier in a read circuit for reading data of a memory cell. A bit line precharge current supplied via an internal data line is produced from the internal power supply voltage. It is possible to provide a nonvolatile semiconductor memory device, which can perform a precise sense operation and an accurate reading of data even under a low power supply voltage condition.
摘要翻译：内部电压产生电路产生并提供高于作为工作电源电压的内部电源电压的升压电压到用于读取存储器单元的数据的读取电路中的读出放大器。从内部电源电压产生经由内部数据线提供的位线预充电电流。可以提供一种非易失性半导体存储器件，即使在低电源电压条件下也能进行精确的读出操作和数据的精确读取。

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