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1. 发明授权

US06936922B1 Semiconductor package structure reducing warpage and manufacturing method thereof 有权
标题翻译：半导体封装结构减少翘曲及其制造方法
公开(公告)号：US06936922B1
公开(公告)日：2005-08-30
申请号：US10672886
申请日：2003-09-26
申请人： Sung Soon Park , Sang Jae Jang , Choon Heung Lee , Seon Goo Lee , Eun Sook Sohn , Sung Su Park
发明人： Sung Soon Park , Sang Jae Jang , Choon Heung Lee , Seon Goo Lee , Eun Sook Sohn , Sung Su Park
IPC分类号： H01L23/16 , H01L23/48 , H01L23/498 , H01L25/10 , H05K1/11 , H05K3/34
CPC分类号： H05K3/3436 , H01L23/16 , H01L23/49816 , H01L24/48 , H01L25/105 , H01L2224/48091 , H01L2224/48227 , H01L2225/1035 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/18165 , H01L2924/3511 , H05K1/111 , H05K2201/094 , H05K2201/09736 , Y02P70/613 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An electrical substrate useful for semiconductor packages is disclosed. The electrical substrate includes a core insulative layer. A first surface of the insulative layer has circuit patterns thereon. Some of the circuit patterns are stepped in their heights from the first surface, in that a first subportion of the circuit pattern, including a ball land, extends further from the first surface than a second subportion of the same circuit pattern, and also extends further from the first surface than a ball land of other circuit patterns. Accordingly, solder balls fused to the ball lands of the stepped circuit patterns extend further from the first surface than same-size solder balls fused to the ball lands of the non-stepped circuit patterns, thereby circumventing electrical connectivity problems that may arise from warpage of the electrical substrate.
摘要翻译：公开了一种可用于半导体封装的电气基板。电气基板包括芯绝缘层。绝缘层的第一表面具有电路图案。电路图案中的一些从第一表面上升到它们的高度，因为电路图形的第一子部分（包括球形区域）比第一表面的第一子部分比相同电路图案的第二子部分进一步延伸，并且还进一步延伸从第一个表面比其他电路图案的球场。因此，熔融到阶梯式电路图案的球台的焊球比与非阶梯式电路图案的球面熔合的相同尺寸的焊球相比，从第一表面延伸出来，从而避免了由于翘曲引起的电连接问题电气基板。

2. 发明授权

US07633763B1 Double mold memory card and its manufacturing method 有权
标题翻译：双模存储卡及其制造方法
公开(公告)号：US07633763B1
公开(公告)日：2009-12-15
申请号：US10766101
申请日：2004-01-28
申请人： Chul Woo Park , Suk Gu Ko , Sang Jae Jang , Sung Su Park , Choon Heung Lee
发明人： Chul Woo Park , Suk Gu Ko , Sang Jae Jang , Sung Su Park , Choon Heung Lee
IPC分类号： H05K7/02 , H05K7/06 , H05K7/08 , H05K7/10
CPC分类号： G06K19/07743 , G06K19/07724 , H01L2224/48091 , H01L2924/1815 , H05K1/117 , H05K3/284 , H05K2201/09036 , H05K2201/10159 , H05K2203/1316 , H05K2203/1572 , H01L2924/00014
摘要： A memory card comprising a substrate having opposed top and bottom surfaces and a plurality of terminals disposed on the bottom surface thereof. Mounted to the top surface of the substrate is at least one component which is itself electrically connected to the terminals of the substrate. Formed on the bottom surface of the substrate is a first encapsulation part. Formed on the top surface of the substrate is a second encapsulation part which encapsulates the component mounted thereto.
摘要翻译：一种存储卡，包括具有相对的顶表面和底表面的基底和设置在其底表面上的多个端子。安装到基板的顶表面的是至少一个本身电连接到基板的端子的部件。形成在基板的底面上的是第一封装部。形成在基板的顶表面上的是封装安装在其上的部件的第二封装部分。

3. 发明授权

US07042072B1 Semiconductor package and method of manufacturing the same which reduces warpage 失效
标题翻译：半导体封装及其制造方法，其减少翘曲
公开(公告)号：US07042072B1
公开(公告)日：2006-05-09
申请号：US10212496
申请日：2002-08-02
申请人： Young Ho Kim , Seok Hyun Choi , Choon Heung Lee , Sung Su Park , Sung Soon Park
发明人： Young Ho Kim , Seok Hyun Choi , Choon Heung Lee , Sung Su Park , Sung Soon Park
IPC分类号： H01L23/02 , H01L21/44
CPC分类号： H01L23/13 , H01L23/3128 , H01L23/49816 , H01L24/48 , H01L2224/48091 , H01L2224/48227 , H01L2224/85001 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/18165 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package and method of producing the same has a semiconductor die having a first face and a second face. A coating material is coupled to the second face of the semiconductor die. A substrate having a cavity is provided wherein the semiconductor die is placed within the cavity. An encapsulant is used to encapsulate the second face of the semiconductor die placed in the cavity. Connection members are provided to couple the semiconductor die and the substrate in order to transfer signals between the semiconductor die and the substrate. Terminal members are couple to the substrate to connect the semiconductor package to an external device. In the semiconductor package, a thermal expansion coefficient of the coating material C and a thermal expansion coefficient of the encapsulant E should be approximately equal in value in order to limit the problems associated with warpage.
摘要翻译：半导体封装及其制造方法具有具有第一面和第二面的半导体管芯。涂层材料耦合到半导体管芯的第二面。提供具有空腔的衬底，其中半导体管芯被放置在空腔内。密封剂用于封装放置在空腔中的半导体管芯的第二面。提供连接构件以耦合半导体管芯和衬底，以便在半导体管芯和衬底之间传输信号。端子构件耦合到衬底以将半导体封装连接到外部设备。在半导体封装中，为了限制与翘曲相关的问题，涂层材料C的热膨胀系数和密封剂E的热膨胀系数的值应近似相等。

4. 发明授权

US07220915B1 Memory card and its manufacturing method 有权
标题翻译：存储卡及其制造方法
公开(公告)号：US07220915B1
公开(公告)日：2007-05-22
申请号：US11060263
申请日：2005-02-17
申请人： Chul Woo Park , Sang Jae Jang , Sung Su Park , Choon Heung Lee , Suk Gu Ko
发明人： Chul Woo Park , Sang Jae Jang , Sung Su Park , Choon Heung Lee , Suk Gu Ko
IPC分类号： H05K3/28 , H01L23/02 , H01L23/495
CPC分类号： G11C29/48 , G11C29/1201 , H01L23/49855 , H01L24/48 , H01L2224/32225 , H01L2224/48137 , H01L2224/48227 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A memory card comprising a circuit board having opposed upper and lower circuit board surfaces, at least one test pad disposed on the upper circuit board surface, and a conductive pattern disposed on the lower circuit board surface and electrically connected to the test pad. Electrically connected to the conductive pattern of the circuit board is a leadframe which includes a plurality of leads, each of the leads having a signal pad portion. At least one electronic circuit element is attached to the lower circuit board surface and electrically connected to the leadframe and to the conductive pattern of the circuit board. A body at least partially encapsulates the circuit board, the leadframe and the electronic circuit element such that the test pad of the circuit board is exposed in an upper body surface of the body, and the signal pad portions of the leads of the leadframe are exposed in a lower body surface of the body.
摘要翻译：一种存储卡，包括具有相对的上电路板表面和下电路板表面的电路板，设置在上电路板表面上的至少一个测试焊盘和布置在下电路板表面上并电连接到测试焊盘的导电图案。电连接到电路板的导电图案的是引线框架，其包括多个引线，每个引线具有信号焊盘部分。至少一个电子电路元件附接到下电路板表面并电连接到引线框架和电路板的导电图案。主体至少部分地封装电路板，引线框架和电子电路元件，使得电路板的测试焊盘暴露在主体的上体表面中，并且引线框的引线的信号焊盘部分被暴露在身体的下半身表面。

5. 发明授权

US07201327B1 Memory card and its manufacturing method 有权
标题翻译：存储卡及其制造方法
公开(公告)号：US07201327B1
公开(公告)日：2007-04-10
申请号：US10967462
申请日：2004-10-18
申请人： Chul Woo Park , Sang Jae Jang , Sung Su Park , Choon Heung Lee , Suk Gu Ko
发明人： Chul Woo Park , Sang Jae Jang , Sung Su Park , Choon Heung Lee , Suk Gu Ko
IPC分类号： G06K19/06
CPC分类号： G06K19/077 , G06K19/07732 , H01L2224/32225 , H01L2224/32245 , H01L2224/48137 , H01L2224/48247 , H01L2224/73265 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/181 , H01L2924/00012
摘要： A memory card comprising a die paddle having opposed, generally planar first and second die paddle surfaces and multiple peripheral edge segments. Disposed along and in spaced relation to one of the peripheral edge segments of the die paddle is a plurality of contacts, each of which has opposed, generally planar first and second contact surfaces. An inner body partially encapsulates the die paddle and the contacts, the first contact surface of each of the contacts and the first die paddle surface of the die paddle being exposed in and substantially flush with a generally planar first inner body surface of the inner body. The inner body further defines a generally planar second inner body surface which is disposed in opposed relation to the first inner body surface, the second contact surface of each of the contacts being exposed in the second inner body surface. At least one electronic circuit element is attached to the first die paddle surface and electrically connected to at least one of the contacts. An outer body partially encapsulates the inner body such that the first die paddle surface, the first contact surface of each of the contacts, the first inner body surface and the electronic circuit element are covered by the outer body, with the second inner body surface and hence the second contact surface of each of the contacts not being covered by the outer body and thus exposed.
摘要翻译：一种存储卡，其包括具有相对的，大致平面的第一和第二管芯片表面和多个外围边缘部分的管芯焊盘。与模板的周边边缘部分中的一个相互间隔设置有多个触点，每个触点具有相对的大致平面的第一和第二接触表面。内部主体部分地封装管芯焊盘和触头，每个触头的第一接触表面和管芯焊盘的第一裸片焊盘表面暴露于内部主体的大致平面的第一内部主体表面并基本上与其平齐。内体进一步限定大致平坦的第二内体表面，其以与第一内体表面相对的方式设置，每个触头的第二接触表面暴露在第二内体表面中。至少一个电子电路元件附接到第一裸片表面并电连接到至少一个触点。外部主体部分地封装内部主体，使得第一裸片表面，每个触点的第一接触表面，第一内部主体表面和电子电路元件被外部主体覆盖，具有第二内部主体表面和因此每个触点的第二接触表面不被外体覆盖并因此被暴露。

6. 发明授权

US06995448B2 Semiconductor package including passive elements and method of manufacture 失效
公开(公告)号：US06995448B2
公开(公告)日：2006-02-07
申请号：US10107656
申请日：2002-03-25
申请人： Sang Ho Lee , Jun Young Yang , Seon Goo Lee , Jong Hae Hyun , Choon Heung Lee
发明人： Sang Ho Lee , Jun Young Yang , Seon Goo Lee , Jong Hae Hyun , Choon Heung Lee
IPC分类号： H01L29/00 , H01L23/02
CPC分类号： H01L24/32 , H01L23/52 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/83 , H01L25/16 , H01L2224/05554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16145 , H01L2224/16225 , H01L2224/27013 , H01L2224/32057 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83051 , H01L2224/83385 , H01L2924/00014 , H01L2924/01013 , H01L2924/01033 , H01L2924/01079 , H01L2924/07802 , H01L2924/10162 , H01L2924/14 , H01L2924/15151 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/18161 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19103 , H01L2924/351 , Y10S257/927 , H01L2924/00012 , H01L2924/3512 , H01L2924/00 , H01L2224/05599
摘要： A semiconductor package including passive elements and a method of manufacturing provide reduced package size, improved performance and higher process yield by mounting the passive elements beneath the semiconductor die on the substrate. The semiconductor die may be mounted above the passive elements by mechanically bonding the semiconductor die to the passive elements, mounting the passive elements within a recess in the substrate or mounting the semiconductor using an adhesive retaining wall on the substrate that protrudes above and extends around the passive elements. The recess may include an aperture through the substrate to vent the package to the outside environment or may comprise an aperture through the substrate and larger than the semiconductor die, permitting the encapsulation to entirely fill the aperture, covering the die and the passive elements to secure them mechanically within the package.

7. 发明授权

US06469258B1 Circuit board for semiconductor package 有权
标题翻译：半导体封装电路板
公开(公告)号：US06469258B1
公开(公告)日：2002-10-22
申请号：US09648946
申请日：2000-08-23
申请人： Choon Heung Lee , Won Dai Shin , Chang Hoon Ko , Won Sun Shin , Seon Goo Lee , Won Kyun Lee , Tae Hoan Jang , Jun Young Yang
发明人： Choon Heung Lee , Won Dai Shin , Chang Hoon Ko , Won Sun Shin , Seon Goo Lee , Won Kyun Lee , Tae Hoan Jang , Jun Young Yang
IPC分类号： H01R1204
CPC分类号： H05K1/0259 , H01L23/60 , H01L2924/0002 , H05K1/0215 , H05K3/0052 , H05K3/28 , H05K2201/09354 , H01L2924/00
摘要： A circuit board for semiconductor package is designed to provide a complete grounding with corresponding equipment in the manufacture of the semiconductor package based on a circuit board, thereby preventing a breakdown of the circuit board or semiconductor chip caused by electrostatic charges. The printed circuit board for semiconductor package includes: a resinous substrate; a chip mounting region formed on the top surface of the resinous substrate for mounting a semiconductor chip thereon; a plurality of fine circuit patterns radially disposed in the circumference of the chip mounting region and extending to the edge of the chip mounting region; a plurality of ball lands formed in an array on the bottom surface of the resinous substrate, to be fused to conductive balls; a conductive via hole connecting the circuit patterns on the top surface of the resinous substrate to the ball lands on the bottom surface of the resinous substrate; a cover coat applied to the top and bottom surfaces of the resinous substrate to protect the circuit patterns from an external environment and make the ball lands open to the exterior; and a means for removing electrostatic charges provided at the edge of the substrate and connected to the plural circuit patterns to remove electrostatic charges in the manufacture of semiconductors.
摘要翻译：用于半导体封装的电路板被设计为在基于电路板的半导体封装的制造中提供与相应设备的完全接地，从而防止由静电电荷引起的电路板或半导体芯片的损坏。用于半导体封装的印刷电路板包括：树脂基板; 芯片安装区，形成在树脂基板的顶表面上，用于在其上安装半导体芯片; 多个精细电路图案，其径向设置在芯片安装区域的周边并延伸到芯片安装区域的边缘; 在树脂基板的底面上以阵列形成的多个球状接头，与导电球熔合; 导电通孔，其将树脂基材的顶表面上的电路图案连接到树脂基材的底表面上的球接头; 涂覆在树脂基材的顶表面和底表面上的保护层，以保护电路图案免受外部环境的影响，并使球体向外露出; 以及用于去除设置在基板的边缘并连接到多个电路图案以在半导体制造中去除静电电荷的静电电荷的装置。

8. 发明授权

US06982485B1 Stacking structure for semiconductor chips and a semiconductor package using it 失效
标题翻译：用于半导体芯片的堆叠结构和使用它的半导体封装
公开(公告)号：US06982485B1
公开(公告)日：2006-01-03
申请号：US10076701
申请日：2002-02-13
申请人： Seon Goo Lee , Young Ho Kim , Choon Heung Lee
发明人： Seon Goo Lee , Young Ho Kim , Choon Heung Lee
IPC分类号： H01L23/48 , H01L23/52 , H01L23/28 , H01L29/40
CPC分类号： H01L24/85 , H01L23/36 , H01L23/49805 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L25/0657 , H01L2224/32145 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/48471 , H01L2224/48475 , H01L2224/48479 , H01L2224/4945 , H01L2224/73265 , H01L2224/78301 , H01L2224/85001 , H01L2224/85051 , H01L2224/85191 , H01L2224/85815 , H01L2224/85986 , H01L2225/0651 , H01L2225/06541 , H01L2225/06555 , H01L2225/06575 , H01L2225/06586 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/15321 , H01L2924/181 , H01L2224/85186 , H01L2924/00 , H01L2924/00012 , H01L2224/4554
摘要： A semiconductor package and method of producing the same has a substrate having a resin layer with first and second surfaces. A plurality of electrically conductive patterns are formed on the resin layer. An aperture is also formed at the center of the substrate. A first semiconductor chip has first and second surfaces. The second surface of the first semiconductor chip has a plurality of input/output pads formed thereon. The first semiconductor chip is placed in the aperture of the substrate. A plurality of first conductive wires connect the input/output pads of the first semiconductor chip to the electrically conductive patterns formed on the second surface of the resin layer. A second semiconductor chip having first and second surfaces is coupled to the first semiconductor chip. The second surface of the second semiconductor chip has a plurality of input/output pads formed thereon. A plurality of second conductive wires connect the input/output pads of the second semiconductor chip to the electrically conductive patterns formed on the second surface of the resin layer. An encapsulate is used to encapsulate the aperture of the substrate, the first and second semiconductor chips, and the first and second conductive wires. A plurality of conductive balls are coupled to the electrically conductive patterns formed on the second surface of the resin layer of the substrate.
摘要翻译：半导体封装及其制造方法具有具有第一和第二表面的树脂层的基板。在树脂层上形成多个导电图案。在基板的中心处还形成有孔。第一半导体芯片具有第一和第二表面。第一半导体芯片的第二表面具有形成在其上的多个输入/输出焊盘。第一半导体芯片被放置在基板的孔中。多个第一导线将第一半导体芯片的输入/输出焊盘连接到形成在树脂层的第二表面上的导电图案。具有第一和第二表面的第二半导体芯片被耦合到第一半导体芯片。第二半导体芯片的第二表面具有形成在其上的多个输入/输出焊盘。多个第二导线将第二半导体芯片的输入/输出焊盘连接到形成在树脂层的第二表面上的导电图案。封装用于封装基板，第一和第二半导体芯片以及第一和第二导线的孔径。多个导电球耦合到形成在基板的树脂层的第二表面上的导电图案。

9. 发明授权

US07375975B1 Enhanced durability memory card 有权
标题翻译：增强耐用性记忆卡
公开(公告)号：US07375975B1
公开(公告)日：2008-05-20
申请号：US11263428
申请日：2005-10-31
申请人： Sang Jae Jang , Chul Woo Park , Choon Heung Lee
发明人： Sang Jae Jang , Chul Woo Park , Choon Heung Lee
IPC分类号： H05K5/03 , H05K9/00
CPC分类号： G06K19/07745 , G06K19/07728 , G06K19/07732 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/00
摘要： In accordance with the present invention, there is provided multiple embodiments of a memory card, each embodiment including a case which is cooperatively engaged to a module comprising at least a printed circuit board having an electronic circuit device mounted thereto. In each embodiment of the present invention, the case is reinforced by a stiffener which effectively increases the mechanical strength of the fully fabricated memory card, thus providing the capability to withstand typical bending and twisting tests. The stiffener may be provided in any one of a plurality of different shapes or profiles, and may embedded within one or more of various locations within the case.
摘要翻译：根据本发明，提供了存储卡的多个实施例，每个实施例包括与至少包括安装有电子电路装置的印刷电路板的模块配合地接合的壳体。在本发明的每个实施例中，通过加强件增强了外壳，该加强件有效地增加了完全制造的存储卡的机械强度，从而提供了经受典型的弯曲和扭曲试验的能力。加强件可以以多种不同形状或轮廓中的任何一种形式提供，并且可以嵌入壳体内的各种位置的一个或多个中。

10. 发明授权

US07837120B1 Modular memory card and method of making same 有权
标题翻译：模块化存储卡及其制作方法
公开(公告)号：US07837120B1
公开(公告)日：2010-11-23
申请号：US11288906
申请日：2005-11-29
申请人： Sang Jae Jang , Chul Woo Park , Choon Heung Lee
发明人： Sang Jae Jang , Chul Woo Park , Choon Heung Lee
IPC分类号： G06K19/06
CPC分类号： G06K19/07732
摘要： In accordance with the present invention, there is provided multiple embodiments of a memory card, each embodiment including a module comprising at least a printed circuit board having an electronic circuit device mounted thereto. The module is inserted into a complementary cavity formed within a case of the memory card, such case generally defining the outer appearance of the memory card. The module is secured within the cavity of the case through the use of an adhesive. In each embodiment of the present invention, the module is uniquely configured to prevent adhesive leakage from within the corresponding cavity of the case of the memory card when the module is secured within the cavity.
摘要翻译：根据本发明，提供了存储卡的多个实施例，每个实施例包括至少包括安装有电子电路装置的印刷电路板的模块。模块被插入形成在存储卡的壳体内的互补空腔中，这种情况通常限定存储卡的外观。模块通过使用粘合剂固定在外壳的腔内。在本发明的每个实施例中，模块被独特地构造成当模块固定在空腔内时，防止粘合剂从存储卡的壳体的相应空腔内泄漏。

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