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1. 发明授权

US06469258B1 Circuit board for semiconductor package 有权
标题翻译：半导体封装电路板
公开(公告)号：US06469258B1
公开(公告)日：2002-10-22
申请号：US09648946
申请日：2000-08-23
申请人： Choon Heung Lee , Won Dai Shin , Chang Hoon Ko , Won Sun Shin , Seon Goo Lee , Won Kyun Lee , Tae Hoan Jang , Jun Young Yang
发明人： Choon Heung Lee , Won Dai Shin , Chang Hoon Ko , Won Sun Shin , Seon Goo Lee , Won Kyun Lee , Tae Hoan Jang , Jun Young Yang
IPC分类号： H01R1204
CPC分类号： H05K1/0259 , H01L23/60 , H01L2924/0002 , H05K1/0215 , H05K3/0052 , H05K3/28 , H05K2201/09354 , H01L2924/00
摘要： A circuit board for semiconductor package is designed to provide a complete grounding with corresponding equipment in the manufacture of the semiconductor package based on a circuit board, thereby preventing a breakdown of the circuit board or semiconductor chip caused by electrostatic charges. The printed circuit board for semiconductor package includes: a resinous substrate; a chip mounting region formed on the top surface of the resinous substrate for mounting a semiconductor chip thereon; a plurality of fine circuit patterns radially disposed in the circumference of the chip mounting region and extending to the edge of the chip mounting region; a plurality of ball lands formed in an array on the bottom surface of the resinous substrate, to be fused to conductive balls; a conductive via hole connecting the circuit patterns on the top surface of the resinous substrate to the ball lands on the bottom surface of the resinous substrate; a cover coat applied to the top and bottom surfaces of the resinous substrate to protect the circuit patterns from an external environment and make the ball lands open to the exterior; and a means for removing electrostatic charges provided at the edge of the substrate and connected to the plural circuit patterns to remove electrostatic charges in the manufacture of semiconductors.
摘要翻译：用于半导体封装的电路板被设计为在基于电路板的半导体封装的制造中提供与相应设备的完全接地，从而防止由静电电荷引起的电路板或半导体芯片的损坏。用于半导体封装的印刷电路板包括：树脂基板; 芯片安装区，形成在树脂基板的顶表面上，用于在其上安装半导体芯片; 多个精细电路图案，其径向设置在芯片安装区域的周边并延伸到芯片安装区域的边缘; 在树脂基板的底面上以阵列形成的多个球状接头，与导电球熔合; 导电通孔，其将树脂基材的顶表面上的电路图案连接到树脂基材的底表面上的球接头; 涂覆在树脂基材的顶表面和底表面上的保护层，以保护电路图案免受外部环境的影响，并使球体向外露出; 以及用于去除设置在基板的边缘并连接到多个电路图案以在半导体制造中去除静电电荷的静电电荷的装置。

2. 发明授权

US06995448B2 Semiconductor package including passive elements and method of manufacture 失效
公开(公告)号：US06995448B2
公开(公告)日：2006-02-07
申请号：US10107656
申请日：2002-03-25
申请人： Sang Ho Lee , Jun Young Yang , Seon Goo Lee , Jong Hae Hyun , Choon Heung Lee
发明人： Sang Ho Lee , Jun Young Yang , Seon Goo Lee , Jong Hae Hyun , Choon Heung Lee
IPC分类号： H01L29/00 , H01L23/02
CPC分类号： H01L24/32 , H01L23/52 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/83 , H01L25/16 , H01L2224/05554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16145 , H01L2224/16225 , H01L2224/27013 , H01L2224/32057 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83051 , H01L2224/83385 , H01L2924/00014 , H01L2924/01013 , H01L2924/01033 , H01L2924/01079 , H01L2924/07802 , H01L2924/10162 , H01L2924/14 , H01L2924/15151 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/18161 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19103 , H01L2924/351 , Y10S257/927 , H01L2924/00012 , H01L2924/3512 , H01L2924/00 , H01L2224/05599
摘要： A semiconductor package including passive elements and a method of manufacturing provide reduced package size, improved performance and higher process yield by mounting the passive elements beneath the semiconductor die on the substrate. The semiconductor die may be mounted above the passive elements by mechanically bonding the semiconductor die to the passive elements, mounting the passive elements within a recess in the substrate or mounting the semiconductor using an adhesive retaining wall on the substrate that protrudes above and extends around the passive elements. The recess may include an aperture through the substrate to vent the package to the outside environment or may comprise an aperture through the substrate and larger than the semiconductor die, permitting the encapsulation to entirely fill the aperture, covering the die and the passive elements to secure them mechanically within the package.

3. 发明授权

US06982485B1 Stacking structure for semiconductor chips and a semiconductor package using it 失效
标题翻译：用于半导体芯片的堆叠结构和使用它的半导体封装
公开(公告)号：US06982485B1
公开(公告)日：2006-01-03
申请号：US10076701
申请日：2002-02-13
申请人： Seon Goo Lee , Young Ho Kim , Choon Heung Lee
发明人： Seon Goo Lee , Young Ho Kim , Choon Heung Lee
IPC分类号： H01L23/48 , H01L23/52 , H01L23/28 , H01L29/40
CPC分类号： H01L24/85 , H01L23/36 , H01L23/49805 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L25/0657 , H01L2224/32145 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/48471 , H01L2224/48475 , H01L2224/48479 , H01L2224/4945 , H01L2224/73265 , H01L2224/78301 , H01L2224/85001 , H01L2224/85051 , H01L2224/85191 , H01L2224/85815 , H01L2224/85986 , H01L2225/0651 , H01L2225/06541 , H01L2225/06555 , H01L2225/06575 , H01L2225/06586 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/15321 , H01L2924/181 , H01L2224/85186 , H01L2924/00 , H01L2924/00012 , H01L2224/4554
摘要： A semiconductor package and method of producing the same has a substrate having a resin layer with first and second surfaces. A plurality of electrically conductive patterns are formed on the resin layer. An aperture is also formed at the center of the substrate. A first semiconductor chip has first and second surfaces. The second surface of the first semiconductor chip has a plurality of input/output pads formed thereon. The first semiconductor chip is placed in the aperture of the substrate. A plurality of first conductive wires connect the input/output pads of the first semiconductor chip to the electrically conductive patterns formed on the second surface of the resin layer. A second semiconductor chip having first and second surfaces is coupled to the first semiconductor chip. The second surface of the second semiconductor chip has a plurality of input/output pads formed thereon. A plurality of second conductive wires connect the input/output pads of the second semiconductor chip to the electrically conductive patterns formed on the second surface of the resin layer. An encapsulate is used to encapsulate the aperture of the substrate, the first and second semiconductor chips, and the first and second conductive wires. A plurality of conductive balls are coupled to the electrically conductive patterns formed on the second surface of the resin layer of the substrate.
摘要翻译：半导体封装及其制造方法具有具有第一和第二表面的树脂层的基板。在树脂层上形成多个导电图案。在基板的中心处还形成有孔。第一半导体芯片具有第一和第二表面。第一半导体芯片的第二表面具有形成在其上的多个输入/输出焊盘。第一半导体芯片被放置在基板的孔中。多个第一导线将第一半导体芯片的输入/输出焊盘连接到形成在树脂层的第二表面上的导电图案。具有第一和第二表面的第二半导体芯片被耦合到第一半导体芯片。第二半导体芯片的第二表面具有形成在其上的多个输入/输出焊盘。多个第二导线将第二半导体芯片的输入/输出焊盘连接到形成在树脂层的第二表面上的导电图案。封装用于封装基板，第一和第二半导体芯片以及第一和第二导线的孔径。多个导电球耦合到形成在基板的树脂层的第二表面上的导电图案。

4. 发明授权

US06936922B1 Semiconductor package structure reducing warpage and manufacturing method thereof 有权
标题翻译：半导体封装结构减少翘曲及其制造方法
公开(公告)号：US06936922B1
公开(公告)日：2005-08-30
申请号：US10672886
申请日：2003-09-26
申请人： Sung Soon Park , Sang Jae Jang , Choon Heung Lee , Seon Goo Lee , Eun Sook Sohn , Sung Su Park
发明人： Sung Soon Park , Sang Jae Jang , Choon Heung Lee , Seon Goo Lee , Eun Sook Sohn , Sung Su Park
IPC分类号： H01L23/16 , H01L23/48 , H01L23/498 , H01L25/10 , H05K1/11 , H05K3/34
CPC分类号： H05K3/3436 , H01L23/16 , H01L23/49816 , H01L24/48 , H01L25/105 , H01L2224/48091 , H01L2224/48227 , H01L2225/1035 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/18165 , H01L2924/3511 , H05K1/111 , H05K2201/094 , H05K2201/09736 , Y02P70/613 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An electrical substrate useful for semiconductor packages is disclosed. The electrical substrate includes a core insulative layer. A first surface of the insulative layer has circuit patterns thereon. Some of the circuit patterns are stepped in their heights from the first surface, in that a first subportion of the circuit pattern, including a ball land, extends further from the first surface than a second subportion of the same circuit pattern, and also extends further from the first surface than a ball land of other circuit patterns. Accordingly, solder balls fused to the ball lands of the stepped circuit patterns extend further from the first surface than same-size solder balls fused to the ball lands of the non-stepped circuit patterns, thereby circumventing electrical connectivity problems that may arise from warpage of the electrical substrate.
摘要翻译：公开了一种可用于半导体封装的电气基板。电气基板包括芯绝缘层。绝缘层的第一表面具有电路图案。电路图案中的一些从第一表面上升到它们的高度，因为电路图形的第一子部分（包括球形区域）比第一表面的第一子部分比相同电路图案的第二子部分进一步延伸，并且还进一步延伸从第一个表面比其他电路图案的球场。因此，熔融到阶梯式电路图案的球台的焊球比与非阶梯式电路图案的球面熔合的相同尺寸的焊球相比，从第一表面延伸出来，从而避免了由于翘曲引起的电连接问题电气基板。

5. 发明授权

US06879034B1 Semiconductor package including low temperature co-fired ceramic substrate 有权
标题翻译：半导体封装包括低温共烧陶瓷基板
公开(公告)号：US06879034B1
公开(公告)日：2005-04-12
申请号：US10427118
申请日：2003-05-01
申请人： Jun Young Yang , Sun Goo Lee , Choon Heung Lee
发明人： Jun Young Yang , Sun Goo Lee , Choon Heung Lee
IPC分类号： H01L21/56 , H01L23/31 , H01L23/49 , H01L23/495 , H01L23/498 , H01L23/64 , H01L25/065 , H01L23/053
CPC分类号： H01L21/568 , H01L21/56 , H01L21/561 , H01L23/3107 , H01L23/49531 , H01L23/49861 , H01L23/64 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L25/0655 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/4911 , H01L2224/49175 , H01L2224/73265 , H01L2224/97 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/09701 , H01L2924/15787 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/19107 , H01L2924/00014 , H01L2224/85 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor package comprising a low temperature co-fired ceramic substrate defining opposed top and bottom surfaces. The substrate comprises at least two stacked ceramic layers and electrically conductive patterns which extend between the layers and along the top surface of the substrate. Mounted to the top surface of the substrate and electrically connected to the conductive patterns is at least one semiconductor die. A plurality of leads extend at least partially about the substrate in spaced relation thereto. Each of the leads defines opposed top and bottom surfaces, the semiconductor die being electrically connected to at least one of the leads. A package body at least partially encapsulates the substrate, the semiconductor die and the leads such that at least a portion of the bottom surface of each of the leads is exposed in the package body.
摘要翻译：一种半导体封装，包括限定相对的顶表面和底表面的低温共烧陶瓷衬底。衬底包括至少两个堆叠的陶瓷层和在层之间并沿着衬底的顶表面延伸的导电图案。安装到基板的顶表面并电连接到导电图案是至少一个半导体管芯。多个引线至少部分地围绕基板间隔开地延伸。每个引线限定相对的顶表面和底表面，半导体管芯电连接到至少一个引线。封装体至少部分地封装衬底，半导体管芯和引线，使得每个引线的底表面的至少一部分暴露在封装主体中。

6. 发明授权

US08802494B2 Method of fabricating a semiconductor device having an interposer 有权
标题翻译：制造具有插入件的半导体器件的方法
公开(公告)号：US08802494B2
公开(公告)日：2014-08-12
申请号：US13454972
申请日：2012-04-24
申请人： Choon Heung Lee , Ki Cheol Bae , Do Hyun Na
发明人： Choon Heung Lee , Ki Cheol Bae , Do Hyun Na
IPC分类号： H01L21/00 , H01L21/82
CPC分类号： H01L24/85 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L24/48 , H01L24/73 , H01L25/065 , H01L25/0657 , H01L2224/06181 , H01L2224/06183 , H01L2224/13025 , H01L2224/16227 , H01L2224/17181 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73215 , H01L2224/73265 , H01L2224/85 , H01L2225/06506 , H01L2225/06541 , H01L2225/06551 , H01L2225/06572 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19011 , H01L2924/19041 , H01L2924/19103 , H01L2924/19104 , H01L2924/19107 , H01L2924/3011 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： The method of fabricating a semiconductor device may include forming a semiconductor die on a substrate, forming an interposer including at least one integrated circuit connected to the semiconductor die on the substrate or on the semiconductor die, and performing encapsulation to surround the semiconductor die and the interposer.
摘要翻译：制造半导体器件的方法可以包括在衬底上形成半导体管芯，形成包括至少一个集成电路的插入器，该至少一个集成电路连接到衬底上或半导体管芯上的半导体管芯，并且进行封装以包围半导体管芯和插入。

7. 发明授权

US07633763B1 Double mold memory card and its manufacturing method 有权
标题翻译：双模存储卡及其制造方法
公开(公告)号：US07633763B1
公开(公告)日：2009-12-15
申请号：US10766101
申请日：2004-01-28
申请人： Chul Woo Park , Suk Gu Ko , Sang Jae Jang , Sung Su Park , Choon Heung Lee
发明人： Chul Woo Park , Suk Gu Ko , Sang Jae Jang , Sung Su Park , Choon Heung Lee
IPC分类号： H05K7/02 , H05K7/06 , H05K7/08 , H05K7/10
CPC分类号： G06K19/07743 , G06K19/07724 , H01L2224/48091 , H01L2924/1815 , H05K1/117 , H05K3/284 , H05K2201/09036 , H05K2201/10159 , H05K2203/1316 , H05K2203/1572 , H01L2924/00014
摘要： A memory card comprising a substrate having opposed top and bottom surfaces and a plurality of terminals disposed on the bottom surface thereof. Mounted to the top surface of the substrate is at least one component which is itself electrically connected to the terminals of the substrate. Formed on the bottom surface of the substrate is a first encapsulation part. Formed on the top surface of the substrate is a second encapsulation part which encapsulates the component mounted thereto.
摘要翻译：一种存储卡，包括具有相对的顶表面和底表面的基底和设置在其底表面上的多个端子。安装到基板的顶表面的是至少一个本身电连接到基板的端子的部件。形成在基板的底面上的是第一封装部。形成在基板的顶表面上的是封装安装在其上的部件的第二封装部分。

8. 发明授权

US07362038B1 Surface acoustic wave (SAW) device package and method for packaging a SAW device 有权
标题翻译：表面声波（SAW）器件封装和SAW器件封装方法
公开(公告)号：US07362038B1
公开(公告)日：2008-04-22
申请号：US11108359
申请日：2005-04-18
申请人： Ho Cheol Jang , Choon Heung Lee , Seong Min Seo
发明人： Ho Cheol Jang , Choon Heung Lee , Seong Min Seo
IPC分类号： H01L41/08
CPC分类号： H03H9/1085 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2924/181 , H01L2924/19105 , H03H9/0542 , H03H9/059 , H01L2924/00012 , H01L2924/00014
摘要： A surface acoustic wave (SAW) device package and method for packaging a SAW device provide a surface excited device having a small footprint, low cost and streamlined manufacturing process. A substrate including a SAW active area on a first side is interconnected to external circuits and mechanically mounted via a plurality of metal pillars and an outer metal sealing wall. The sealing wall additionally provides protection from external environmental contamination and interference. The sealing wall may include a number of gaps to reduce stress due to differences in thermal expansion coefficients between the SAW substrate and the metal sealing wall and the gaps may be filled with a flexible sealant. The metal pillars may be round, square or other suitable shape and solder bump terminals may be added to the ends of the pillars and the bottom edge of the sealing wall.
摘要翻译：用于封装SAW器件的表面声波（SAW）器件封装和方法提供具有小占地面积，低成本和流线型制造工艺的表面激励器件。包括在第一侧上的SAW有源区的衬底互连到外部电路，并通过多个金属柱和外部金属密封壁机械地安装。密封壁还提供防止外部环境污染和干扰的保护。密封壁可以包括多个间隙，以减少由于SAW基底和金属密封壁之间的热膨胀系数的差异而产生的应力，并且间隙可填充有柔性密封剂。金属支柱可以是圆形，正方形或其它合适的形状，并且焊料凸块端子可以被添加到柱的端部和密封壁的底部边缘。

9. 发明授权

US06867071B1 Leadframe including corner leads and semiconductor package using same 有权
标题翻译：引线框架包括角引线和使用相同的半导体封装
公开(公告)号：US06867071B1
公开(公告)日：2005-03-15
申请号：US10194557
申请日：2002-07-12
申请人： Choon Heung Lee , Sung Sik Jang , Su Yol Yoo
发明人： Choon Heung Lee , Sung Sik Jang , Su Yol Yoo
IPC分类号： H01L21/44 , H01L23/31 , H01L23/495
CPC分类号： H01L23/49548 , H01L23/3107 , H01L23/49541 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/32245 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2224/73265 , H01L2924/00014 , H01L2924/01079 , H01L2924/181 , H01L2924/1815 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A leadframe comprising a frame body having four peripheral sides, each adjacent pair of which collectively defines a frame corner. Disposed within a central space or opening defined by the frame body is a die paddle including four peripheral edge segments, each adjacent pair of which collectively define a paddle corner. The leadframe also includes a plurality of tie bars, each of which comprises a first portion extending from a respective paddle corner of the die paddle and a second portion which extends angularly from the first portion and perpendicularly into connection with one of the sides of the frame body. Connected to and extending from the sides of the frame body toward and in spaced relation to respective ones of the peripheral edge segments of the die paddle are a plurality of leads. Additionally, connected to and extending from the sides of the frame body in close proximity to respective ones of the frame corners are a plurality of corner leads. Each of the corner leads extends in spaced, generally parallel relation to at least one of the peripheral edge segments of the die paddle.
摘要翻译：一种引线框架，包括具有四个周边的框体，每个相邻的一对共同限定框架角。设置在由框架体限定的中心空间或开口内的是包括四个周边边缘段的模片，每个相邻的一对共同限定了一个桨角。引线框还包括多个连接杆，每个连接杆包括从模桨的相应桨角延伸的第一部分和从第一部分角度地延伸并且垂直地与框架的一个侧面连接的第二部分身体。连接到框架体的侧面并且与模具板的相应的周边边缘部分间隔开并且与间隔开的部分延伸的是多个引线。另外，连接到框架主体的侧面并靠近相应的框架角部延伸的多个角部引线。每个拐角引线以与模板的至少一个周边边缘部分间隔开的大致平行的关系延伸。

10. 发明授权

US08183678B2 Semiconductor device having an interposer 有权
标题翻译：具有插入器的半导体器件
公开(公告)号：US08183678B2
公开(公告)日：2012-05-22
申请号：US12535316
申请日：2009-08-04
申请人： Choon Heung Lee , Ki Cheol Bae , Do Hyun Na
发明人： Choon Heung Lee , Ki Cheol Bae , Do Hyun Na
IPC分类号： H01L25/065 , H01L23/52 , H01L21/50
CPC分类号： H01L24/85 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L24/48 , H01L24/73 , H01L25/065 , H01L25/0657 , H01L2224/06181 , H01L2224/06183 , H01L2224/13025 , H01L2224/16227 , H01L2224/17181 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73215 , H01L2224/73265 , H01L2224/85 , H01L2225/06506 , H01L2225/06541 , H01L2225/06551 , H01L2225/06572 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19011 , H01L2924/19041 , H01L2924/19103 , H01L2924/19104 , H01L2924/19107 , H01L2924/3011 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： A semiconductor device and a method of fabricating the same. An interposer used for the semiconductor device includes integrated circuits therein to realize the functions of a decoupling capacitor, an ESD preventing circuit, an impedance matching circuit, and termination. The semiconductor device may include a semiconductor die with a through silicon via (TSV) structure having two or more through electrodes that pass through the semiconductor die, in which each of the through electrodes are connected to a respective bond pad of the semiconductor die.
摘要翻译：一种半导体器件及其制造方法。用于半导体器件的插入器包括其中的集成电路，以实现去耦电容器，ESD防止电路，阻抗匹配电路和终端的功能。半导体器件可以包括具有贯穿半导体管芯的两个或更多个贯通电极的贯穿硅通孔（TSV）结构的半导体管芯，其中每个通孔电极连接到半导体管芯的相应接合焊盘。

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