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1. 发明申请

US20060024950A1 Methods of forming metal contact structures and methods of fabricating phase-change memory devices using the same 有权
公开(公告)号：US20060024950A1
公开(公告)日：2006-02-02
申请号：US11084505
申请日：2005-03-18
申请人： Suk-Hun Choi , Byeong-ok Cho , Yoon-ho Son , Sang-don Nam
发明人： Suk-Hun Choi , Byeong-ok Cho , Yoon-ho Son , Sang-don Nam
IPC分类号： H01L21/4763
CPC分类号： H01L21/76877 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/16
摘要： Methods of forming a metal contact structure include forming an interlayer insulating layer on a substrate, etching the interlayer insulating layer to form a hole, depositing a metal layer on the surface of the interlayer insulating layer including inside the hole, planarizing the metal layer to provide a buried portion of the metal layer in the hole and to remove portions of the metal layer outside of the hole, etching-back the buried portion of the metal layer in the hole such that some of the portion of the metal layer within the hole remains and depositing a conductive layer on the surface of the interlayer insulating layer and the portion of the metal layer that remains within the hole. Methods of forming a phase change memory device are also provided.

2. 发明授权

US07622379B2 Methods of forming metal contact structures and methods of fabricating phase-change memory devices using the same 有权
标题翻译：形成金属接触结构的方法和使用其形成相变存储器件的方法
公开(公告)号：US07622379B2
公开(公告)日：2009-11-24
申请号：US11084505
申请日：2005-03-18
申请人： Suk-Hun Choi , Byeong-ok Cho , Yoon-ho Son , Sang-don Nam
发明人： Suk-Hun Choi , Byeong-ok Cho , Yoon-ho Son , Sang-don Nam
IPC分类号： H01L21/4763
CPC分类号： H01L21/76877 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/16
摘要： Methods of forming a metal contact structure include forming an interlayer insulating layer on a substrate, etching the interlayer insulating layer to form a hole, depositing a metal layer on the surface of the interlayer insulating layer including inside the hole, planarizing the metal layer to provide a buried portion of the metal layer in the hole and to remove portions of the metal layer outside of the hole, etching-back the buried portion of the metal layer in the hole such that some of the portion of the metal layer within the hole remains and depositing a conductive layer on the surface of the interlayer insulating layer and the portion of the metal layer that remains within the hole. Methods of forming a phase change memory device are also provided.
摘要翻译：形成金属接触结构的方法包括在基板上形成层间绝缘层，蚀刻层间绝缘层以形成孔，在包括孔内部的层间绝缘层的表面上沉积金属层，平坦化金属层以提供在孔中的金属层的掩埋部分并且去除孔的外部的金属层的部分，蚀刻孔中的金属层的掩埋部分，使得孔内的金属层的一些部分保持以及在所述层间绝缘层的表面和所述金属层中保留在所述孔内的部分的表面上沉积导电层。还提供了形成相变存储器件的方法。

3. 发明申请

US20060076641A1 Methods of fabricating phase changeable semiconductor memory devices including multi-plug conductive structures and related devices 审中-公开
标题翻译：制造包括多插头导电结构和相关装置的相变半导体存储器件的方法
公开(公告)号：US20060076641A1
公开(公告)日：2006-04-13
申请号：US11209938
申请日：2005-08-23
申请人： Byeong-Ok Cho , Sang-Don Nam , Suk-Hun Choi
发明人： Byeong-Ok Cho , Sang-Don Nam , Suk-Hun Choi
IPC分类号： H01L29/40 , H01L21/44
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/16 , H01L45/1675
摘要： In fabricating a phase changeable memory device, an insulating layer with an opening extending therethrough is formed on a substrate. A conductive structure is formed in the opening. The conductive structure includes a first conductive plug on opposing sidewalls of the opening and a surface therebetween and a second plug on the first conductive plug. The first conductive plug is between the second plug and the sidewalls of the opening and between the second plug and the surface therebetween. A lower electrode is formed on the first conductive plug, on the second plug, and on the insulating layer. The lower electrode extends outside the opening in the insulating layer. A phase changeable material layer is formed on the lower electrode, and an upper electrode is formed on the phase changeable material layer opposite the lower electrode.
摘要翻译：在制造相变存储器件时，在衬底上形成具有延伸通过其的开口的绝缘层。在开口中形成导电结构。导电结构包括位于开口的相对侧壁上的第一导电插塞和其间的表面，以及在第一导电插塞上的第二插头。第一导电插头位于第二插头和开口的侧壁之间以及第二插头与它们之间的表面之间。下电极形成在第一导电插塞上，第二插头上，绝缘层上。下电极延伸到绝缘层的开口的外侧。在下电极上形成相变材料层，在与下电极相对的相变材料层上形成上电极。

4. 发明申请

US20070243641A1 Method for forming ferroelectric memory device 有权
标题翻译：形成铁电存储器件的方法
公开(公告)号：US20070243641A1
公开(公告)日：2007-10-18
申请号：US11812141
申请日：2007-06-15
申请人： Yoon-Ho Son , Sang-Don Nam , Suk-Hun Choi
发明人： Yoon-Ho Son , Sang-Don Nam , Suk-Hun Choi
IPC分类号： H01L21/00
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/65
摘要： A ferroelectric memory device and a method of forming the same are provided. At least two lower electrode patterns are formed on an interlayer insulating layer covering a semiconductor substrate. A seed layer pattern filling a space between at least the two lower electrode patterns and having a planar surface is formed. A ferroelectric layer is formed on the lower electrode pattern and the seed layer pattern. An upper electrode overlapping the two lower electrode patterns is formed on the ferroelectric layer.
摘要翻译：提供了铁电存储器件及其形成方法。在覆盖半导体衬底的层间绝缘层上形成至少两个下电极图案。形成填充至少两个下电极图案之间并具有平坦表面的空间的晶种层图案。在下部电极图案和种子层图案上形成铁电体层。在强电介质层上形成与两个下电极图案重叠的上电极。

5. 发明申请

US20060027848A1 Ferroelectric memory device and method of forming the same 审中-公开
标题翻译：铁电存储器件及其形成方法
公开(公告)号：US20060027848A1
公开(公告)日：2006-02-09
申请号：US11196287
申请日：2005-08-04
申请人： Yoon-Ho Son , Sang-Don Nam , Suk-Hun Choi
发明人： Yoon-Ho Son , Sang-Don Nam , Suk-Hun Choi
IPC分类号： H01L29/94 , H01L21/00
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/65
摘要： A ferroelectric memory device and a method of forming the same are provided. At least two lower electrode patterns are formed on an interlayer insulating layer covering a semiconductor substrate. A seed layer pattern filling a space between at least the two lower electrode patterns and having a planar surface is formed. A ferroelectric layer is formed on the lower electrode pattern and the seed layer pattern. An upper electrode overlapping the two lower electrode patterns is formed on the ferroelectric layer.
摘要翻译：提供了铁电存储器件及其形成方法。在覆盖半导体衬底的层间绝缘层上形成至少两个下电极图案。形成填充至少两个下电极图案之间并具有平坦表面的空间的晶种层图案。在下部电极图案和种子层图案上形成铁电体层。在强电介质层上形成与两个下电极图案重叠的上电极。

6. 发明授权

US07517703B2 Method for forming ferroelectric memory device 有权
标题翻译：形成铁电存储器件的方法
公开(公告)号：US07517703B2
公开(公告)日：2009-04-14
申请号：US11812141
申请日：2007-06-15
申请人： Yoon-Ho Son , Sang-Don Nam , Suk-Hun Choi
发明人： Yoon-Ho Son , Sang-Don Nam , Suk-Hun Choi
IPC分类号： H01L21/00
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/65
摘要： A ferroelectric memory device and a method of forming the same are provided. At least two lower electrode patterns are formed on an interlayer insulating layer covering a semiconductor substrate. A seed layer pattern filling a space between at least the two lower electrode patterns and having a planar surface is formed. A ferroelectric layer is formed on the lower electrode pattern and the seed layer pattern. An upper electrode overlapping the two lower electrode patterns is formed on the ferroelectric layer.
摘要翻译：提供了铁电存储器件及其形成方法。在覆盖半导体衬底的层间绝缘层上形成至少两个下电极图案。形成填充至少两个下电极图案之间并具有平坦表面的空间的晶种层图案。在下部电极图案和种子层图案上形成铁电体层。在强电介质层上形成与两个下电极图案重叠的上电极。

7. 发明授权

US08034705B2 Method of forming a seam-free tungsten plug 有权
标题翻译：形成无缝钨丝塞的方法
公开(公告)号：US08034705B2
公开(公告)日：2011-10-11
申请号：US12460318
申请日：2009-07-16
申请人： Suk-Hun Choi , Chang-Ki Hong , Yoon-Ho Son , Ju-Young Jung
发明人： Suk-Hun Choi , Chang-Ki Hong , Yoon-Ho Son , Ju-Young Jung
IPC分类号： H01L21/4763
CPC分类号： H01L21/76888 , H01L21/76879 , H01L21/76883 , H01L27/24
摘要： A plug comprises a first insulating interlayer, a tungsten pattern and a tungsten oxide pattern. The first insulating interlayer has a contact hole formed therethrough on a substrate. The tungsten pattern is formed in the contact hole. The tungsten pattern has a top surface lower than an upper face of the first insulating interlayer. The tungsten oxide pattern is formed in the contact hole and on the tungsten pattern. The tungsten oxide pattern has a level face.
摘要翻译：插头包括第一绝缘中间层，钨图案和氧化钨图案。第一绝缘中间层具有在基板上形成的接触孔。钨图案形成在接触孔中。钨图案具有比第一绝缘中间层的上表面低的顶表面。氧化钨图案形成在接触孔和钨图案上。氧化钨图案具有水平面。

8. 发明授权

US07291556B2 Method for forming small features in microelectronic devices using sacrificial layers 失效
标题翻译：在使用牺牲层的微电子器件中形成小特征的方法
公开(公告)号：US07291556B2
公开(公告)日：2007-11-06
申请号：US10873388
申请日：2004-06-22
申请人： Suk-Hun Choi , Yoon-Ho Son , Sung-Lae Cho , Joon-Sang Park
发明人： Suk-Hun Choi , Yoon-Ho Son , Sung-Lae Cho , Joon-Sang Park
IPC分类号： H01L21/00
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/126 , H01L45/16
摘要： A dielectric layer is formed on a region of a microelectronic substrate. A sacrificial layer is formed on the dielectric layer, and portions of the sacrificial layer and the dielectric layer are removed to form an opening that exposes a portion of the region. A conductive layer is formed on the sacrificial layer and in the opening. Portions of the sacrificial layer and the conductive layer on the dielectric layer are removed to leave a conductive plug in the dielectric layer and in contact with the region. Removal of the sacrificial layer and portions of the conductive layer on the dielectric layer may include polishing to expose the sacrificial layer and to leave a conductive plug in the sacrificial layer and the dielectric layer, etching the sacrificial layer to expose the dielectric layer and leave a portion of the conductive plug protruding from the dielectric layer, and polishing to remove the protruding portion of the conductive plug. Phase-change memory devices formed by such techniques are also discussed.
摘要翻译：在微电子基板的区域上形成介电层。在电介质层上形成牺牲层，去除牺牲层和电介质层的部分以形成露出该区域的一部分的开口。在牺牲层和开口中形成导电层。去除部分牺牲层和电介质层上的导电层，以在电介质层中留下导电插塞并与该区域接触。消除牺牲层和电介质层上的导电层的部分可以包括抛光以暴露牺牲层并且在牺牲层和电介质层中留下导电插塞，蚀刻牺牲层以暴露电介质层并留下导电插头从电介质层突出的部分，并且抛光以去除导电插塞的突出部分。还讨论了通过这种技术形成的相变存储器件。

9. 发明申请

US20050250316A1 Methods for fabricating memory devices using sacrifical layers and memory devices fabricated by same 失效
标题翻译：用于制造使用牺牲层的存储器件和由其制造的存储器件的方法
公开(公告)号：US20050250316A1
公开(公告)日：2005-11-10
申请号：US11168894
申请日：2005-06-29
申请人： Suk-Hun Choi , Chang-Ki Hong , Yoon-Ho Son
发明人： Suk-Hun Choi , Chang-Ki Hong , Yoon-Ho Son
IPC分类号： H01L21/3205 , H01L21/44 , H01L21/4763 , H01L21/768 , H01L27/24
CPC分类号： H01L21/7684 , H01L21/76816 , H01L21/76831 , H01L21/76883 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： Methods are provided for fabricating contacts in integrated circuit devices, such as phase-change memories. A protection layer and a sacrificial layer are sequentially formed on a semiconductor substrate. A contact hole is formed through the sacrificial layer and the protection layer. A conductive layer is formed on the sacrificial layer and in the contact hole, and portions of the conductive layer and the sacrificial layer are removed to expose the protection layer and form a conductive plug protruding from the protection layer. A protruding portion of the conductive plug removed to leave a contact plug in the protection layer. A phase-change data storage element may be formed on the contact plug.
摘要翻译：提供了用于在诸如相变存储器的集成电路器件中制造触点的方法。在半导体衬底上依次形成保护层和牺牲层。通过牺牲层和保护层形成接触孔。在牺牲层和接触孔中形成导电层，并且去除导电层和牺牲层的部分以露出保护层并形成从保护层突出的导电插塞。去除导电塞的突出部分，以在保护层中留下接触塞。可以在接触插塞上形成相变数据存储元件。

10. 发明授权

US08148710B2 Phase-change memory device using a variable resistance structure 有权
标题翻译：使用可变电阻结构的相变存储器件
公开(公告)号：US08148710B2
公开(公告)日：2012-04-03
申请号：US12805824
申请日：2010-08-20
申请人： Suk-Hun Choi , Chang-Ki Hong , Yoon-Ho Son , Jang-Eun Heo
发明人： Suk-Hun Choi , Chang-Ki Hong , Yoon-Ho Son , Jang-Eun Heo
IPC分类号： H01L47/00 , H01L29/08 , H01L29/18
CPC分类号： H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/143 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： A phase-change memory device including a first contact region and a second contact region formed on a semiconductor substrate. A first insulating layer with a first contact hole and a second contact hole is disposed on the semiconductor substrate, exposing the first and second contact regions. A first conductive layer is disposed on the first insulating interlayer to fill the first and the second contact holes. A first protection layer pattern and a lower wiring protection pattern are disposed on the first conductive layer. A first contact with a first electrode and a second contact with a lower wiring are disposed so as to connect the first and second contact regions. A second protection layer with a second electrode is disposed on the first protection layer pattern and the lower wiring protection pattern. A via filled with a phase-change material is disposed between the first electrode and the second electrode.
摘要翻译：一种相变存储器件，包括形成在半导体衬底上的第一接触区域和第二接触区域。具有第一接触孔和第二接触孔的第一绝缘层设置在半导体衬底上，暴露第一和第二接触区域。第一导电层设置在第一绝缘中间层上以填充第一和第二接触孔。第一保护层图案和下布线保护图案设置在第一导电层上。设置与第一电极和与下布线的第二接触件的第一接触，以便连接第一和第二接触区域。具有第二电极的第二保护层设置在第一保护层图案和下布线保护图案上。填充有相变材料的通孔设置在第一电极和第二电极之间。

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