专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07443708B2 Low resistance plate line bus architecture 有权
标题翻译：低电阻板线总线架构
公开(公告)号：US07443708B2
公开(公告)日：2008-10-28
申请号：US11409628
申请日：2006-04-24
申请人： Sudhir Kumar Madan , Sung-Wei Lin , John Fong
发明人： Sudhir Kumar Madan , Sung-Wei Lin , John Fong
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , H01L27/11502
摘要： An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.
摘要翻译：描述了其中板线在字线方向上延伸的FeRAM存储器阵列，其在具有公共板线连接的阵列中提供减小的板线电阻。下板线电阻降低了板线上负尖峰的幅度，以减少FeCap去极化的可能性。多列存储器单元的两条或多条板条沿位线方向互连。一个或多个虚拟存储器单元列的一些或全部平板线也可互连，以减小板线电阻并且最小化阵列的有源单元的位线电容的任何增加。改进的FeRAM阵列提供了降低的数据错误率，特别是在快速的存储周期时间。

2. 发明申请

US20080084773A1 Methods and systems for accessing memory 有权
标题翻译：访问内存的方法和系统
公开(公告)号：US20080084773A1
公开(公告)日：2008-04-10
申请号：US11543338
申请日：2006-10-04
申请人： Sudhir Kumar Madan , Hugh P. Mcadams , Sung-Wei Lin
发明人： Sudhir Kumar Madan , Hugh P. Mcadams , Sung-Wei Lin
IPC分类号： G11C11/22 , G11C7/00 , G11C7/02
CPC分类号： G11C11/22 , G11C2207/005 , G11C2207/2281 , G11C2207/229
摘要： One aspect of the invention relates to a method for accessing a memory device. One embodiment relates to a method for accessing a memory device. In the method during a read operation, one data value is provided on a local IO line while complimentary local IO line that is associated with the local IO line is inactivated. During a write operation, another data value is provided on the local IO line and a complimentary data value is provided on the complimentary local IO line. Other systems and methods are also disclosed.
摘要翻译：本发明的一个方面涉及一种用于访问存储器件的方法。一个实施例涉及访问存储器件的方法。在读操作期间的方法中，在本地IO线上提供一个数据值，而与本地IO线相关联的互补本地IO线被停用。在写操作期间，本地IO线上提供另一个数据值，并在互补的本地IO线上提供补充数据值。还公开了其它系统和方法。

3. 发明授权

US07630257B2 Methods and systems for accessing memory 有权
标题翻译：访问内存的方法和系统
公开(公告)号：US07630257B2
公开(公告)日：2009-12-08
申请号：US11543338
申请日：2006-10-04
申请人： Sudhir Kumar Madan , Hugh P. Mcadams , Sung-Wei Lin
发明人： Sudhir Kumar Madan , Hugh P. Mcadams , Sung-Wei Lin
IPC分类号： G11C7/00
CPC分类号： G11C11/22 , G11C2207/005 , G11C2207/2281 , G11C2207/229
摘要： One aspect of the invention relates to a method for accessing a memory device. One embodiment relates to a method for accessing a memory device. In the method during a read operation, one data value is provided on a local IO line while complimentary local IO line that is associated with the local IO line is inactivated. During a write operation, another data value is provided on the local IO line and a complimentary data value is provided on the complimentary local IO line. Other systems and methods are also disclosed.
摘要翻译：本发明的一个方面涉及一种用于访问存储器件的方法。一个实施例涉及访问存储器件的方法。在读操作期间的方法中，在本地IO线上提供一个数据值，而与本地IO线相关联的互补本地IO线被停用。在写操作期间，本地IO线上提供另一个数据值，并在互补的本地IO线上提供补充数据值。还公开了其它系统和方法。

4. 发明授权

US07301795B2 Accelerated low power fatigue testing of FRAM 有权
标题翻译： FRAM加速低功耗疲劳试验
公开(公告)号：US07301795B2
公开(公告)日：2007-11-27
申请号：US11260987
申请日：2005-10-28
申请人： John Y. Fong , Anand Seshadri , Sung-Wei Lin , Sudhir Kumar Madan , Jarrod Eliason
发明人： John Y. Fong , Anand Seshadri , Sung-Wei Lin , Sudhir Kumar Madan , Jarrod Eliason
IPC分类号： G11C11/22
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/5002
摘要： Systems and methods fatigue a ferroelectric memory device. Within a single cycle, a group of selected ferroelectric memory cells is fatigued by reading a first logical value from the cells while also writing a second logical value to the memory cells. The first logical value is temporarily stored into latches of sense amplifiers associated with the selected memory cells in order to decipher logical values. Subsequently, the first logical value is written back to the ferroelectric memory cells and a cycle of the fatigue operation is ended.
摘要翻译：系统和方法使铁电存储器件疲劳。在单个周期内，通过从单元读取第一逻辑值，同时向存储单元写入第二逻辑值，使一组选定的铁电存储单元疲劳。将第一逻辑值临时存储到与所选择的存储器单元相关联的读出放大器的锁存器中，以便解密逻辑值。随后，将第一逻辑值写回到铁电存储单元，并且结束疲劳操作的循环。

5. 发明授权

US07133304B2 Method and apparatus to reduce storage node disturbance in ferroelectric memory 有权
标题翻译：减少铁电存储器节点干扰的方法和装置
公开(公告)号：US07133304B2
公开(公告)日：2006-11-07
申请号：US10805809
申请日：2004-03-22
申请人： Sudhir Kumar Madan , Sung-Wei Lin , Hugh P. McAdams , Anand Seshadri , Jarrod Eliason
发明人： Sudhir Kumar Madan , Sung-Wei Lin , Hugh P. McAdams , Anand Seshadri , Jarrod Eliason
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： Methods and ferroelectric devices are presented, in which pulses are selectively applied to ferroelectric memory cell wordlines to discharge cell storage node disturbances while the cell plateline and the associated bitline are held at substantially the same voltage.
摘要翻译：提出了方法和铁电器件，其中脉冲被选择性地施加到铁电存储器单元字线以放电单元存储节点干扰，同时单元板线和相关联的位线保持在基本上相同的电压。

6. 发明授权

US07349237B2 Plateline driver with RAMP rate control 有权
标题翻译：具有RAMP速率控制的Plateline驱动程序
公开(公告)号：US07349237B2
公开(公告)日：2008-03-25
申请号：US11003707
申请日：2004-12-03
申请人： Sung-Wei Lin , Sudhir K. Madan , John Fong
发明人： Sung-Wei Lin , Sudhir K. Madan , John Fong
IPC分类号： G11C11/00 , G11C5/14
CPC分类号： H03K19/00346 , H03K19/185
摘要： A memory circuit and method to reduce wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and 706) and columns (750, 752). A first conductor (710, 850) is coupled to a plurality of the rows (702, 704, and 706) of memory cells. A first transistor (810) has a current path coupled between a voltage supply terminal (800) and the first conductor (850) and a control terminal coupled to receive a first control signal (PLV). A second transistor (820) has a current path coupled between the voltage supply terminal and the first conductor and a control terminal coupled to receive a second control signal (PLW).
摘要翻译：公开了一种减少字线耦合的存储电路和方法。电路包括排列成行（702,704和706）和列（750,752）的多个存储单元。第一导体（710,850）耦合到存储器单元的多个行（702,704和706）。第一晶体管（810）具有耦合在电压源端子（800）和第一导体（850）之间的电流通路和耦合以接收第一控制信号（PLV）的控制端子。第二晶体管（820）具有耦合在电压供应端和第一导体之间的电流路径，以及耦合以接收第二控制信号（PLW）的控制端。

7. 发明申请

US20060107095A1 Accelerated low power fatigue testing of fram 有权
标题翻译：框架加速低功率疲劳试验
公开(公告)号：US20060107095A1
公开(公告)日：2006-05-18
申请号：US11260987
申请日：2005-10-28
申请人： John Fong , Anand Seshadri , Sung-Wei Lin , Sudhir Madan , Jarrod Eliason
发明人： John Fong , Anand Seshadri , Sung-Wei Lin , Sudhir Madan , Jarrod Eliason
IPC分类号： G06F11/00
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/5002
摘要： Systems and methods fatigue a ferroelectric memory device. Within a single cycle, a group of selected ferroelectric memory cells is fatigued by reading a first logical value from the cells while also writing a second logical value to the memory cells. The first logical value is temporarily stored into latches of sense amplifiers associated with the selected memory cells in order to decipher logical values. Subsequently, the first logical value is written back to the ferroelectric memory cells and a cycle of the fatigue operation is ended.
摘要翻译：系统和方法使铁电存储器件疲劳。在单个周期内，通过从单元读取第一逻辑值，同时向存储单元写入第二逻辑值，使一组选定的铁电存储单元疲劳。将第一逻辑值临时存储到与所选择的存储器单元相关联的读出放大器的锁存器中，以便解密逻辑值。随后，将第一逻辑值写回到铁电存储单元，并且结束疲劳操作的循环。

8. 发明申请

US20070211510A1 Low resistance plate line bus architecture 有权
标题翻译：低电阻板线总线架构
公开(公告)号：US20070211510A1
公开(公告)日：2007-09-13
申请号：US11409628
申请日：2006-04-24
申请人： Sudhir Madan , Sung-Wei Lin , John Fong
发明人： Sudhir Madan , Sung-Wei Lin , John Fong
IPC分类号： G11C11/22 , G11C5/06 , G11C11/42
CPC分类号： G11C11/22 , H01L27/11502
摘要： An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.
摘要翻译：描述了其中板线在字线方向上延伸的FeRAM存储器阵列，其在具有公共板线连接的阵列中提供减小的板线电阻。下板线电阻降低了板线上负尖峰的幅度，以减少FeCap去极化的可能性。多列存储器单元的两条或多条板条沿位线方向互连。一个或多个虚拟存储器单元列的一些或全部平板线也可互连，以减小板线电阻并且最小化阵列的有源单元的位线电容的任何增加。改进的FeRAM阵列提供了降低的数据错误率，特别是在快速的存储周期时间。

9. 发明申请

US20080079471A1 Plateline Driver with Ramp Rate Control 审中-公开
标题翻译：斜坡驱动器，具有斜坡率控制
公开(公告)号：US20080079471A1
公开(公告)日：2008-04-03
申请号：US11937303
申请日：2007-11-08
申请人： Sung-Wei Lin , Sudhir Madan , John Fong
发明人： Sung-Wei Lin , Sudhir Madan , John Fong
IPC分类号： H03K5/01
CPC分类号： H03K19/00346 , H03K19/185
摘要： A memory circuit and method to reduce wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and 706) and columns (750, 752). A first conductor (710, 850 ) is coupled to a plurality of the rows (702, 704, and 706) of memory cells. A first transistor (810) has a current path coupled between a voltage supply terminal (800) and the first conductor (850) and a control terminal coupled to receive a first control signal (PLV). A second transistor (820) has a current path coupled between the voltage supply terminal and the first conductor and a control terminal coupled to receive a second control signal (PLW).
摘要翻译：公开了一种减少字线耦合的存储电路和方法。电路包括排列成行（702,704和706）和列（750,752）的多个存储单元。第一导体（710,850）耦合到存储器单元的多个行（702,704和706）。第一晶体管（810）具有耦合在电压源端子（800）和第一导体（850）之间的电流通路和耦合以接收第一控制信号（PLV）的控制端子。第二晶体管（820）具有耦合在电压供应端和第一导体之间的电流路径，以及耦合以接收第二控制信号（PLW）的控制端。

10. 发明申请

US20050078504A1 Plateline driver with RAMP rate control 有权
标题翻译：具有RAMP速率控制的Plateline驱动程序
公开(公告)号：US20050078504A1
公开(公告)日：2005-04-14
申请号：US11003707
申请日：2004-12-03
申请人： Sung-Wei Lin , Sudhir Madan , John Fong
发明人： Sung-Wei Lin , Sudhir Madan , John Fong
IPC分类号： G11C11/22
CPC分类号： H03K19/00346 , H03K19/185
摘要： A memory circuit and method to reduce wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and 706) and columns (750, 752). A first conductor (710, 850) is coupled to a plurality of the rows (702, 704, and 706) of memory cells. A first transistor (810) has a current path coupled between a voltage supply terminal (800) and the first conductor (850) and a control terminal coupled to receive a first control signal (PLV). A second transistor (820) has a current path coupled between the voltage supply terminal and the first conductor and a control terminal coupled to receive a second control signal (PLW).
摘要翻译：公开了一种减少字线耦合的存储电路和方法。电路包括排列成行（702,704和706）和列（750,752）的多个存储单元。第一导体（710,850）耦合到存储器单元的多个行（702,704和706）。第一晶体管（810）具有耦合在电压源端子（800）和第一导体（850）之间的电流通路和耦合以接收第一控制信号（PLV）的控制端子。第二晶体管（820）具有耦合在电压供应端和第一导体之间的电流路径，以及耦合以接收第二控制信号（PLW）的控制端。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式