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1. 发明授权

US09002915B1 Circuits for shifting bussed data 有权
标题翻译：用于转换总线数据的电路
公开(公告)号：US09002915B1
公开(公告)日：2015-04-07
申请号：US12417048
申请日：2009-04-02
申请人： Steven P. Young , Brian C. Gaide
发明人： Steven P. Young , Brian C. Gaide
IPC分类号： G06F7/00 , G06F15/00 , G06F5/01
CPC分类号： G06F5/015 , H03K19/17736
摘要： A circuit for shifting bussed data includes a first column of shift blocks, a compare block, and a second column of multiplexer blocks. The first column shifts the bussed data by a number of bits specified by first bits of a shift control input. The compare block determines the value of a second bit of the shift control input and creates an output reflecting that value. The second column has a control input coupled to the output of the compare block, shifts the data by one byte when the second bit of the shift control input has a first value, and does not shift the data when the second bit has a second value. The shift, compare, and multiplexer blocks can be substantially similar logic blocks programmable to perform any of these functions, can include N-bit data inputs and outputs, and can operate on the bussed data as an N-bit bus.
摘要翻译：用于移位总线数据的电路包括第一列移位块，比较块和第二列复用器块。第一列将总线数据移位由移位控制输入的第一位指定的位数。比较块确定移位控制输入的第二位的值，并创建反映该值的输出。第二列具有耦合到比较块的输出的控制输入，当移位控制输入的第二位具有第一值时将数据移位一个字节，并且当第二位具有第二值时不移位数据。移位，比较和多路复用器块可以是基本相似的可编程以执行这些功能的逻辑块，可以包括N位数据输入和输出，并且可以作为N位总线对总线数据进行操作。

2. 发明授权

US08058905B1 Clock distribution to facilitate gated clocks 有权
标题翻译：时钟分配方便门控时钟
公开(公告)号：US08058905B1
公开(公告)日：2011-11-15
申请号：US12363722
申请日：2009-01-31
申请人： Matthew H. Klein , Richard W. Swanson , Trevor J. Bauer , Steven P. Young , Andy DeBaets
发明人： Matthew H. Klein , Richard W. Swanson , Trevor J. Bauer , Steven P. Young , Andy DeBaets
IPC分类号： H03K19/00 , H03K3/356
CPC分类号： G06F1/10 , G06F1/3203 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： Circuits and methods for facilitating distribution of gated clocks in a programmable integrated circuit such as a field programmable gate array (FPGA) are described. Dynamic power savings are achieved in a FPGA by providing gated clock driver circuitry at various places in a hierarchical clock distribution network. The gated clock circuitry provides a clock signal gated by an enable signal to clocked elements. Configurable logic blocks (CLBs) comprising the clocked elements and programmable interconnect tiles are disposed in the gate array. Clock signals are distributed to the CLBs via a clock distribution network. Clock enable signals are provided corresponding to some of the clock signals. Clock buffers or drivers are provided within the clock distribution network that drive gated clock signals to CLBs. By disabling certain clocked elements using one or more embodiments of the invention when portions of the FPGA are inactive, dynamic power consumption is reduced.
摘要翻译：描述了便于在诸如现场可编程门阵列（FPGA）的可编程集成电路中分配门控时钟的电路和方法。通过在分层时钟分配网络中的不同位置提供门控时钟驱动器电路，可以在FPGA中实现动态功耗。门控时钟电路通过使能信号为时钟元件提供门控时钟信号。包括时钟元件和可编程互连瓦片的可配置逻辑块（CLB）设置在门阵列中。时钟信号通过时钟分配网络分发给CLB。对应于一些时钟信号提供时钟使能信号。在时钟分配网络中提供时钟缓冲器或驱动器，将门控时钟信号驱动到CLB。通过在FPGA的部分不活动时使用本发明的一个或多个实施例来禁用某些时钟元件，动态功耗降低。

3. 发明授权

US07902863B1 Methods and apparatus for device-specific configuration of a programmable integrated circuit 有权
标题翻译：可编程集成电路器件特定配置的方法和装置
公开(公告)号：US07902863B1
公开(公告)日：2011-03-08
申请号：US12049189
申请日：2008-03-14
申请人： David E. Tetzlaff , Daniel J. Ferris, III , Steven P. Young
发明人： David E. Tetzlaff , Daniel J. Ferris, III , Steven P. Young
IPC分类号： H03K19/173
CPC分类号： H03K19/17748 , G06F17/5054
摘要： Methods and apparatus for configuring a programmable integrated circuit are described. In one example, a configuration stream having first data for programming first locations in a configuration memory and an instruction for referencing circuitry in the programmable integrated circuit is received. Second data is obtained from the circuitry based on the instruction. Second locations in the configuration memory are programmed in response to the second data.
摘要翻译：描述用于配置可编程集成电路的方法和装置。在一个示例中，接收具有用于对配置存储器中的第一位置进行编程的第一数据和用于参考可编程集成电路中的电路的指令的配置流。基于该指令的电路获得第二数据。响应于第二数据对配置存储器中的第二位置进行编程。

4. 发明授权

US07895509B1 Error checking parity and syndrome of a block of data with relocated parity bits 有权
标题翻译：错误检查具有重定位奇偶校验位的数据块的奇偶校验和校验
公开(公告)号：US07895509B1
公开(公告)日：2011-02-22
申请号：US12188935
申请日：2008-08-08
申请人： Warren E. Cory , David P. Schultz , Steven P. Young
发明人： Warren E. Cory , David P. Schultz , Steven P. Young
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： H03M13/27 , H03M13/19 , H03M13/45
摘要： Method and apparatus for error checking information is described. Configuration data includes data bits and parity bits. Notably, parity bits may be relocated for determining a syndrome value. Syndrome bits are determined by computing a partial syndrome value for each word serially transmitted of the configuration data, where the configuration data includes one or more data vectors. Location of each word of the configuration data is identified. It is determined whether a partial syndrome value is an initial partial syndrome value or other partial syndrome value responsive to word location. An initial partial syndrome value is stored, and subsequent partial syndrome values are cumulatively added for each word of a data vector to arrive at a syndrome value for the data vector.
摘要翻译：描述了用于错误检查信息的方法和装置。配置数据包括数据位和奇偶校验位。值得注意的是，可以重新定位奇偶校验位以确定校正子值。通过对配置数据的串行发送的每个字计算部分校正子值来确定综合征位，其中配置数据包括一个或多个数据向量。识别配置数据的每个单词的位置。确定部分综合征值是否是初始部分综合征值或响应于词位置的其他部分综合征值。存储初始部分综合征值，并且随后的部分综合征值被累积地添加到数据向量的每个单词以得到数据向量的校正子值。

5. 发明授权

US07746106B1 Circuits for enabling feedback paths in a self-timed integrated circuit 有权
标题翻译：用于在自定时集成电路中启用反馈路径的电路
公开(公告)号：US07746106B1
公开(公告)日：2010-06-29
申请号：US12417040
申请日：2009-04-02
申请人： Brian C. Gaide , Steven P. Young
发明人： Brian C. Gaide , Steven P. Young
IPC分类号： H03K19/173
CPC分类号： H03K19/1736 , H03K19/17728 , H03K19/17736
摘要： Circuits enabling feedback paths in a self-timed integrated circuit. Each of a plurality of interconnected logic blocks includes a logic circuit having first and second outputs, and means for placing, during an initial cycle, a self-timed first data signal on the second output onto a logic block output, and for placing, during subsequent cycles, a self-timed second data signal on a selected one of the first or second outputs onto the logic block output. Initially, an output token is provided only when valid new data is received on the second output and on a select signal. Subsequently, the output token is provided only when either the first output of the logic circuit is selected, and valid new data is received on the first output and on the select signal; or the second output of the logic circuit is selected, and valid new data is received on the first and second outputs and on the select signal.
摘要翻译：在自定时集成电路中实现反馈路径的电路。多个相互连接的逻辑块中的每一个包括具有第一和第二输出的逻辑电路，以及用于在初始周期期间将第二输出上的自定时第一数据信号放置在逻辑块输出上并用于在随后的周期中，在逻辑块输出上的第一或第二输出中的所选择的一个上的自定时第二数据信号。最初，仅当在第二输出和选择信号上接收到有效的新数据时才提供输出令牌。随后，仅当逻辑电路的第一输出被选择并且在第一输出和选择信号上接收到有效的新数据时才提供输出令牌; 或选择逻辑电路的第二输出，并在第一和第二输出和选择信号上接收有效的新数据。

6. 发明授权

US07617472B1 Regional signal-distribution network for an integrated circuit 有权
标题翻译：集成电路的区域信号分配网络
公开(公告)号：US07617472B1
公开(公告)日：2009-11-10
申请号：US12025637
申请日：2008-02-04
申请人： Jason R. Bergendahl , Ping-Chen Liu , Paul T. Sasaki , Suresh M. Menon , Atul V. Ghia , Steven P. Young , Trevor J. Bauer
发明人： Jason R. Bergendahl , Ping-Chen Liu , Paul T. Sasaki , Suresh M. Menon , Atul V. Ghia , Steven P. Young , Trevor J. Bauer
IPC分类号： G06F17/50 , H03K19/177
CPC分类号： G06F17/5054 , G06F2217/62
摘要： Signal distribution of a regional signal is described. An integrated circuit includes a global signal distribution network, a regional signal distribution network and a regional buffer. The regional buffer has an output coupled at an end of the regional signal distribution network. The regional signal distribution network is coupled to a configurable logic block via an interconnect tile. The regional buffer is coupled to a regional clock capable input/output block. Additionally described is a source synchronous interface for regional signal distribution.
摘要翻译：描述区域信号的信号分布。集成电路包括全球信号分配网络，区域信号分配网络和区域缓冲器。区域缓冲区具有耦合在区域信号分配网络末端的输出。区域信号分配网络通过互连瓦片耦合到可配置的逻辑块。区域缓冲器耦合到具有区域时钟的输入/输出块。另外描述了用于区域信号分配的源同步接口。

7. 发明授权

US07489152B2 Characterizing circuit performance by separating device and interconnect impact on signal delay 有权
标题翻译：通过分离器件和互连对信号延迟的影响来表征电路性能
公开(公告)号：US07489152B2
公开(公告)日：2009-02-10
申请号：US11498371
申请日：2006-08-03
申请人： Xiao-Jie Yuan , Michael J. Hart , Zicheng G. Ling , Steven P. Young
发明人： Xiao-Jie Yuan , Michael J. Hart , Zicheng G. Ling , Steven P. Young
IPC分类号： G01R31/28
CPC分类号： G01R31/2882 , G01R31/318511 , G01R31/318516 , G01R31/3187
摘要： An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.
摘要翻译：集成电路（IC）包括多个嵌入式测试电路，其中都包括耦合到测试负载的环形振荡器。测试负载在环形振荡器中是直接短路，或者是表示IC中互连层之一的互连负载。为每个嵌入式测试电路定义一个模型方程，每个模型方程式将其相关嵌入式测试电路的输出延迟指定为线路前端（FEOL）和线路后端（BEOL）参数的函数。然后，对于各种FEOL和BEOL参数求解模型方程，作为测试电路输出延迟的函数。最后，将测量的输出延迟值替换为这些参数方程，以生成各种FEOL和BEOL参数的实际值，从而允许快速准确地识别任何关注的领域。

8. 发明授权

US07402443B1 Methods of providing families of integrated circuits with similar dies partially disabled using product selection codes 有权
标题翻译：使用产品选择代码为集成电路系列提供类似模具的方法部分禁用
公开(公告)号：US07402443B1
公开(公告)日：2008-07-22
申请号：US11333819
申请日：2006-01-17
申请人： Raymond C. Pang , Trevor J. Bauer , F. Erich Goetting , Bruce E. Talley , Steven P. Young
发明人： Raymond C. Pang , Trevor J. Bauer , F. Erich Goetting , Bruce E. Talley , Steven P. Young
IPC分类号： G01R31/26
CPC分类号： H01L27/11807 , H01L27/0207
摘要： A method of providing a family of integrated circuits (ICs) includes applying a first product selection code (PSC) to a first IC die, applying a second PSC to a second IC die, and providing a third packaged IC die. The first IC die includes first and second portions, both of which are operational based on the first PSC. The second IC die is a duplicate of the first die, but the second portion is rendered non-operational by the second PSC. The third IC die is substantially similar to the first portion of the first die. The second and third packages can be the same and the packaged dies can be interchangeable in a system. When the dies are programmable logic device (PLD) dies, the second and third dies use the same configuration bit stream, which may be smaller than the configuration bit stream for the first IC die.
摘要翻译：提供集成电路（IC）系列的方法包括：将第一产品选择代码（PSC）应用于第一IC芯片，将第二PSC应用于第二IC芯片，以及提供第三封装IC芯片。第一IC芯片包括第一和第二部分，它们都基于第一PSC而可操作。第二IC芯片是第一裸片的副本，但是第二部分由第二PSC不可操作。第三IC管芯基本上类似于第一管芯的第一部分。第二和第三包可以是相同的，并且包装的模具可以在系统中互换。当管芯是可编程逻辑器件（PLD）管芯时，第二和第三管芯使用与第一IC管芯的配置位流相同的配置位流。

9. 发明授权

US07314174B1 Method and system for configuring an integrated circuit 有权
标题翻译：用于配置集成电路的方法和系统
公开(公告)号：US07314174B1
公开(公告)日：2008-01-01
申请号：US10970964
申请日：2004-10-22
申请人： Vasisht Mantra Vadi , David P. Schultz , Steven P. Young , Jennifer Wong
发明人： Vasisht Mantra Vadi , David P. Schultz , Steven P. Young , Jennifer Wong
IPC分类号： G06K7/10 , G06K9/36 , G06K9/80
CPC分类号： H03K19/177
摘要： A system for programming configuration memory cells in an integrated circuit. The system includes: a set of data registers, wherein a member of the set has a temporary storage for a fixed number of configuration bits; and a plurality of rows, each row has a plurality of columns, wherein configuration memory cells in a selected column and in a selected row are programmed using the fixed number of configuration bits.
摘要翻译：一种用于在集成电路中编程配置存储单元的系统。该系统包括：一组数据寄存器，其中该组的成员具有固定数量的配置位的临时存储; 和多行，每行具有多个列，其中使用固定数量的配置位对所选列和所选行中的配置存储单元进行编程。

10. 发明授权

US07312631B1 Structures and methods for avoiding hold time violations in a programmable logic device 有权
标题翻译：用于避免可编程逻辑器件中的保持时间违规的结构和方法
公开(公告)号：US07312631B1
公开(公告)日：2007-12-25
申请号：US11264405
申请日：2005-11-01
申请人： Trevor J. Bauer , Ramakrishna K. Tanikella , Steven P. Young
发明人： Trevor J. Bauer , Ramakrishna K. Tanikella , Steven P. Young
IPC分类号： H03K19/177 , H03K19/173 , H03K19/00
CPC分类号： H03K19/17736 , H03K19/00323
摘要： Structures and methods of avoiding hold time violations in a design implemented in a PLD. In a programmable device, the delay of a signal path varies, e.g., depending on the separation between the source and destination of the signal. An optional delay element is provided between a programmable interconnect structure and a destination logic element having a clock skew relative to the source. The optional delay element is programmed by the implementation software to introduce a delay on the signal path when necessary to meet the hold time requirements for the destination logic element. The optional delay is designed to be large enough to overcome hold-time violations even for the largest possible clock skew and the smallest possible signal delay. When no hold time violation occurs, the optional delay element is configured to bypass the additional delay, to avoid imposing a large setup requirement on the signal.
摘要翻译：在PLD中实现的设计中避免持续时间违规的结构和方法。在可编程设备中，信号路径的延迟例如取决于信号的源和目的地之间的间隔而变化。在可编程互连结构和具有相对于源的时钟偏移的目的地逻辑元件之间提供可选的延迟元件。可选延迟元件由实现软件编程，以在必要时在信号路径上引入延迟以满足目的地逻辑元件的保持时间要求。可选延迟被设计为足够大，以克服即使对于最大可能的时钟偏移和尽可能小的信号延迟的保持时间违规。当没有发生保持时间违规时，可选的延迟元件被配置为绕过附加延迟，以避免对信号施加大的设置要求。

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