专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07383376B2 Apparatus and methods for storing data in a magnetic random access memory (MRAM) 有权
标题翻译：用于将数据存储在磁随机存取存储器（MRAM）中的装置和方法
公开(公告)号：US07383376B2
公开(公告)日：2008-06-03
申请号：US11535899
申请日：2006-09-27
申请人： Richard W. Swanson
发明人： Richard W. Swanson
IPC分类号： H01L27/06 , G06F12/00
CPC分类号： G11C11/16
摘要： An apparatus and methods store data in a magnetic random access memory (MRAM) in a fast and efficient manner. Embodiments advantageously decrease the number of clock cycles required to store data by eliminating at least one wait state in a transition from a read state to a write state. Embodiments advantageously enhance the throughput of the MRAM and a related digital circuit, such as a computer system, which advantageously enhances the operating speed of the digital circuit.
摘要翻译：一种装置和方法以快速有效的方式将数据存储在磁随机存取存储器（MRAM）中。实施例有利地通过在从读取状态到写入状态的转变中消除至少一个等待状态来减少存储数据所需的时钟周期数。实施例有利地增强了MRAM和相关数字电路（例如计算机系统）的吞吐量，其有利地增强了数字电路的操作速度。

2. 发明授权

US06968482B2 Memory redundancy with programmable non-volatile control 有权
公开(公告)号：US06968482B2
公开(公告)日：2005-11-22
申请号：US11067355
申请日：2005-02-25
申请人： Theodore Zhu , Gary Kirchner , Richard W. Swanson , Yong Lu
发明人： Theodore Zhu , Gary Kirchner , Richard W. Swanson , Yong Lu
IPC分类号： G11C29/00
CPC分类号： G11C29/808 , G11C29/846
摘要： A redundancy scheme for a memory is disclosed that is programmable both before and after the memory device is packaged and/or installed in a system. This is preferably accomplished by using programmable non-volatile memory elements to control the replacement circuitry. Because the programmable memory elements are non-volatile, the desired replacement configuration is not lost during shipping, or if power is lost in a system. By allowing post-packaging replacement of defective memory elements, the overall yield of the device may be improved. By allowing post system installation replacement of defective memory elements, the reliability of many systems may be improved. In addition, the disclosed redundancy scheme allows two or more defective memory elements from different rows or columns to be replaced with memory elements from a single redundant low or column. This provides added flexibility during the replacement process.

3. 发明授权

US07389451B2 Memory redundancy with programmable control 有权
标题翻译：内存冗余与可编程控制
公开(公告)号：US07389451B2
公开(公告)日：2008-06-17
申请号：US11067356
申请日：2005-02-25
申请人： Theodore Zhu , Gary Kirchner , Richard W. Swanson , Yong Lu
发明人： Theodore Zhu , Gary Kirchner , Richard W. Swanson , Yong Lu
IPC分类号： G01C29/00
CPC分类号： G11C29/808 , G11C29/846
摘要： A redundancy scheme for a memory is disclosed that is programmable both before and after the memory device is packaged and/or installed in a system. This is preferably accomplished by using programmable non-volatile memory elements to control the replacement circuitry. Because the programmable memory elements are non-volatile, the desired replacement configuration is not lost during shipping, or if power is lost in a system. By allowing post-packaging replacement of defective memory elements, the overall yield of the device may be improved. By allowing post system installation replacement of defective memory elements, the reliability of many systems may be improved. In addition, the disclosed redundancy scheme allows two or more defective memory elements from different rows or columns to be replaced with memory elements from a single redundant low or column. This provides added flexibility during the replacement process.
摘要翻译：公开了一种用于存储器的冗余方案，其在存储器件被封装和/或安装在系统中之前和之后是可编程的。这优选地通过使用可编程非易失性存储器元件来控制替换电路来实现。由于可编程存储器元件是非易失性的，所以在运输过程中或者系统中的电源丢失时，所需的更换配置不会丢失。通过允许更换缺陷存储元件的后期封装，可以提高器件的整体产量。通过允许后置系统安装更换有缺陷的存储器元件，可以提高许多系统的可靠性。此外，所公开的冗余方案允许来自不同行或列的两个或更多个有缺陷的存储器元件被来自单个冗余行或列的存储器元件替换。这在更换过程中提供了更多的灵活性。

4. 发明授权

US06724654B1 Pulsed write techniques for magneto-resistive memories 有权
标题翻译：用于磁阻存储器的脉冲写入技术
公开(公告)号：US06724654B1
公开(公告)日：2004-04-20
申请号：US10366292
申请日：2003-02-13
申请人： Richard W. Swanson , William J. Johnson , Theodore Zhu , Anthony S. Arrott
发明人： Richard W. Swanson , William J. Johnson , Theodore Zhu , Anthony S. Arrott
IPC分类号： G11C1100
CPC分类号： G11C8/14 , G11C11/15
摘要： A magneto-resistive memory that has a shared word line and sense line is disclosed. By providing the shared word line and sense line, the number of relatively large drivers required to drive the word line and sense line currents can be reduced. This reduces the peripheral overhead of the memory, and may increase the overall density and reduce the overall power of the memory.
摘要翻译：公开了具有共享字线和感测线的磁阻存储器。通过提供共享字线和感测线，可以减少驱动字线和感测线电流所需的较大驱动器的数量。这减少了存储器的周边开销，并且可以增加总体密度并降低存储器的整体功率。

5. 发明授权

US08270235B2 Dynamic detection of a strobe signal within an integrated circuit 有权
标题翻译：集成电路内的选通信号的动态检测
公开(公告)号：US08270235B2
公开(公告)日：2012-09-18
申请号：US12794605
申请日：2010-06-04
申请人： Richard W. Swanson , Tao Pi
发明人： Richard W. Swanson , Tao Pi
IPC分类号： G11C7/00
CPC分类号： G06F13/1689
摘要： A method of processing a strobe signal can include oversampling a strobe signal received from a source synchronous device and determining an amount of time between sending a read request to the source synchronous device and detecting a first pulse of the strobe signal according to the oversampling. The method also can include squelching the strobe signal for the amount of time responsive to at least one subsequent read request.
摘要翻译：处理选通信号的方法可以包括对从源同步装置接收的选通信号进行过采样，并且确定发送对源同步装置的读请求之间的时间量，并根据过采样检测选通信号的第一脉冲。该方法还可以包括响应于至少一个后续读取请求来对选通信号进行静噪的时间量。

6. 发明授权

US08058905B1 Clock distribution to facilitate gated clocks 有权
标题翻译：时钟分配方便门控时钟
公开(公告)号：US08058905B1
公开(公告)日：2011-11-15
申请号：US12363722
申请日：2009-01-31
申请人： Matthew H. Klein , Richard W. Swanson , Trevor J. Bauer , Steven P. Young , Andy DeBaets
发明人： Matthew H. Klein , Richard W. Swanson , Trevor J. Bauer , Steven P. Young , Andy DeBaets
IPC分类号： H03K19/00 , H03K3/356
CPC分类号： G06F1/10 , G06F1/3203 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： Circuits and methods for facilitating distribution of gated clocks in a programmable integrated circuit such as a field programmable gate array (FPGA) are described. Dynamic power savings are achieved in a FPGA by providing gated clock driver circuitry at various places in a hierarchical clock distribution network. The gated clock circuitry provides a clock signal gated by an enable signal to clocked elements. Configurable logic blocks (CLBs) comprising the clocked elements and programmable interconnect tiles are disposed in the gate array. Clock signals are distributed to the CLBs via a clock distribution network. Clock enable signals are provided corresponding to some of the clock signals. Clock buffers or drivers are provided within the clock distribution network that drive gated clock signals to CLBs. By disabling certain clocked elements using one or more embodiments of the invention when portions of the FPGA are inactive, dynamic power consumption is reduced.
摘要翻译：描述了便于在诸如现场可编程门阵列（FPGA）的可编程集成电路中分配门控时钟的电路和方法。通过在分层时钟分配网络中的不同位置提供门控时钟驱动器电路，可以在FPGA中实现动态功耗。门控时钟电路通过使能信号为时钟元件提供门控时钟信号。包括时钟元件和可编程互连瓦片的可配置逻辑块（CLB）设置在门阵列中。时钟信号通过时钟分配网络分发给CLB。对应于一些时钟信号提供时钟使能信号。在时钟分配网络中提供时钟缓冲器或驱动器，将门控时钟信号驱动到CLB。通过在FPGA的部分不活动时使用本发明的一个或多个实施例来禁用某些时钟元件，动态功耗降低。

7. 发明授权

US07328379B2 Look-up table for use with redundant memory 有权
标题翻译：查找表用于冗余内存
公开(公告)号：US07328379B2
公开(公告)日：2008-02-05
申请号：US11067326
申请日：2005-02-25
申请人： Theodore Zhu , Gary Kirchner , Richard W. Swanson , Yong Lu
发明人： Theodore Zhu , Gary Kirchner , Richard W. Swanson , Yong Lu
IPC分类号： G11C29/00
CPC分类号： G11C29/808 , G11C29/846
摘要： A redundancy scheme for a memory is disclosed that is programmable both before and after the memory device is packaged and/or installed in a system. This is preferably accomplished by using programmable non-volatile memory elements to control the replacement circuitry. Because the programmable memory elements are non-volatile, the desired replacement configuration is not lost during shipping, or if power is lost in a system. By allowing post-packaging replacement of defective memory elements, the overall yield of the device may be improved. By allowing post system installation replacement of defective memory elements, the reliability of many systems may be improved. In addition, the disclosed redundancy scheme allows two or more defective memory elements from different rows or columns to be replaced with memory elements from a single redundant low or column. This provides added flexibility during the replacement process.
摘要翻译：公开了一种用于存储器的冗余方案，其在存储器件被封装和/或安装在系统中之前和之后是可编程的。这优选地通过使用可编程非易失性存储器元件来控制替换电路来实现。由于可编程存储器元件是非易失性的，所以在运输过程中或者系统中的电源丢失时，所需的更换配置不会丢失。通过允许更换缺陷存储元件的后期封装，可以提高器件的整体产量。通过允许后置系统安装更换有缺陷的存储器元件，可以提高许多系统的可靠性。此外，所公开的冗余方案允许来自不同行或列的两个或更多个有缺陷的存储器元件被来自单个冗余行或列的存储器元件替换。这在更换过程中提供了更多的灵活性。

8. 发明授权

US06671834B1 Memory redundancy with programmable non-volatile control 有权
标题翻译：内存冗余与可编程非易失性控制
公开(公告)号：US06671834B1
公开(公告)日：2003-12-30
申请号：US09618492
申请日：2000-07-18
申请人： Theodore Zhu , Gary Kirchner , Richard W. Swanson , Yong Lu
发明人： Theodore Zhu , Gary Kirchner , Richard W. Swanson , Yong Lu
IPC分类号： G11C2900
CPC分类号： G11C29/808 , G11C29/846
摘要： A redundancy scheme for a memory is disclosed that is programmable both before and after the memory device is packaged and/or installed in a system. This is preferably accomplished by using programmable non-volatile memory elements to control the replacement circuitry. Because the programmable memory elements are non-volatile, the desired replacement configuration is not lost during shipping, or if power is lost in a system. By allowing post-packaging replacement of defective memory elements, the overall yield of the device may be improved. By allowing post system installation replacement of defective memory elements, the reliability of many systems may be improved. In addition, the disclosed redundancy scheme allows two or more defective memory elements from different rows or columns to be replaced with memory elements from a single redundant low or column. This provides added flexibility during the replacement process.
摘要翻译：公开了一种用于存储器的冗余方案，其在存储器件被封装和/或安装在系统中之前和之后是可编程的。这优选地通过使用可编程非易失性存储器元件来控制替换电路来实现。由于可编程存储器元件是非易失性的，所以在运输过程中，或者系统中的电源丢失时，所需的更换配置不会丢失。通过允许更换缺陷存储元件的后期封装，可以提高器件的整体产量。通过允许后置系统安装更换有缺陷的存储器元件，可以提高许多系统的可靠性。此外，所公开的冗余方案允许来自不同行或列的两个或更多个有缺陷的存储器元件被来自单个冗余低或列的存储器元件替换。这在更换过程中提供了更多的灵活性。

9. 发明授权

US06538918B2 Pulsed write techniques for magneto-resistive memories 有权
公开(公告)号：US06538918B2
公开(公告)日：2003-03-25
申请号：US10174214
申请日：2002-06-17
申请人： Richard W. Swanson , William J. Johnson , Theodore Zhu
发明人： Richard W. Swanson , William J. Johnson , Theodore Zhu
IPC分类号： G11C1100
CPC分类号： G11C11/15 , G11C8/14
摘要： A magneto-resistive memory that has a shared word line and sense line is disclosed. By providing the shared word line and sense line, the number of relatively large drivers required to drive the word line and sense line currents can be reduced. This reduces the peripheral overhead of the memory, and may increase the overall density and reduce the overall power of the memory.

10. 发明申请

US20110299347A1 DYNAMIC DETECTION OF A STROBE SIGNAL WITHIN AN INTEGRATED CIRCUIT 有权
标题翻译：在集成电路中的动态信号的动态检测
公开(公告)号：US20110299347A1
公开(公告)日：2011-12-08
申请号：US12794605
申请日：2010-06-04
申请人： Richard W. Swanson , Tao Pi
发明人： Richard W. Swanson , Tao Pi
IPC分类号： G11C7/00
CPC分类号： G06F13/1689
摘要： A method of processing a strobe signal can include oversampling a strobe signal received from a source synchronous device and determining an amount of time between sending a read request to the source synchronous device and detecting a first pulse of the strobe signal according to the oversampling. The method also can include squelching the strobe signal for the amount of time responsive to at least one subsequent read request.
摘要翻译：处理选通信号的方法可以包括对从源同步装置接收的选通信号进行过采样，并且确定发送对源同步装置的读请求之间的时间量，并根据过采样检测选通信号的第一脉冲。该方法还可以包括响应于至少一个后续读取请求来对选通信号进行静噪的时间量。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式