专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07314174B1 Method and system for configuring an integrated circuit 有权
标题翻译：用于配置集成电路的方法和系统
公开(公告)号：US07314174B1
公开(公告)日：2008-01-01
申请号：US10970964
申请日：2004-10-22
申请人： Vasisht Mantra Vadi , David P. Schultz , Steven P. Young , Jennifer Wong
发明人： Vasisht Mantra Vadi , David P. Schultz , Steven P. Young , Jennifer Wong
IPC分类号： G06K7/10 , G06K9/36 , G06K9/80
CPC分类号： H03K19/177
摘要： A system for programming configuration memory cells in an integrated circuit. The system includes: a set of data registers, wherein a member of the set has a temporary storage for a fixed number of configuration bits; and a plurality of rows, each row has a plurality of columns, wherein configuration memory cells in a selected column and in a selected row are programmed using the fixed number of configuration bits.
摘要翻译：一种用于在集成电路中编程配置存储单元的系统。该系统包括：一组数据寄存器，其中该组的成员具有固定数量的配置位的临时存储; 和多行，每行具有多个列，其中使用固定数量的配置位对所选列和所选行中的配置存储单元进行编程。

2. 发明授权

US07142442B1 Segmented dataline scheme in a memory with enhanced full fault coverage memory cell testability 有权
标题翻译：具有增强的全故障覆盖存储器单元可测性的存储器中的分段数据线方案
公开(公告)号：US07142442B1
公开(公告)日：2006-11-28
申请号：US10796750
申请日：2004-03-08
申请人： Vasisht Mantra Vadi , David P. Schultz , Steven P. Young , Jennifer Wong
发明人： Vasisht Mantra Vadi , David P. Schultz , Steven P. Young , Jennifer Wong
IPC分类号： G11C5/06 , G11C8/00 , G11C7/00
CPC分类号： G11C29/50 , G11C7/12 , G11C11/41 , G11C11/419 , G11C2029/1204
摘要： A memory includes a plurality of row segments, with each row segment having a number of memory cells coupled to a corresponding dataline segment pair. Dataline driver circuits are provided between row segments to buffer signals on adjacent dataline segments. A control circuit is coupled to at least one row segment, and provides control signals to the at least one row segment and to the dataline driver circuits.
摘要翻译：存储器包括多个行段，其中每个行段具有耦合到对应的数据段段对的多个存储器单元。数据线驱动器电路提供在行段之间以缓冲相邻数据段上的信号。控制电路耦合到至少一个行段，并且向至少一个行段和数据线驱动器电路提供控制信号。

3. 发明授权

US07286382B1 Segmented dataline scheme in a memory with enhanced full fault coverage memory cell testability 有权
标题翻译：具有增强的全故障覆盖存储器单元可测性的存储器中的分段数据线方案
公开(公告)号：US07286382B1
公开(公告)日：2007-10-23
申请号：US11590333
申请日：2006-10-31
申请人： Vasisht Mantra Vadi , David P. Schultz , Steven P. Young , Jennifer Wong
发明人： Vasisht Mantra Vadi , David P. Schultz , Steven P. Young , Jennifer Wong
IPC分类号： G11C15/00 , G11C11/00
CPC分类号： G11C29/50 , G11C7/12 , G11C11/41 , G11C11/419 , G11C2029/1204
摘要： A memory includes a plurality of row segments, with each row segment having a number of memory cells coupled to a corresponding dataline segment pair. Dataline driver circuits are provided between row segments to buffer signals on adjacent dataline segments. A control circuit is coupled to at least one row segment, and provides control signals to the at least one row segment and to the dataline driver circuits.
摘要翻译：存储器包括多个行段，其中每个行段具有耦合到对应的数据段段对的多个存储器单元。数据线驱动器电路提供在行段之间以缓冲相邻数据段上的信号。控制电路耦合到至少一个行段，并且向至少一个行段和数据线驱动器电路提供控制信号。

4. 发明授权

US07071756B1 Clock multiplexing system 有权
标题翻译：时钟复用系统
公开(公告)号：US07071756B1
公开(公告)日：2006-07-04
申请号：US10837329
申请日：2004-04-30
申请人： Vasisht Mantra Vadi , Steven P. Young
发明人： Vasisht Mantra Vadi , Steven P. Young
IPC分类号： G06F1/04 , H03K3/00
CPC分类号： G06F1/04 , H03K17/005 , H03K17/693
摘要： A clock control circuit in an integrated circuit for providing a differential clock signal to a differential clock tree. The clock control circuit includes: first differential multiplexers configured to select first outputs from the input clock signals; second differential multiplexers coupled to the first differential multiplexers and configured to select second outputs from the first outputs; loop back signal lines configured to feed back the second outputs to at least part of the input clock signals of the first differential multiplexers; and differential signal lines of the differential clock tree coupled to the second outputs.
摘要翻译：用于向差分时钟树提供差分时钟信号的集成电路中的时钟控制电路。时钟控制电路包括：第一差分复用器，被配置为从输入时钟信号中选择第一输出; 第二差分多路复用器，耦合到所述第一差分多路复用器，并且被配置为从所述第一输出中选择第二输出; 配置为将所述第二输出反馈到所述第一差分多路复用器的输入时钟信号的至少一部分的环回信号线; 以及差分时钟树的差分信号线耦合到第二输出。

5. 发明授权

US07759973B1 Integrated circuit having embedded differential clock tree 有权
标题翻译：集成电路具有嵌入式差分时钟树
公开(公告)号：US07759973B1
公开(公告)日：2010-07-20
申请号：US12174502
申请日：2008-07-16
申请人： Vasisht Mantra Vadi , Steven P. Young , Atul V. Ghia , Adebabay M. Bekele , Suresh M. Menon
发明人： Vasisht Mantra Vadi , Steven P. Young , Atul V. Ghia , Adebabay M. Bekele , Suresh M. Menon
IPC分类号： H03K19/177
CPC分类号： G06F1/10 , H03K5/15013 , H03K19/1774 , H03K19/17784 , H03K19/17796
摘要： A clock distribution network having: a backbone clock signal line configured to provide a differential clock signal; multiple branches coupled to the backbone clock signal line for distributing the differential clock signal to multiple programmable function elements; a first leaf node coupled to a first branch, where the first leaf node is configured to provide the differential clock signal to a first programmable function element; and a second leaf node coupled to a second branch, where the second leaf node is configured to provide a single ended clock signal derived from the differential clock signal to a second programmable function element.
摘要翻译：一种时钟分配网络，具有：骨干时钟信号线，被配置为提供差分时钟信号; 多个分支耦合到主干时钟信号线，用于将差分时钟信号分配给多个可编程功能元件; 耦合到第一分支的第一叶节点，其中所述第一叶节点被配置为将所述差分时钟信号提供给第一可编程功能元件; 以及耦合到第二分支的第二叶节点，其中所述第二叶节点被配置为将从所述差分时钟信号导出的单端时钟信号提供给第二可编程功能元件。

6. 发明授权

US07414430B2 Programmable logic device having an embedded differential clock tree 有权
标题翻译：具有嵌入式差分时钟树的可编程逻辑器件
公开(公告)号：US07414430B2
公开(公告)日：2008-08-19
申请号：US11511647
申请日：2006-08-29
申请人： Vasisht Mantra Vadi , Steven P. Young , Atul V. Ghia , Adebabay M. Bekele , Suresh M. Menon
发明人： Vasisht Mantra Vadi , Steven P. Young , Atul V. Ghia , Adebabay M. Bekele , Suresh M. Menon
IPC分类号： H03K19/177
CPC分类号： G06F1/10 , H03K5/15013 , H03K19/1774 , H03K19/17784 , H03K19/17796
摘要： A clock distribution network having: a backbone clock signal line configured to provide a differential clock signal; multiple branches coupled to the backbone clock signal line for distributing the differential clock signal to multiple programmable function elements; a first leaf node coupled to a first branch, where the first leaf node is configured to provide the differential clock signal to a first programmable function element; and a second leaf node coupled to a second branch, where the second leaf node is configured to provide a single ended clock signal derived from the differential clock signal to a second programmable function element.
摘要翻译：一种时钟分配网络，具有：骨干时钟信号线，被配置为提供差分时钟信号; 多个分支耦合到主干时钟信号线，用于将差分时钟信号分配给多个可编程功能元件; 耦合到第一分支的第一叶节点，其中所述第一叶节点被配置为将所述差分时钟信号提供给第一可编程功能元件; 以及耦合到第二分支的第二叶节点，其中所述第二叶节点被配置为将从所述差分时钟信号导出的单端时钟信号提供给第二可编程功能元件。

7. 发明授权

US07518401B2 Differential clock tree in an integrated circuit 有权
标题翻译：差分时钟树在集成电路中
公开(公告)号：US07518401B2
公开(公告)日：2009-04-14
申请号：US11511973
申请日：2006-08-29
申请人： Vasisht Mantra Vadi , Steven P. Young , Atul V. Ghia , Adebabay M. Bekele , Suresh M. Menon
发明人： Vasisht Mantra Vadi , Steven P. Young , Atul V. Ghia , Adebabay M. Bekele , Suresh M. Menon
IPC分类号： H01L25/00 , H03K19/177 , H03K19/00
CPC分类号： G06F1/10 , H03K5/2481
摘要： A clock distribution network having: a main trunk configured to provide a differential clock signal; a plurality of branches coupled to the main trunk for distributing the differential clock signal to a plurality of circuit elements on the integrated circuit; and a plurality of switches coupling the main trunk to the plurality of branches.
摘要翻译：一种时钟分配网络，具有：主干线，其被配置为提供差分时钟信号; 耦合到所述主干线的多个分支，用于将所述差分时钟信号分配给所述集成电路上的多个电路元件; 以及将主干线连接到多个分支的多个开关。

8. 发明授权

US07372299B2 Differential clock tree in an integrated circuit 有权
标题翻译：差分时钟树在集成电路中
公开(公告)号：US07372299B2
公开(公告)日：2008-05-13
申请号：US11511779
申请日：2006-08-29
申请人： Vasisht Mantra Vadi , Steven P. Young , Atul V. Ghia , Adebabay M. Bekele , Suresh M. Menon
发明人： Vasisht Mantra Vadi , Steven P. Young , Atul V. Ghia , Adebabay M. Bekele , Suresh M. Menon
IPC分类号： H03K19/177
CPC分类号： G06F1/10 , H03K5/2481
摘要： A clock distribution network having: a main trunk configured to provide a differential clock signal; a plurality of branches coupled to the main trunk for distributing the differential clock signal to a plurality of circuit elements on the integrated circuit; and a plurality of switches coupling the main trunk to the plurality of branches.
摘要翻译：一种时钟分配网络，具有：主干线，被配置为提供差分时钟信号; 耦合到所述主干线的多个分支，用于将所述差分时钟信号分配给所述集成电路上的多个电路元件; 以及将主干线连接到多个分支的多个开关。

9. 发明授权

US07129765B2 Differential clock tree in an integrated circuit 有权
公开(公告)号：US07129765B2
公开(公告)日：2006-10-31
申请号：US10836722
申请日：2004-04-30
申请人： Vasisht Mantra Vadi , Steven P. Young , Atul V. Ghia , Adebabay M. Bekele , Suresh M. Menon
发明人： Vasisht Mantra Vadi , Steven P. Young , Atul V. Ghia , Adebabay M. Bekele , Suresh M. Menon
IPC分类号： G06F1/04 , H03K3/00
CPC分类号： G06F1/10 , H03K5/2481
摘要： A clock distribution network having: a main trunk configured to provide a differential clock signal; a plurality of branches coupled to the main trunk for distributing the differential clock signal to a plurality of circuit elements on the integrated circuit; and a plurality of switches coupling the main trunk to the plurality of branches.

10. 发明授权

US07126406B2 Programmable logic device having an embedded differential clock tree 有权
标题翻译：具有嵌入式差分时钟树的可编程逻辑器件
公开(公告)号：US07126406B2
公开(公告)日：2006-10-24
申请号：US10837009
申请日：2004-04-30
申请人： Vasisht Mantra Vadi , Steven P. Young , Atul V. Ghia , Adebabay M. Bekele , Suresh M. Menon
发明人： Vasisht Mantra Vadi , Steven P. Young , Atul V. Ghia , Adebabay M. Bekele , Suresh M. Menon
IPC分类号： G06F1/04 , H03K3/00
CPC分类号： G06F1/10 , H03K5/15013 , H03K19/1774 , H03K19/17784 , H03K19/17796
摘要： A clock distribution network having: a backbone clock signal line configured to provide a differential clock signal; multiple branches coupled to the backbone clock signal line for distributing the differential clock signal to multiple programmable function elements; a first leaf node coupled to a first branch, where the first leaf node is configured to provide the differential clock signal to a first programmable function element; and a second leaf node coupled to a second branch, where the second leaf node is configured to provide a single ended clock signal derived from the differential clock signal to a second programmable function element.
摘要翻译：一种时钟分配网络，具有：骨干时钟信号线，被配置为提供差分时钟信号; 多个分支耦合到主干时钟信号线，用于将差分时钟信号分配给多个可编程功能元件; 耦合到第一分支的第一叶节点，其中所述第一叶节点被配置为将所述差分时钟信号提供给第一可编程功能元件; 以及耦合到第二分支的第二叶节点，其中所述第二叶节点被配置为将从所述差分时钟信号导出的单端时钟信号提供给第二可编程功能元件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式