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1. 发明授权

US5293342A Wordline driver circuit having an automatic precharge circuit 失效
标题翻译：字线驱动电路具有自动预充电电路
公开(公告)号：US5293342A
公开(公告)日：1994-03-08
申请号：US993929
申请日：1992-12-17
申请人： Stephen L. Casper , Adrian Ong , Paul S. Zagar
发明人： Stephen L. Casper , Adrian Ong , Paul S. Zagar
IPC分类号： G11C8/08 , G11C11/408 , G11C7/00
CPC分类号： G11C8/08 , G11C11/4085
摘要： The invention is an automatic precharge circuit featuring precharge devices each of which is interposed between a high voltage node, connectable to a supply potential, and a serial node. The precharge devices are gated automatically by a primary predecode signal of a decode portion of the row decoder. Power is conserved since the serial nodes are passively pulled to the supply potential through the precharge devices. The invention increases speed and provides error free wordline selection.
摘要翻译：本发明是一种自动预充电电路，其特征在于预充电装置各自插入在可连接到电源电位的高压节点和串联节点之间。预充电装置由行解码器的解码部分的主要预解码信号自动选通。功率节省，因为串行节点被动地通过预充电器件拉到电源电位。本发明提高了速度并提供了无错误的字线选择。

2. 再颁专利

USRE35750E Wordline driver circuit having an automatic precharge circuit 失效
标题翻译：字线驱动电路具有自动预充电电路
公开(公告)号：USRE35750E
公开(公告)日：1998-03-24
申请号：US611618
申请日：1996-03-08
申请人： Stephen L. Casper , Adrian Ong , Paul S. Zagar
发明人： Stephen L. Casper , Adrian Ong , Paul S. Zagar
IPC分类号： G11C8/08 , G11C11/408 , G11C7/00
CPC分类号： G11C8/08 , G11C11/4085
摘要： The invention is an automatic precharge circuit featuring precharge devices each of which is interposed between a high voltage node, connectable to a supply potential, and a serial node. The precharge devices are gated automatically by a primary predecode signal of a decode portion of the row decoder. Power is conserved since the serial nodes are passively pulled to the supply potential through the precharge devices. The invention increases speed and provides error free wordline selection.
摘要翻译：本发明是一种自动预充电电路，其特征在于预充电装置各自插入在可连接到电源电位的高压节点和串联节点之间。预充电装置由行解码器的解码部分的主要预解码信号自动选通。功率节省，因为串行节点被动地通过预充电器件拉到电源电位。本发明提高了速度并提供了无错误的字线选择。

3. 发明授权

US5311481A Wordline driver circuit having a directly gated pull-down device 失效
标题翻译：字线驱动电路具有直接门控下拉装置
公开(公告)号：US5311481A
公开(公告)日：1994-05-10
申请号：US993934
申请日：1992-12-17
申请人： Stephen L. Casper , Adrian Ong , Paul S. Zagar
发明人： Stephen L. Casper , Adrian Ong , Paul S. Zagar
IPC分类号： G11C8/00 , G11C8/08
CPC分类号： G11C8/08
摘要： The invention is a circuit and method for quickly driving non-selected wordlines to correct potentials. The invention drives the non-selected wordlines to low potentials through a driving device directly gated by a primary select predecode signal generated by decode circuitry. The driving device is electrically interposed between the wordline and a reference node. The invention provides low power operation, and provides reliable wordline selection for circuits having supply potentials less than 5 volts.
摘要翻译：本发明是用于快速驱动未选择的字线以纠正电位的电路和方法。本发明通过由解码电路产生的初级选择预解码信号直接选通的驱动装置将未选择的字线驱动到低电位。驱动装置电插入字线和参考节点之间。本发明提供低功率操作，并且为电源电压低于5伏的电路提供可靠的字线选择。

4. 发明授权

US5552739A Integrated circuit power supply having piecewise linearity 失效
标题翻译：具有分段线性的集成电路电源
公开(公告)号：US5552739A
公开(公告)日：1996-09-03
申请号：US559414
申请日：1995-11-15
申请人： Brent Keeth , Paul S. Zagar , Brian M. Shirley , Stephen L. Casper
发明人： Brent Keeth , Paul S. Zagar , Brian M. Shirley , Stephen L. Casper
IPC分类号： G05F1/46 , G05F1/10
CPC分类号： G05F1/465
摘要： A power supply for an integrated circuit has a piecewise linear operating characteristic for improved integrated circuit testing and screening. In an integrated circuit that receives an externally applied power signal, designated V.sub.CCX, and includes a power supply for generating an internal operating voltage, designated V.sub.CCR, an on-chip power supply circuit provides V.sub.CCR as a piecewise linear function of V.sub.CCX. In a first segment of such a function, V.sub.CCR approximates V.sub.CCX for efficient low voltage operations. In a second segment, used for normal operations of the integrated circuit, V.sub.CCR rises gradually with V.sub.CCX so that test results at the edges of the segment can be guaranteed with a margin for measurement tolerance, process variation, and derating. In a third segment, V.sub.CCR follows below V.sub.CCX at a predetermined constant offset. Transitions between segments are smooth due to nonlinear devices used in the power supply circuitry. When used in a dynamic random access memory integrated circuit, operation in the first segment provides data retention at low power consumption. Operation in the second segment supports speed grading individual devices with a margin for properly stating memory performance specifications. Operation in the third segment supports screening at elevated temperatures for identifying weak and defective memory devices.
摘要翻译：集成电路的电源具有分段线性工作特性，用于改进的集成电路测试和屏蔽。接收外部施加的电源信号（指定为VCCX）的集成电路中，包括用于产生内部工作电压的电源（指定为VCCR），片上电源电路提供VCCR作为VCCX的分段线性功能。在这种功能的第一段中，VCCR逼近VCCX以实现有效的低电压操作。在用于集成电路的正常操作的第二段中，VCCR随着VCCX逐渐上升，从而可以保证测量公差，工艺变化和降额的边缘上的测试结果。在第三部分中，VCCR在预定的常数偏移下遵循VCCX以下。由于电源电路中使用的非线性器件，片段之间的转换是平滑的。当在动态随机存取存储器集成电路中使用时，第一段中的操作以低功耗提供数据保持。第二部分中的操作支持对具有裕量的各个设备进行速度分级，以正确说明内存性能规格。第三部分的操作支持在升高的温度下进行筛选以识别弱和有缺陷的存储器件。

5. 再颁专利

USRE36821E Wordline driver circuit having a directly gated pull-down device 失效
标题翻译：字线驱动电路具有直接门控下拉装置
公开(公告)号：USRE36821E
公开(公告)日：2000-08-15
申请号：US644351
申请日：1996-05-10
申请人： Stephen L. Casper , Paul S. Zagar , Adrian E. Ong
发明人： Stephen L. Casper , Paul S. Zagar , Adrian E. Ong
IPC分类号： G11C8/00 , G11C8/08
CPC分类号： G11C8/08
摘要： The invention is a circuit and method for quickly driving non-selected wordlines to correct potentials. The invention drives the non-selected wordlines to low potentials through a driving device directly gated by a primary select predecode signal generated by decode circuitry. The driving device is electrically interposed between the wordline and a reference node. The invention provides low power operation, and provides reliable wordline selection for circuits having supply potentials less than 5 volts.
摘要翻译：本发明是用于快速驱动未选择的字线以纠正电位的电路和方法。本发明通过由解码电路产生的初级选择预解码信号直接选通的驱动装置将未选择的字线驱动到低电位。驱动装置电插入字线和参考节点之间。本发明提供低功率操作，并且为电源电压低于5伏的电路提供可靠的字线选择。

6. 发明授权

US5999480A Dynamic random-access memory having a hierarchical data path 有权
标题翻译：具有分层数据路径的动态随机存取存储器
公开(公告)号：US5999480A
公开(公告)日：1999-12-07
申请号：US167259
申请日：1998-10-06
申请人： Adrian Ong , Paul S. Zagar , Troy Manning , Brent Keeth , Ken Waller
发明人： Adrian Ong , Paul S. Zagar , Troy Manning , Brent Keeth , Ken Waller
IPC分类号： G11C5/02 , G11C7/10 , G11C11/4096 , G11C29/00 , G11C29/36 , G11C8/00
CPC分类号： G11C29/785 , G11C11/4096 , G11C29/80 , G11C29/88 , G11C5/025 , G11C7/10 , G11C29/36
摘要： A semiconductor dynamic random-access memory (DRAM) device embodying numerous features that collectively and/or individually prove beneficial and advantageous with regard to such considerations as density, power consumption, speed, and redundancyis disclosed. The device is a 64 Mbit DRAM comprising eight substantially identical 8 Mbit partial array blocks (PABs), each pair of PABs comprising a 16 Mbit quadrant of the device. Between the top two quadrants and between the bottom two quadrants are column blocks containing I/O read/write circuitry, column redundancy fuses, and column decode circuitry. Column select lines originate from the column blocks and extend right and left across the width of each quadrant. Each PAB comprises eight substantially identical 1Mbit sub-array blocks (SABs). Associated with each SAB are a plurality of local row decoder circuits functioning to receive partially decoded row addresses from a column predecoder circuit and generating local row addresses supplied to the SAB with which they are associated. A hierarchical data path is provided wherein a plurality of multiplexers are distributed throughout each SAB, these multiplexers functioning to selectively couple sense amplifier output signals to local data I/O lines associated with each SAB. In one embodiment, the data path multiplexers are physically disposed within gaps defined by adjacent ones of the local row address decoders distributed throughout each SAB.
摘要翻译：一种体现许多特征的半导体动态随机存取存储器（DRAM）装置，其集合和/或单独证明在所公开的诸如密度，功耗，速度和冗余度之类的考虑方面是有益和有利的。该器件是包括八个基本上相同的8兆位部分阵列块（PAB）的64Mbit DRAM，每对PAB包括该器件的16Mb象限。顶部两个象限之间和底部两个象限之间是包含I / O读/写电路，列冗余保险丝和列解码电路的列块。列选择线来自列块，并在每个象限的宽度上左右延伸。每个PAB包括八个基本相同的1M位子阵列块（SAB）。与每个SAB相关联的是多个本地行解码器电路，用于从列预解码器电路接收部分解码的行地址，并产生提供给与它们相关联的SAB的本地行地址。提供了分层数据路径，其中多个复用器分布在每个SAB中，这些多路复用器用于选择性地将感测放大器输出信号耦合到与每个SAB相关联的本地数据I / O线。在一个实施例中，数据路径多路复用器物理地布置在分布在每个SAB中的相邻的本地行地址解码器限定的间隙内。

7. 发明授权

US5675549A Burst EDO memory device address counter 失效
标题翻译：突发EDO存储设备地址计数器
公开(公告)号：US5675549A
公开(公告)日：1997-10-07
申请号：US457651
申请日：1995-06-01
申请人： Adrian Ong , Paul S. Zagar , Brett L. Wiliams , Troy A. Manning
发明人： Adrian Ong , Paul S. Zagar , Brett L. Wiliams , Troy A. Manning
IPC分类号： G06F12/06 , G11C7/10 , G11C11/407 , G11C8/00
CPC分类号： G06F12/0638 , G11C11/407 , G11C7/1018 , G11C7/1021 , G11C7/1024 , G11C7/1039 , G11C7/1045 , G11C7/1078 , G11C7/109 , G11C7/1096 , G06F2212/2022
摘要： A counter comprised of two flip flops and a multiplexer produces a sequential or interleaved address sequence. The addresses produced are used to access memory elements in a Burst Extended Data Output Dynamic Random Access Memory (Burst EDO or BEDO DRAM). Input addresses in combination with a sequence select signal are logically combined to produce a multiplexer select input which selects between true and compliment outputs of a first flip flop to couple to an input of a second flip flop to specify a toggle condition for the second flip flop. Outputs of the counter are compared with outputs of an input address latch to detect the end of a burst sequence and initialize the device for another burst access. A transition of the Read/Write control line during a burst access will terminate the burst access and initialize the device for another burst access.
摘要翻译：由两个触发器和多路复用器组成的计数器产生顺序或交错地址序列。所产生的地址用于访问突发扩展数据输出动态随机存取存储器（Burst EDO或BEDO DRAM）中的存储器元件。与序列选择信号组合的输入地址被逻辑地组合以产生多路复用器选择输入，其选择第一触发器的真实和补码输出以耦合到第二触发器的输入以指定第二触发器的切换条件。将计数器的输出与输入地址锁存器的输出进行比较，以检测突发序列的结束，并初始化用于另一个突发存取的设备。在脉冲串访问期间读/写控制线的转换将终止脉冲串访问并初始化设备以进行另一个突发存取。

8. 发明授权

US6104645A High speed global row redundancy system 失效
标题翻译：高速全局行冗余系统
公开(公告)号：US6104645A
公开(公告)日：2000-08-15
申请号：US659724
申请日：1996-06-06
申请人： Adrian Ong , Paul S. Zagar
发明人： Adrian Ong , Paul S. Zagar
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/808
摘要： A row repair system for replacing a defective primary memory row with a redundant memory row within an entire section of an integrated circuit memory chip. The system comprises a dedicated match circuit for each redundant row in a given section. The match circuit analyzes incoming address information to determine whether the address corresponds to a memory location in a specific defective row in any one of a number of sub-array blocks within the section. When such a critical address is detected, the match circuit activates circuitry which inhibits access to the defective row and enables access to its dedicated redundant row.
摘要翻译：用于在集成电路存储器芯片的整个部分内用冗余存储器行替换有缺陷的主存储器行的行修复系统。该系统包括用于给定部分中的每个冗余行的专用匹配电路。匹配电路分析输入地址信息以确定地址是否对应于该区段内的多个子阵列块中的任何一个中的特定缺陷行中的存储器位置。当检测到这样的关键地址时，匹配电路激活禁止对缺陷行进行访问并允许访问其专用冗余行的电路。

9. 发明授权

US5528539A High speed global row redundancy system 失效
公开(公告)号：US5528539A
公开(公告)日：1996-06-18
申请号：US315154
申请日：1994-09-29
申请人： Adrian Ong , Paul S. Zagar
发明人： Adrian Ong , Paul S. Zagar
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/808
摘要： A row repair system for replacing a defective primary memory row with a redundant memory row within an entire section of an integrated circuit memory chip. The system comprises a dedicated match circuit for each redundant row in a given section. The match circuit analyzes incoming address information to determine whether the address corresponds to a memory location in a specific defective row in any one of a number of sub-array blocks within the section. When such a critical address is detected, the match circuit activates circuitry which inhibits access to the defective row and enables access to its dedicated redundant row.

10. 再颁专利

USRE36952E One time programmable fully-testable programmable logic device with zero power and anti-fuse cell architecture 失效
标题翻译：一次性可编程完全可测试的可编程逻辑器件，具有零功率和抗熔丝单元架构
公开(公告)号：USRE36952E
公开(公告)日：2000-11-14
申请号：US653516
申请日：1996-05-24
申请人： Paul S. Zagar , Kurt P. Douglas
发明人： Paul S. Zagar , Kurt P. Douglas
IPC分类号： G01R31/3185 , G11C17/16 , H03K19/173
CPC分类号： H03K19/1735 , G01R31/318516 , G11C17/16
摘要： There is a zero power programmable logic device with a one time programmable and fully-testable anti-fuse cell architecture. Specifically, a half-latch and fuse cell circuit allows the PLD to use "zero power" during the standby period since the sense amps are not used to maintain the programmed logic. Additionally, the PLD is capable of being tested for logic gate and logic path integrity, and anti-fuse electrical parameters without permanently programming the anti-fuse.
摘要翻译：有一个零功率可编程逻辑器件，具有一次性可编程和完全可测试的反熔丝单元架构。具体来说，半锁存和熔丝单元电路允许PLD在待机期间使用“零功率”，因为感测放大器不用于维持编程逻辑。此外，PLD能够对逻辑门和逻辑路径完整性进行测试，并且可以对反熔丝电气参数进行测试，而无需永久编程防熔丝。

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