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1. 发明授权

US07564284B2 Time delay circuit and time to digital converter 有权
标题翻译：时间延迟电路和数字转换器的时间
公开(公告)号：US07564284B2
公开(公告)日：2009-07-21
申请号：US11728442
申请日：2007-03-26
申请人： Stephan Henzler , Siegmar Köppe , Dominik Lorenz
发明人： Stephan Henzler , Siegmar Köppe , Dominik Lorenz
IPC分类号： H03H11/26
CPC分类号： H03K5/13 , G04F10/06 , H03K5/135 , H03L7/085 , H03M1/205
摘要： A time delay circuit is disclosed and includes a delay line with a first delay circuit and at least a second delay circuit connected downstream. An interpolation circuit is used to generate intermediate signals derived by delayed successive signals in the delay line.
摘要翻译：公开了一种延时电路，并且包括具有第一延迟电路和至少连接在下游的第二延迟电路的延迟线。内插电路用于产生由延迟线中延迟的连续信号导出的中间信号。

2. 发明授权

US07696829B2 Frequency synthesizer and method 有权
标题翻译：频率合成器和方法
公开(公告)号：US07696829B2
公开(公告)日：2010-04-13
申请号：US11524674
申请日：2006-09-21
申请人： Stephan Henzler , Siegmar Köppe
发明人： Stephan Henzler , Siegmar Köppe
IPC分类号： H03L7/093 , H03C3/06
CPC分类号： H03L7/0991 , H03L7/08 , H03L7/18 , H03L2207/50
摘要： A synthesizer arrangement includes an oscillator, a phase detector, and a loop filter that form a phase-locked loop. The loop filter is coupled to a control unit to activate a respective set of internal states out of a plurality of sets of internal states.
摘要翻译：合成器装置包括形成锁相环的振荡器，相位检测器和环路滤波器。环路滤波器耦合到控制单元以激活多组内部状态中的相应的一组内部状态。

3. 发明授权

US07688126B2 Time delay circuit and time to digital converter 有权
标题翻译：时间延迟电路和数字转换器的时间
公开(公告)号：US07688126B2
公开(公告)日：2010-03-30
申请号：US12362247
申请日：2009-01-29
申请人： Stephan Henzler , Siegmar Köppe , Dominik Lorenz
发明人： Stephan Henzler , Siegmar Köppe , Dominik Lorenz
IPC分类号： H03H11/26
CPC分类号： H03K5/13 , G04F10/06 , H03K5/135 , H03L7/085 , H03M1/205
摘要： A time delay circuit is disclosed and includes a delay line with a first delay circuit and at least a second delay circuit connected downstream. An interpolation circuit is used to generate intermediate signals derived by delayed successive signals in the delay line.
摘要翻译：公开了一种延时电路，并且包括具有第一延迟电路和至少连接在下游的第二延迟电路的延迟线。内插电路用于产生由延迟线中延迟的连续信号导出的中间信号。

4. 发明授权

US06661701B2 Three-transistor DRAM cell and associated fabrication method 失效
标题翻译：三晶体DRAM单元及相关制造方法
公开(公告)号：US06661701B2
公开(公告)日：2003-12-09
申请号：US10158032
申请日：2002-05-30
申请人： Claus Dahl , Siegmar Köppe
发明人： Claus Dahl , Siegmar Köppe
IPC分类号： G11C1124
CPC分类号： H01L27/108
摘要： The three-transistor DRAM cell has a memory transistor formed as a field-effect transistor with a short-channel section and a long-channel section. A second insulating layer and a conductive layer are additionally formed on a gate layer of the memory transistor. A substantially constant voltage value is present between a potential of the conductive layer and a potential of the substrate area. A three-transistor DRAM cell with improved interference immunity and charge retention time
摘要翻译：三晶体管DRAM单元具有形成为具有短沟道部分和长沟道部分的场效应晶体管的存储晶体管。另外在存储晶体管的栅极层上形成第二绝缘层和导电层。在导电层的电位和衬底区域的电位之间存在基本恒定的电压值。具有改善的抗干扰性和电荷保留时间的三晶体管DRAM单元

5. 发明授权

US07509561B2 Parity checking circuit for continuous checking of the parity of a memory cell 有权
标题翻译：用于连续检查存储单元奇偶校验的奇偶校验电路
公开(公告)号：US07509561B2
公开(公告)日：2009-03-24
申请号：US11063953
申请日：2005-02-23
申请人： Winfried Kamp , Siegmar Köppe
发明人： Winfried Kamp , Siegmar Köppe
IPC分类号： H03M13/00
CPC分类号： G11C15/04 , G06F11/1048 , G11C15/00 , G11C2029/0411
摘要： A parity checking circuit is designed for continuous parity checking of content-addressable memory cells, and is configured such that during a parity check the number of parity checking steps per data word is the same as the number of bits in the original payload data word to be stored, with the parity checking circuit being formed from four transistors of the same conductance type. The parity checking circuit has a detector, which automatically detects the change in an information state of a memory cell. The detector is in the form of an automatic state device and has a number of catch latches.
摘要翻译：奇偶校验电路被设计用于可内容寻址存储器单元的连续奇偶校验，并且被配置为使得在奇偶校验期间，每个数据字的奇偶校验步骤的数量与原始有效载荷数据字中的位数相同存储奇偶校验电路由相同电导型的四个晶体管形成。奇偶校验电路具有检测器，其自动检测存储器单元的信息状态的变化。检测器是自动状态设备的形式，并具有多个锁存器。

6. 发明授权

US07386776B2 System for testing digital components 有权
标题翻译：数字元件测试系统
公开(公告)号：US07386776B2
公开(公告)日：2008-06-10
申请号：US10514537
申请日：2003-05-14
申请人： Ralf Arnold , Matthias Heinitz , Siegmar Köppe , Volker Schöber
发明人： Ralf Arnold , Matthias Heinitz , Siegmar Köppe , Volker Schöber
IPC分类号： G06F11/00
CPC分类号： G01R31/3183 , G01R31/31813 , G01R31/318547
摘要： In order to test digital modules with functional elements, these are divided into test units (3) which respectively have inputs and outputs. Alternating test patterns are applied to the inputs of the test unit (3), and the test responses resulting from this are evaluated at the outputs of the test unit (3). The effect is then encountered that changes at each of the inputs of a test unit (3) do not all affect a particular output of this test unit (3). For every output of the test unit (3), it is possible to define a cone (5) whose apex is formed by the particular output of the test unit (3) and whose base comprises the inputs of the test unit (3) where, and only where, changes affect the particular output. According to the invention, the test pattern to be applied to the inputs of the test unit (3) is constructed of sub-patterns, whose length is in particular ≦ the number of inputs of the test unit (3) that are contained in the base of a cone (5). Owing to their shorter length, all possible combinations can be used for selecting the sub-patterns, so that a comprehensive function test of the test unit (3) can be carried out rapidly and with little outlay. In a digital module, this test function may in particular be implemented by a self-test unit (1) which can switch over the rest of the digital module into a test mode, generates the test patterns on the basis of sub-patterns, loads them into a test-pattern output register (2) for application to a test unit (3) and can evaluate the test response subsequently found at the outputs of the test unit (3) by means of an evaluation unit (16), or read it in for evaluation.
摘要翻译：为了测试具有功能元件的数字模块，它们分为测试单元（3），分别具有输入和输出。将交替测试图案应用于测试单元（3）的输入，并且在测试单元（3）的输出处评估由此产生的测试响应。然后会遇到测试单元（3）的每个输入端的变化都不会影响该测试单元（3）的特定输出的效果。对于测试单元（3）的每个输出，可以定义锥形（5），其顶点由测试单元（3）的特定输出形成，并且其底部包括测试单元（3）的输入，其中，只有在这些变化影响特定的输出。根据本发明，应用于测试单元（3）的输入的测试模式由子模式构成，子模式的长度特别地<=测试单元（3）的输入数量锥体的底部（5）。由于其长度较短，所有可能的组合都可用于选择子图案，从而可以快速实现测试单元（3）的综合功能测试，并且具有很少的支出。在数字模块中，该测试功能可以特别地由可以将数字模块的其余部分切换到测试模式的自检单元（1）来实现，并且基于子模式生成测试模式它们进入用于应用于测试单元（3）的测试图案输出寄存器（2），并且可以通过评估单元（16）评估随后在测试单元（3）的输出处发现的测试响应，或读取它用于评估。

7. 发明授权

US08188780B2 Pulsed static flip-flop 有权
标题翻译：脉冲静态触发器
公开(公告)号：US08188780B2
公开(公告)日：2012-05-29
申请号：US11648194
申请日：2006-12-29
申请人： Christian Pacha , Siegmar Köppe , Karl Zapf
发明人： Christian Pacha , Siegmar Köppe , Karl Zapf
IPC分类号： H03K3/00
CPC分类号： H03K3/35625 , H03K3/012
摘要： A pulsed static flip-flop comprises a first logic device which combines a logic signal with a pulsed signal and outputs a set signal, a second logic device which logically combines the logic signal with a complementary pulsed signal and outputs a reset signal; and a latch device comprising storage means which hold a logic hold level to be tapped off as a stored logic state of the logic signal. The logic hold level is adjustable to a first logic level by a first push-pull transistor controlled by the set signal and to a second logic level by a second push-pull transistor controlled by the reset signal.
摘要翻译：脉冲静态触发器包括将逻辑信号与脉冲信号组合并输出设定信号的第一逻辑器件，将逻辑信号与互补脉冲信号逻辑组合并输出复位信号的第二逻辑器件; 以及锁存装置，其包括存储装置，其保持要作为逻辑信号的存储的逻辑状态被分接的逻辑保持电平。逻辑保持电平由被设置信号控制的第一推挽晶体调节到第一逻辑电平，并且由复位信号控制的第二推挽晶体调节到第二逻辑电平。

8. 发明授权

US07158396B2 CAM (content addressable memory) apparatus 有权
标题翻译： CAM（内容可寻址存储器）装置
公开(公告)号：US07158396B2
公开(公告)日：2007-01-02
申请号：US10723833
申请日：2003-11-26
申请人： Noel Hatsch , Winfried Kamp , Siegmar Köppe , Thomas Künemund , Heinz Söldner , Michel D'Argouges
发明人： Noel Hatsch , Winfried Kamp , Siegmar Köppe , Thomas Künemund , Heinz Söldner , Michel D'Argouges
IPC分类号： G11C15/00
CPC分类号： G06F7/02 , G06F2207/025 , G11C15/04
摘要： The present invention provides a CAM (content addressable memory) apparatus having: a first memory device (10) with a word line input (WL) and at least one storage node (12; 13) for storing a first bit of a data word; a second memory device (11) with a word line input (WL) and at least one storage node (14; 15) for storing a second bit of a data word; and a comparator device (16) for comparing the first and second stored bits with two precoded comparison bits fed via four inputs (20; 21; 22; 23) and for driving a hit node (17) in the event of the first stored bit corresponding to the first comparison bit and the second stored bit corresponding to the second comparison bit.
摘要翻译：本发明提供一种CAM（内容可寻址存储器）装置，其具有：具有字线输入（WL）的第一存储器件（10）和用于存储数据字的第一位的至少一个存储节点（12; 13）具有字线输入（WL）的第二存储器件（11）和用于存储数据字的第二位的至少一个存储节点（14; 15）以及比较器装置（16），用于将第一和第二存储位与经由四个输入（20; 21; 22; 23）馈送的两个预编码比较位进行比较，并且用于在第一个存储位的情况下驱动命中节点（17）对应于对应于第二比较位的第一比较位和第二存储位。

9. 发明申请

US20100308863A1 Architecture of Function Blocks and Wirings in a Structured ASIC and Configurable Driver Cell of a Logic Cell Zone 审中-公开
标题翻译：结构化ASIC中的功能块和布线的结构以及逻辑单元区的可配置驱动单元
公开(公告)号：US20100308863A1
公开(公告)日：2010-12-09
申请号：US12780772
申请日：2010-05-14
申请人： Jörg Gliese , Winfried Kamp , Siegmar Köppe , Michael Scheppler
发明人： Jörg Gliese , Winfried Kamp , Siegmar Köppe , Michael Scheppler
IPC分类号： H03K19/177
CPC分类号： H03K19/1735 , H01L27/11807
摘要： An integrated semiconductor circuit has a regular array of logic function blocks (L) and a regular array of wiring zones (X) corresponding thereto. The wiring lines in at least one wiring layer of a wiring zone (X) are realized as line segments that are continuous within the wiring zone and are interrupted at zone boundaries. Furthermore, the semiconductor circuit comprises driver cells that surround a logic cell of the logic function block in an L-shaped manner.
摘要翻译：集成半导体电路具有规则的逻辑功能块（L）阵列和对应于其的布线区域（X）的规则阵列。布线区域（X）的至少一个布线层中的布线被实现为在布线区域内连续并在区域边界处中断的线段。此外，半导体电路包括以L形方式围绕逻辑功能块的逻辑单元的驱动器单元。

10. 发明授权

US07755110B2 Architecture of function blocks and wirings in a structured ASIC and configurable driver cell of a logic cell zone 有权
标题翻译：逻辑单元区域的结构化ASIC和可配置驱动单元中的功能块和布线的架构
公开(公告)号：US07755110B2
公开(公告)日：2010-07-13
申请号：US11088506
申请日：2005-03-24
申请人： Jörg Gliese , Winfried Kamp , Siegmar Köppe , Michael Scheppler
发明人： Jörg Gliese , Winfried Kamp , Siegmar Köppe , Michael Scheppler
IPC分类号： H01L27/10
CPC分类号： H03K19/1735 , H01L27/11807
摘要： An integrated semiconductor circuit has a regular array of logic function blocks (L) and a regular array of wiring zones (X) corresponding thereto. The wiring lines in at least one wiring layer of a wiring zone (X) are realized as line segments that are continuous within the wiring zone and are interrupted at zone boundaries. Furthermore, the semiconductor circuit comprises driver cells that surround a logic cell of the logic function block in an L-shaped manner.
摘要翻译：集成半导体电路具有规则的逻辑功能块（L）阵列和对应于其的布线区域（X）的规则阵列。布线区域（X）的至少一个布线层中的布线被实现为在布线区域内连续并在区域边界处中断的线段。此外，半导体电路包括以L形方式围绕逻辑功能块的逻辑单元的驱动器单元。

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