专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5530293A Carbon-free hydrogen silsesquioxane with dielectric constant less than 3.2 annealed in hydrogen for integrated circuits 失效
标题翻译：介电常数小于3.2的无碳氢倍半硅氧烷在氢气中退火用于集成电路
公开(公告)号：US5530293A
公开(公告)日：1996-06-25
申请号：US345099
申请日：1994-11-28
申请人： Stephan A. Cohen , Vincent J. McGahay , Ronald R. Uttecht
发明人： Stephan A. Cohen , Vincent J. McGahay , Ronald R. Uttecht
IPC分类号： H01L21/768 , H01L21/316 , H01L21/762 , H01L23/522 , H01L23/532 , H01L23/485
CPC分类号： H01L23/5329 , H01L21/76224 , H01L23/5222 , H01L2924/0002
摘要： An insulator for covering an interconnection wiring level in a surface thereof on a semiconductor substrate containing semiconductor devices formed by curing a flowable oxide layer and annealing is provided. The annealing is carried out in the presence of hydrogen and aluminum to obtain a dielectric constant of the oxide layer to a value below 3.2. Also provided is electrical insulation between neighboring devices using the flowable oxide which is cured and annealed. In this case, the annealing can be carried out in hydrogen with or without the presence of aluminum.
摘要翻译：提供一种用于在包含通过固化可流动氧化物层和退火形成的半导体器件的半导体衬底上的表面中覆盖互连布线层的绝缘体。退火在氢和铝的存在下进行，以获得低于3.2的氧化物层的介电常数。还提供了使用可固化和退火的可流动氧化物的相邻装置之间的电绝缘。在这种情况下，退火可以在有或者没有铝的情况下在氢气中进行。

2. 发明授权

US5760674A Fusible links with improved interconnect structure 失效
标题翻译：具有改进的互连结构的易熔链
公开(公告)号：US5760674A
公开(公告)日：1998-06-02
申请号：US563691
申请日：1995-11-28
申请人： Richard A. Gilmour , Ronald R. Uttecht , Erick G. Walton
发明人： Richard A. Gilmour , Ronald R. Uttecht , Erick G. Walton
IPC分类号： H01L23/525 , H01H85/00
CPC分类号： H01L23/5258 , H01L2924/0002
摘要： The fuse link includes a first and second interconnect, with interconnects each being substantially longer than deep. The interconnects are disposed toward each other with a insulator region between them. A fusible conductor, spanning the insulator region, is attached at the top of the interconnects. The present device allows the length of the fusible conductor to be shortened, and results in a fuse link that can be consistently blown with a single laser pulse. Additionally, the fuse link can be used in a staggered layout. The staggered layout of parallel fuse links allows a high number of links in a relatively small area, with or without the use of tungsten barriers, and allows accessing all fuse links through a single fuse blow window.
摘要翻译：熔丝连接件包括第一和第二互连件，其互连件基本上比深度长。互连通过它们之间的绝缘体区域彼此相对设置。跨越绝缘体区域的可熔导体连接在互连的顶部。本装置允许可熔导体的长度缩短，并且导致可以用单个激光脉冲一致地熔断的熔丝链。此外，熔丝链可以以交错的布局使用。平行熔丝链的交错布局允许在有或没有使用钨屏障的情况下，在相对较小的区域中有大量的连接，并且允许通过单个保险丝熔断窗口访问所有熔丝链。

3. 发明授权

US5523253A Array protection devices and fabrication method 失效
标题翻译：阵列保护装置及制造方法
公开(公告)号：US5523253A
公开(公告)日：1996-06-04
申请号：US389529
申请日：1995-02-16
申请人： Richard A. Gilmour , Thomas J. Hartswick , David C. Thomas , Ronald R. Uttecht , Erick G. Walton
发明人： Richard A. Gilmour , Thomas J. Hartswick , David C. Thomas , Ronald R. Uttecht , Erick G. Walton
IPC分类号： H01L23/62 , H01L21/82
CPC分类号： H01L23/62 , H01L2924/0002
摘要： The present disclosure sets forth an improved integrated circuit in which circuit elements, adjacent to a fuse, are protected by barriers positioned adjacent the fuse. In the improved integrated circuit the barriers are non-frangible, high melting point structures buried in the passivating layer, covering a wiring layer containing a fuse, and are between the fuse and adjacent circuit elements in the wiring layer structures.Also taught is a method of protecting circuit elements adjacent a fuse comprising the steps of depositing an insulating layer on the surface of a semiconductor device having active regions therein, forming a plurality of fuses and circuit elements in said layer, coating said fuses and elements with a second insulating layer, patterning said second insulating layer to form grooves between each of said fuses and any adjacent fuse or circuit element, and depositing a high melting point and non-frangible material in said grooves.
摘要翻译：本公开提出了一种改进的集成电路，其中与保险丝相邻的电路元件由位于保险丝附近的屏障保护。在改进的集成电路中，阻挡层是非易碎的，高熔点结构掩埋在钝化层中，覆盖包含保险丝的布线层，并且位于布线层结构中的熔丝和相邻的电路元件之间。还教导了一种保护靠近熔丝的电路元件的方法，包括以下步骤：在其中具有有源区的半导体器件的表面上沉积绝缘层，在所述层中形成多个保险丝和电路元件，将所述保险丝和元件涂覆第二绝缘层，图案化所述第二绝缘层以在每个所述保险丝和任何相邻的熔丝或电路元件之间形成槽，以及在所述槽中沉积高熔点和非易碎材料。

4. 发明授权

US6093630A Semi-conductor personalization structure and method 失效
标题翻译：半导体个性化结构与方法
公开(公告)号：US6093630A
公开(公告)日：2000-07-25
申请号：US80573
申请日：1998-05-18
申请人： Robert Michael Geffken , William Thomas Motsiff , Ronald R. Uttecht
发明人： Robert Michael Geffken , William Thomas Motsiff , Ronald R. Uttecht
IPC分类号： H01L23/485 , H01L23/525 , H01L21/44
CPC分类号： H01L24/10 , H01L23/525 , H01L24/13 , H01L2224/05558 , H01L2224/05572 , H01L2224/13 , H01L2224/13099 , H01L2224/45124 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14
摘要： The preferred embodiment of the present invention provides a structure and method for personalizing a semiconductor device in the context of a bump array connection to packaging, substrates and such. The preferred embodiment method uses a plurality of conduction lines on said semiconductor device, including a plurality of landing lines and personalization lines. Vias are opened to the plurality of landing lines and selectively opened to a portion of the personalization lines. Connections are made between the opened personalization lines with bumps deposited as part of the bump array.
摘要翻译：本发明的优选实施例提供了在与封装，基板等的凸点阵列连接的上下文中个性化半导体器件的结构和方法。优选实施例的方法在所述半导体器件上使用多条导线，包括多条着陆线和个性化线。通孔对多个着陆线打开，并且选择性地打开到个性化生产线的一部分。在打开的个性化线之间形成连接，其中凸起作为凸块阵列的一部分。

5. 发明授权

US5883435A Personalization structure for semiconductor devices 失效
标题翻译：半导体器件的个性化结构
公开(公告)号：US5883435A
公开(公告)日：1999-03-16
申请号：US686899
申请日：1996-07-25
申请人： Robert Michael Geffken , William Thomas Motsiff , Ronald R. Uttecht
发明人： Robert Michael Geffken , William Thomas Motsiff , Ronald R. Uttecht
IPC分类号： H01L23/485 , H01L23/525 , H01L23/48 , H01L23/52
CPC分类号： H01L24/10 , H01L23/525 , H01L24/13 , H01L2224/05558 , H01L2224/05572 , H01L2224/13 , H01L2224/13099 , H01L2224/45124 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14
摘要： The preferred embodiment of the present invention provides a structure and method for personalizing a semiconductor device in the context of a bump array connection to packaging, substrates and such. The preferred embodiment method uses a plurality of conduction lines on said semiconductor device, including a plurality of landing lines and personalization lines. Vias are opened to the plurality of landing lines and selectively opened to a portion of the personalization lines. Connections are made between the opened personalization lines with bumps deposited as part of the bump array.
摘要翻译：本发明的优选实施例提供了在与封装，基板等的凸点阵列连接的上下文中个性化半导体器件的结构和方法。优选实施例方法在所述半导体器件上使用多条导线，包括多条着陆线和个性化线。通孔对多个着陆线打开，并且选择性地打开到个性化生产线的一部分。在打开的个性化线之间形成连接，其中凸起作为凸块阵列的一部分。

6. 发明授权

US4981530A Planarizing ladder-type silsesquioxane polymer insulation layer 失效
标题翻译：平面化阶梯型倍半硅氧烷聚合物绝缘层
公开(公告)号：US4981530A
公开(公告)日：1991-01-01
申请号：US276597
申请日：1988-11-28
申请人： Donna J. Clodgo , Rosemary A. Previti-Kelly , Ronald R. Uttecht , Erick G. Walton
发明人： Donna J. Clodgo , Rosemary A. Previti-Kelly , Ronald R. Uttecht , Erick G. Walton
IPC分类号： H01B3/46 , C08G77/06 , C08G77/26 , C08G77/28 , C09D183/04 , H01L21/312 , H01L23/29
CPC分类号： H01L21/02126 , H01L21/02216 , H01L21/02282 , H01L21/3121 , H01L21/3122 , H01L23/293 , H01L2924/0002
摘要： An improved insulation layer is formed by first preparing a solution by reacting water with an aminoalkoxysilane monomer in a solvent, using a critical mole ratio of water/monomer. After a sufficient aging period, the solution is coated onto a suitable surface, e.g. the surface of a semiconductor device, and then cured, in an essentially oxygen-free atmosphere, to a ladder-type silsesquioxane polymer. The insulation layer demonstrates excellent planarizing characteristics, while also exhibiting enhanced crack-resistance.

7. 发明授权

US6054339A Fusible links formed on interconnects which are at least twice as long as they are deep 失效
标题翻译：在互连上形成的可熔链，至少是深度的两倍
公开(公告)号：US6054339A
公开(公告)日：2000-04-25
申请号：US810587
申请日：1997-03-04
申请人： Richard A. Gilmour , Ronald R. Uttecht , Erick G. Walton
发明人： Richard A. Gilmour , Ronald R. Uttecht , Erick G. Walton
IPC分类号： H01L23/525 , H01L21/82
CPC分类号： H01L23/5258 , H01L2924/0002
摘要： A shortened fuse link is disclosed. The fuse link comprises a first and second interconnect, with interconnects each being substantially longer than deep. The interconnects are disposed toward each other with a insulator region between them. A fusible conductor, spanning the insulator region, is attached at the top of the interconnects. The present device allows the length of the fusible conductor to be shortened, and results in a fuse link that can be consistently blown with a single laser pulse. Additionally, the fuse link can be used in a staggered layout. The staggered layout of parallel fuse links allows a high number of links in a relatively small area, with or without the use of tungsten barriers, and allows accessing all fuse links through a single fuse blow window.
摘要翻译：公开了一种缩短的熔断体。熔丝连接件包括第一和第二互连件，每个互连件基本上比深度长。互连通过它们之间的绝缘体区域彼此相对设置。跨越绝缘体区域的可熔导体连接在互连的顶部。本装置允许可熔导体的长度缩短，并且导致可以用单个激光脉冲一致地熔断的熔丝链。此外，熔丝链可以以交错的布局使用。平行熔丝链的交错布局允许在有或没有使用钨屏障的情况下，在相对较小的区域中有大量的连接，并且允许通过单个保险丝熔断窗口访问所有熔丝链。

8. 发明授权

US5286572A Planarizing ladder-type silsequioxane polymer insulation layer 失效
标题翻译：平面化梯形硅氧烷聚合物绝缘层
公开(公告)号：US5286572A
公开(公告)日：1994-02-15
申请号：US924414
申请日：1992-07-30
申请人： Donna J. Clodgo , Rosemary A. Previti-Kelly , Ronald R. Uttecht , Erick G. Walton
发明人： Donna J. Clodgo , Rosemary A. Previti-Kelly , Ronald R. Uttecht , Erick G. Walton
IPC分类号： H01L21/312 , H01L23/29 , B32B9/04
CPC分类号： H01L21/02126 , H01L21/02216 , H01L21/02282 , H01L21/3121 , H01L21/3122 , H01L23/293 , H01L2924/0002 , Y10T428/31612 , Y10T428/31663
摘要： An improved insulation layer is formed by first preparing a solution by reacting water with an aminoalkoxysilane monomer in a solvent, using a critical mole ratio of water/monomer. After a sufficient aging period, the solution is coated onto a suitable surface, e.g. the surface of a semiconductor device, and then cured, in an essentially oxygen-free atmosphere, to a ladder-type silsesquioxane polymer. The insulation layer demonstrates excellent planarizing characteristics, while also exhibiting enhanced crack-resistance.
摘要翻译：通过使用水/单体的临界摩尔比，首先通过使水与氨基烷氧基硅烷单体在溶剂中反应来制备溶液来形成改进的绝缘层。在足够的老化时间之后，将溶液涂覆到合适的表面上，例如半导体器件的表面，然后在基本上无氧的气氛中固化到梯型倍半硅氧烷聚合物。绝缘层表现出优异的平坦化特性，同时表现出增强的抗裂性。

9. 发明授权

US5126006A Plural level chip masking 失效
标题翻译：多级芯片屏蔽
公开(公告)号：US5126006A
公开(公告)日：1992-06-30
申请号：US708608
申请日：1991-05-31
申请人： John E. Cronin , Paul A. Farrar, Sr. , Robert M. Geffken , William H. Guthrie , Carter W. Kaanta , Rosemary A. Previti-Kelly , James G. Ryan , Ronald R. Uttecht , Andrew J. Watts
发明人： John E. Cronin , Paul A. Farrar, Sr. , Robert M. Geffken , William H. Guthrie , Carter W. Kaanta , Rosemary A. Previti-Kelly , James G. Ryan , Ronald R. Uttecht , Andrew J. Watts
IPC分类号： G03F1/00 , G03F7/00
CPC分类号： G03F7/0035 , G03F1/50
摘要： A sequence of masking steps reduces the amount of transference of a workpiece among work stations and reduces certain tolerances required for mask alignment in the construction of integrated circuits, and a gray level mask suitable for photolithography. In the integrated circuit, masking layers are developed directly in a wafer for delineating vertical and horizontal portions of an electrically conductive path. The mask is constructed of a transparent glass substrate which supports plural levels of materials having different optical transmissivities. In the case of a mask employing only two of these levels, one level may be constructed of a glass made partially transmissive by substitution of silver ions in place of metal ions of alkali metal silicates employed in the construction of the glass. The second layer may be made opaque by construction of the layer of a metal such as chromium. Both the wafer and the mask are fabricated by a photoresist structure which is etched in specific regions by photolithographic masking to enable selective etching of exposed regions of the level of materials of differing optical transmissivities. Various etches are employed for selective etching of the photoresist and other ones of the layers. The etches include plasma etch with chloride ions to attack the chromium of the opaque layer, compounds of fluorine to attack the glass layer, and reactive ion etching with oxygen to attack the photoresist structure.
摘要翻译：一系列掩蔽步骤减少了工件之间工件的移动量，并降低了集成电路结构中掩模对准所需的某些公差以及适用于光刻的灰度级掩模。在集成电路中，掩模层直接在晶片中显影，用于描绘导电路径的垂直和水平部分。掩模由透明玻璃基板构成，其支撑具有不同透光率的多层材料。在仅使用这些水平中的两个的掩模的情况下，一个层可以由通过取代银离子代替在玻璃的结构中使用的碱金属硅酸盐的金属离子而部分透射的玻璃构成。第二层可以通过金属如铬的构造而变得不透明。晶片和掩模都通过光致抗蚀剂结构制造，该光致抗蚀剂结构通过光刻掩模在特定区域中被蚀刻，以使得能够选择性地蚀刻具有不同光学透射率的材料层的暴露区域。各种蚀刻用于选择性蚀刻光致抗蚀剂和其它层。蚀刻包括用氯离子等离子体蚀刻以侵蚀不透明层的铬，氟的化合物侵蚀玻璃层，以及用氧反应离子蚀刻以侵蚀光致抗蚀剂结构。

10. 发明授权

US5576246A Personalized area leadframe coining or half etching for reduced mechanical stress at device edge 失效
标题翻译：个性化区域引线框压印或半刻蚀，以减少器件边缘的机械应力
公开(公告)号：US5576246A
公开(公告)日：1996-11-19
申请号：US458848
申请日：1995-06-02
申请人： Harold W. Conru , Francis E. Froebel , Albert J. Gregoritsch, Jr. , Sheldon C. Rieley , Stephen G. Starr , Ronald R. Uttecht , Eric J. White , Jens G. Pohl
发明人： Harold W. Conru , Francis E. Froebel , Albert J. Gregoritsch, Jr. , Sheldon C. Rieley , Stephen G. Starr , Ronald R. Uttecht , Eric J. White , Jens G. Pohl
IPC分类号： H01L23/50 , H01L23/00 , H01L23/495 , H01L21/60
CPC分类号： H01L23/564 , H01L23/4951 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/73215 , H01L24/48 , H01L2924/00014 , H01L2924/07802 , H01L2924/14 , H01L2924/3011 , Y10T29/49121
摘要： A lead on chip (LOC) semiconductor leadframe package provides notched lead-fingers to eliminate mechanical shear-stress at the peripheral edge of a semiconductor chip. Opposite rows of substantially flat cantilevered lead-fingers are attached by double-sided adhesive tape in thermal contact with the active face of a chip. The lead-fingers are routed in personalized paths over the face of the chip to cover a large surface area to aid heat dissipation. All wirebond connections between the lead-fingers and the chip are made at a centerline connection strip running down the center of the chip. Each of the cantilevered lead-fingers has a notched portion positioned directly over the vulnerable peripheral chip edge to reduce thermal, mechanical shear-stress. Additionally, since corrosion typically follows a lead path, the notch provides increasing path length to prevent corrosive ingress over the chip face.
摘要翻译：片上芯片（LOC）半导体引线框封装提供缺口引线以消除半导体芯片外围边缘的机械剪切应力。基本上平坦的悬臂式引指的相对排通过双面胶带与芯片的主动面热接触。引线指状物以个性化的路径布置在芯片的表面上以覆盖大的表面积以有助于散热。引线指和芯片之间的所有引线键合都是在沿芯片中心延伸的中心线连接条上制成的。每个悬臂的引指具有直接位于脆弱的外围芯片边缘上方的切口部分，以减少热，机械剪切应力。此外，由于腐蚀通常遵循引导路径，所以凹口提供增加的路径长度以防止在芯片表面上的腐蚀性侵入。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式