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1. 发明授权

US5420455A Array fuse damage protection devices and fabrication method 失效
标题翻译：阵列保险丝损坏保护装置及制造方法
公开(公告)号：US5420455A
公开(公告)日：1995-05-30
申请号：US221715
申请日：1994-03-31
申请人： Richard A. Gilmour , Thomas J. Hartswick , David C. Thomas , Ronald R. Uttecht , Erick G. Walton
发明人： Richard A. Gilmour , Thomas J. Hartswick , David C. Thomas , Ronald R. Uttecht , Erick G. Walton
IPC分类号： H01L23/62 , H01L27/02
CPC分类号： H01L23/62 , H01L2924/0002
摘要： The present disclosure sets forth an improved integrated circuit in which circuit elements, adjacent to a fuse, are protected by barriers positioned adjacent the fuse. In the improved integrated circuit the barriers are non-frangible, high melting point structures buried in the passivating layer, covering a wiring layer containing a fuse, and are between the fuse and adjacent circuit elements in the wiring layer structures.Also taught is a method of protecting circuit elements adjacent a fuse comprising the steps of depositing an insulating layer on the surface of a semiconductor device having active regions therein, forming a plurality of fuses and circuit elements in said layer, coating said fuses and elements with a second insulating layer, patterning said second insulating layer to form grooves between each of said fuses and any adjacent fuse or circuit element, and depositing a high melting point and non-frangible material in said grooves.
摘要翻译：本公开提出了一种改进的集成电路，其中与保险丝相邻的电路元件由位于保险丝附近的屏障保护。在改进的集成电路中，阻挡层是非易碎的，高熔点结构掩埋在钝化层中，覆盖包含保险丝的布线层，并且位于布线层结构中的熔丝和相邻的电路元件之间。还教导了一种保护靠近熔丝的电路元件的方法，包括以下步骤：在其中具有有源区的半导体器件的表面上沉积绝缘层，在所述层中形成多个保险丝和电路元件，将所述保险丝和元件涂覆第二绝缘层，图案化所述第二绝缘层以在每个所述保险丝和任何相邻的熔丝或电路元件之间形成槽，以及在所述槽中沉积高熔点和非易碎材料。

2. 发明授权

US5523253A Array protection devices and fabrication method 失效
标题翻译：阵列保护装置及制造方法
公开(公告)号：US5523253A
公开(公告)日：1996-06-04
申请号：US389529
申请日：1995-02-16
申请人： Richard A. Gilmour , Thomas J. Hartswick , David C. Thomas , Ronald R. Uttecht , Erick G. Walton
发明人： Richard A. Gilmour , Thomas J. Hartswick , David C. Thomas , Ronald R. Uttecht , Erick G. Walton
IPC分类号： H01L23/62 , H01L21/82
CPC分类号： H01L23/62 , H01L2924/0002
摘要： The present disclosure sets forth an improved integrated circuit in which circuit elements, adjacent to a fuse, are protected by barriers positioned adjacent the fuse. In the improved integrated circuit the barriers are non-frangible, high melting point structures buried in the passivating layer, covering a wiring layer containing a fuse, and are between the fuse and adjacent circuit elements in the wiring layer structures.Also taught is a method of protecting circuit elements adjacent a fuse comprising the steps of depositing an insulating layer on the surface of a semiconductor device having active regions therein, forming a plurality of fuses and circuit elements in said layer, coating said fuses and elements with a second insulating layer, patterning said second insulating layer to form grooves between each of said fuses and any adjacent fuse or circuit element, and depositing a high melting point and non-frangible material in said grooves.
摘要翻译：本公开提出了一种改进的集成电路，其中与保险丝相邻的电路元件由位于保险丝附近的屏障保护。在改进的集成电路中，阻挡层是非易碎的，高熔点结构掩埋在钝化层中，覆盖包含保险丝的布线层，并且位于布线层结构中的熔丝和相邻的电路元件之间。还教导了一种保护靠近熔丝的电路元件的方法，包括以下步骤：在其中具有有源区的半导体器件的表面上沉积绝缘层，在所述层中形成多个保险丝和电路元件，将所述保险丝和元件涂覆第二绝缘层，图案化所述第二绝缘层以在每个所述保险丝和任何相邻的熔丝或电路元件之间形成槽，以及在所述槽中沉积高熔点和非易碎材料。

3. 发明授权

US5760674A Fusible links with improved interconnect structure 失效
标题翻译：具有改进的互连结构的易熔链
公开(公告)号：US5760674A
公开(公告)日：1998-06-02
申请号：US563691
申请日：1995-11-28
申请人： Richard A. Gilmour , Ronald R. Uttecht , Erick G. Walton
发明人： Richard A. Gilmour , Ronald R. Uttecht , Erick G. Walton
IPC分类号： H01L23/525 , H01H85/00
CPC分类号： H01L23/5258 , H01L2924/0002
摘要： The fuse link includes a first and second interconnect, with interconnects each being substantially longer than deep. The interconnects are disposed toward each other with a insulator region between them. A fusible conductor, spanning the insulator region, is attached at the top of the interconnects. The present device allows the length of the fusible conductor to be shortened, and results in a fuse link that can be consistently blown with a single laser pulse. Additionally, the fuse link can be used in a staggered layout. The staggered layout of parallel fuse links allows a high number of links in a relatively small area, with or without the use of tungsten barriers, and allows accessing all fuse links through a single fuse blow window.
摘要翻译：熔丝连接件包括第一和第二互连件，其互连件基本上比深度长。互连通过它们之间的绝缘体区域彼此相对设置。跨越绝缘体区域的可熔导体连接在互连的顶部。本装置允许可熔导体的长度缩短，并且导致可以用单个激光脉冲一致地熔断的熔丝链。此外，熔丝链可以以交错的布局使用。平行熔丝链的交错布局允许在有或没有使用钨屏障的情况下，在相对较小的区域中有大量的连接，并且允许通过单个保险丝熔断窗口访问所有熔丝链。

4. 发明授权

US6054339A Fusible links formed on interconnects which are at least twice as long as they are deep 失效
标题翻译：在互连上形成的可熔链，至少是深度的两倍
公开(公告)号：US6054339A
公开(公告)日：2000-04-25
申请号：US810587
申请日：1997-03-04
申请人： Richard A. Gilmour , Ronald R. Uttecht , Erick G. Walton
发明人： Richard A. Gilmour , Ronald R. Uttecht , Erick G. Walton
IPC分类号： H01L23/525 , H01L21/82
CPC分类号： H01L23/5258 , H01L2924/0002
摘要： A shortened fuse link is disclosed. The fuse link comprises a first and second interconnect, with interconnects each being substantially longer than deep. The interconnects are disposed toward each other with a insulator region between them. A fusible conductor, spanning the insulator region, is attached at the top of the interconnects. The present device allows the length of the fusible conductor to be shortened, and results in a fuse link that can be consistently blown with a single laser pulse. Additionally, the fuse link can be used in a staggered layout. The staggered layout of parallel fuse links allows a high number of links in a relatively small area, with or without the use of tungsten barriers, and allows accessing all fuse links through a single fuse blow window.
摘要翻译：公开了一种缩短的熔断体。熔丝连接件包括第一和第二互连件，每个互连件基本上比深度长。互连通过它们之间的绝缘体区域彼此相对设置。跨越绝缘体区域的可熔导体连接在互连的顶部。本装置允许可熔导体的长度缩短，并且导致可以用单个激光脉冲一致地熔断的熔丝链。此外，熔丝链可以以交错的布局使用。平行熔丝链的交错布局允许在有或没有使用钨屏障的情况下，在相对较小的区域中有大量的连接，并且允许通过单个保险丝熔断窗口访问所有熔丝链。

5. 发明授权

US4981530A Planarizing ladder-type silsesquioxane polymer insulation layer 失效
标题翻译：平面化阶梯型倍半硅氧烷聚合物绝缘层
公开(公告)号：US4981530A
公开(公告)日：1991-01-01
申请号：US276597
申请日：1988-11-28
申请人： Donna J. Clodgo , Rosemary A. Previti-Kelly , Ronald R. Uttecht , Erick G. Walton
发明人： Donna J. Clodgo , Rosemary A. Previti-Kelly , Ronald R. Uttecht , Erick G. Walton
IPC分类号： H01B3/46 , C08G77/06 , C08G77/26 , C08G77/28 , C09D183/04 , H01L21/312 , H01L23/29
CPC分类号： H01L21/02126 , H01L21/02216 , H01L21/02282 , H01L21/3121 , H01L21/3122 , H01L23/293 , H01L2924/0002
摘要： An improved insulation layer is formed by first preparing a solution by reacting water with an aminoalkoxysilane monomer in a solvent, using a critical mole ratio of water/monomer. After a sufficient aging period, the solution is coated onto a suitable surface, e.g. the surface of a semiconductor device, and then cured, in an essentially oxygen-free atmosphere, to a ladder-type silsesquioxane polymer. The insulation layer demonstrates excellent planarizing characteristics, while also exhibiting enhanced crack-resistance.

6. 发明授权

US5286572A Planarizing ladder-type silsequioxane polymer insulation layer 失效
标题翻译：平面化梯形硅氧烷聚合物绝缘层
公开(公告)号：US5286572A
公开(公告)日：1994-02-15
申请号：US924414
申请日：1992-07-30
申请人： Donna J. Clodgo , Rosemary A. Previti-Kelly , Ronald R. Uttecht , Erick G. Walton
发明人： Donna J. Clodgo , Rosemary A. Previti-Kelly , Ronald R. Uttecht , Erick G. Walton
IPC分类号： H01L21/312 , H01L23/29 , B32B9/04
CPC分类号： H01L21/02126 , H01L21/02216 , H01L21/02282 , H01L21/3121 , H01L21/3122 , H01L23/293 , H01L2924/0002 , Y10T428/31612 , Y10T428/31663
摘要： An improved insulation layer is formed by first preparing a solution by reacting water with an aminoalkoxysilane monomer in a solvent, using a critical mole ratio of water/monomer. After a sufficient aging period, the solution is coated onto a suitable surface, e.g. the surface of a semiconductor device, and then cured, in an essentially oxygen-free atmosphere, to a ladder-type silsesquioxane polymer. The insulation layer demonstrates excellent planarizing characteristics, while also exhibiting enhanced crack-resistance.
摘要翻译：通过使用水/单体的临界摩尔比，首先通过使水与氨基烷氧基硅烷单体在溶剂中反应来制备溶液来形成改进的绝缘层。在足够的老化时间之后，将溶液涂覆到合适的表面上，例如半导体器件的表面，然后在基本上无氧的气氛中固化到梯型倍半硅氧烷聚合物。绝缘层表现出优异的平坦化特性，同时表现出增强的抗裂性。

7. 发明授权

US07207096B2 Method of manufacturing high performance copper inductors with bond pads 有权
标题翻译：制造具有接合焊盘的高性能铜电感器的方法
公开(公告)号：US07207096B2
公开(公告)日：2007-04-24
申请号：US10707896
申请日：2004-01-22
申请人： Jeffrey P. Gambino , William T. Motsiff , Erick G. Walton
发明人： Jeffrey P. Gambino , William T. Motsiff , Erick G. Walton
IPC分类号： H01F7/127 , H01L21/44
CPC分类号： H01L28/10 , H01F41/041 , H01L21/76852 , H01L21/76885 , H01L23/3192 , H01L23/5227 , H01L23/53238 , H01L24/02 , H01L2224/0401 , H01L2224/13022 , H01L2224/13147 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01044 , H01L2924/0105 , H01L2924/01055 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , Y10T29/4902 , Y10T29/49155 , Y10T29/49165 , H01L2924/00
摘要： A method for manufacturing high performance copper inductors includes providing a tall, Cu laminate spiral inductor is formed at the last metal level, and at the last metal +1 level, with the metal levels being interconnected by a bar via having the same spiral shape as the spiral metal inductors at the last metal level and the last metal +1 level. The method includes integrating the formation of thick inductors with the formation of bond pads, terminals and interconnect wiring with the last metal +1 wiring. Included are dielectric deposition and spacer formation steps, and/or selective deposition of a passivating metal such as CoWP, to passivate a Cu inductor that is formed after the last metal layer.
摘要翻译：一种用于制造高性能铜电感器的方法包括提供在最后的金属层面上形成的高Cu层压螺旋电感器，并且在最后的金属+1级别处，金属层通过棒与第二金属层相互螺旋形形成最后一个金属级螺旋金属电感和最后一个金属+1电平。该方法包括将厚电感器的形成与最后的金属+1布线形成接合焊盘，端子和互连布线。包括介电沉积和间隔物形成步骤，和/或钝化金属如CoWP的选择性沉积，以钝化在最后一个金属层之后形成的Cu电感器。

8. 发明授权

US06471845B1 Method of controlling chemical bath composition in a manufacturing environment 有权
标题翻译：在制造环境中控制化学浴组成的方法
公开(公告)号：US06471845B1
公开(公告)日：2002-10-29
申请号：US09461849
申请日：1999-12-15
申请人： John O. Dukovic , William E. Corbin, Jr. , Erick G. Walton , Peter S. Locke , Panayotis C. Andricacos , James E. Fluegel , Evan Patton , Jonathan Reid
发明人： John O. Dukovic , William E. Corbin, Jr. , Erick G. Walton , Peter S. Locke , Panayotis C. Andricacos , James E. Fluegel , Evan Patton , Jonathan Reid
IPC分类号： C25D2112
CPC分类号： C25D21/12 , Y10T137/2509
摘要： A method for controlling the composition of a chemical bath in which predictive dosing is used to account for changes in the composition of the bath in which the operating characteristics of the process are partitioned into a plurality of operating modes and the consumption or generation of materials related to the process are determined empirically and additions of material are made as appropriate.
摘要翻译：用于控制化学浴的组成的方法，其中使用预测剂量来解释浴的组成的变化，其中过程的操作特性被划分为多种操作模式以及相关材料的消耗或产生根据经验确定该过程，并酌情添加材料。

9. 发明申请

US20100051474A1 METHOD AND COMPOSITION FOR ELECTRO-CHEMICAL-MECHANICAL POLISHING 审中-公开
标题翻译：电化学机械抛光方法与组合
公开(公告)号：US20100051474A1
公开(公告)日：2010-03-04
申请号：US12548893
申请日：2009-08-27
申请人： Panayotis C. Andricacos , Caliopi Andricacos , Donald F. Canaperi , Emanuel I. Cooper , John M. Cotte , Hariklia Deligianni , Laertis Economikos , Daniel C. Edelstein , Silvia Franz , Balasubramanian Pranatharthiharan , Mahadevaiyer Krishnan , Andrew P. Mansson , Erick G. Walton , Alan C. West
发明人： Panayotis C. Andricacos , Caliopi Andricacos , Donald F. Canaperi , Emanuel I. Cooper , John M. Cotte , Hariklia Deligianni , Laertis Economikos , Daniel C. Edelstein , Silvia Franz , Balasubramanian Pranatharthiharan , Mahadevaiyer Krishnan , Andrew P. Mansson , Erick G. Walton , Alan C. West
IPC分类号： B23H5/06
CPC分类号： C25F3/02 , B23H5/08 , C09G1/04 , H01L21/32125
摘要： Methods and compositions for electro-chemical-mechanical polishing (e-CMP) of silicon chip interconnect materials, such as copper, are provided. The methods include the use of compositions according to the invention in combination with pads having various configurations.
摘要翻译：提供了诸如铜之类的硅芯片互连材料的电化学机械抛光（e-CMP）的方法和组合物。所述方法包括使用根据本发明的组合物与具有各种构型的垫组合。

10. 发明授权

US07015580B2 Roughened bonding pad and bonding wire surfaces for low pressure wire bonding 有权
标题翻译：用于低压引线接合的粗化焊盘和接合线表面
公开(公告)号：US07015580B2
公开(公告)日：2006-03-21
申请号：US10722704
申请日：2003-11-25
申请人： John A. Fitzsimmons , Jeffrey P. Gambino , Erick G. Walton
发明人： John A. Fitzsimmons , Jeffrey P. Gambino , Erick G. Walton
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/85 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05073 , H01L2224/05166 , H01L2224/05187 , H01L2224/05556 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4807 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2224/48824 , H01L2224/48844 , H01L2224/48847 , H01L2224/85203 , H01L2224/85205 , H01L2224/85345 , H01L2224/85365 , H01L2224/85385 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/04953 , H01L2924/14 , H01L2924/00014 , H01L2924/04941 , H01L2924/00 , H01L2224/48744 , H01L2924/00015
摘要： An intermediate semiconductor structure and method for low-pressure wire bonding that reduces the propensity of dielectric material to mechanical failure due to any wire bonding stresses. Roughened surfaces such as metal pillars or metal dendrites are provided on a bonding pad, bonding wire or both. These roughened surfaces increase reactivity between the bond wire and the bond pad to form strong bonds. This increased activity as a result of the roughened bonding pad and/or wire surfaces reduce the amount of pressure, temperature and energy required for wire bonding, which in turn, avoids damage to the bonding pad as well as the semiconductor substrate.
摘要翻译：用于低压引线接合的中间半导体结构和方法，其降低由于任何引线键合应力引起的介电材料对机械故障的倾向。在焊盘，接合线或两者上设置诸如金属柱或金属枝晶的粗化表面。这些粗糙表面增加了接合线和接合焊盘之间的反应性，以形成强键。由于粗糙的焊盘和/或线表面的结果，这种增加的活性减少了引线接合所需的压力，温度和能量的量，这进而避免了对焊盘以及半导体衬底的损坏。

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