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1. 发明授权

US07279997B2 Voltage controlled oscillator with a multiple gate transistor and method therefor 有权
公开(公告)号：US07279997B2
公开(公告)日：2007-10-09
申请号：US11250994
申请日：2005-10-14
申请人： Sriram S. Kalpat , Leo Mathew , Mohamed S. Moosa , Michael A. Sadd , Hector Sanchez
发明人： Sriram S. Kalpat , Leo Mathew , Mohamed S. Moosa , Michael A. Sadd , Hector Sanchez
IPC分类号： H03L7/099
CPC分类号： H01L27/1211 , H01L29/66795 , H01L29/785 , H03K5/133 , H03K2005/00026 , H03K2005/00058 , H03L7/0995
摘要： A voltage controlled oscillator (VCO) has a plurality of series-connected inverters. Within each inverter a first transistor has a first current electrode coupled to a first power supply voltage terminal, a second current electrode, a first control electrode coupled to an output terminal of another inverter of the plurality of series-connected inverters, and a second control electrode for receiving a first bias signal. A second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to a second power supply voltage terminal, and a first control electrode coupled to the first control electrode of the first transistor. The second control electrode of the first transistor of each inverter receives a same or separate analog control signal to adjust the threshold voltage of the first transistors thereof to affect frequency and phase of the VCO's signal.

2. 发明申请

US20120241909A1 Low-Leakage, High-Capacitance Capacitor Structures and Method of Making 有权
标题翻译：低泄漏，高电容电容器结构及制作方法
公开(公告)号：US20120241909A1
公开(公告)日：2012-09-27
申请号：US13070049
申请日：2011-03-23
申请人： Tushar P. Merchant , Michael A. Sadd
发明人： Tushar P. Merchant , Michael A. Sadd
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/92 , H01L29/94
摘要： A process and device structure is provided for increasing capacitance density of a capacitor structure. A sandwich capacitor is provided in which a bottom silicon-containing conductor plate is formed with holes or cavities, upon which an oxide layer and a top silicon-containing layer conductor is formed. The holes or cavities provide additional capacitive area, thereby increasing capacitance per footprint area of the capacitor structure. The holes can form, for example, a line structure or a waffle-like structure in the bottom conductor plate. Etching techniques used to form the holes in the bottom conductor plate can also result in side wall tapering of the holes, thereby increasing the surface area of the silicon-containing layer defined by the holes. In addition, depth of holes can be adjusted through timed etching to further adjust capacitive area.
摘要翻译：提供了一种用于增加电容器结构的电容密度的工艺和器件结构。提供一种夹层电容器，其中底部含硅导电板形成有孔或空腔，在其上形成氧化物层和顶部含硅层导体。孔或腔提供附加的电容区域，从而增加电容器结构的每个覆盖区域的电容。孔可以形成例如底部导体板中的线结构或华夫饼状结构。用于在底部导体板中形成孔的蚀刻技术还可导致孔的侧壁渐缩，从而增加由孔限定的含硅层的表面积。此外，可以通过定时蚀刻来调整孔的深度，以进一步调整电容面积。

3. 发明授权

US07800164B2 Nanocrystal non-volatile memory cell and method therefor 有权
标题翻译：纳米晶体非挥发性记忆体及其方法
公开(公告)号：US07800164B2
公开(公告)日：2010-09-21
申请号：US12397849
申请日：2009-03-04
申请人： Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Bruce E. White
发明人： Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Bruce E. White
IPC分类号： H01L29/792
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/28273 , H01L29/513 , H01L29/7881 , Y10S977/773
摘要： A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.
摘要翻译：一种形成半导体器件的方法包括在半导体衬底上形成第一电介质层，在第一介电层上形成多个离散存储元件，热氧化多个离散的存储元件，以在多个离散存储器上形成第二电介质元件，并且在所述第二介电层上形成栅电极，其中所述栅电极的重要部分位于所述多个离散存储元件的对之间。在一个实施例中，栅电极的部分位于离散存储元件之间的空间中并且延伸到空间深度的一半以上。

4. 发明授权

US07456465B2 Split gate memory cell and method therefor 有权
标题翻译：分闸存储单元及其方法
公开(公告)号：US07456465B2
公开(公告)日：2008-11-25
申请号：US11240240
申请日：2005-09-30
申请人： Erwin J. Prinz , Michael A. Sadd , Robert F. Steimle
发明人： Erwin J. Prinz , Michael A. Sadd , Robert F. Steimle
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , B82Y10/00 , H01L29/42328 , H01L29/42332
摘要： A split gate memory cell has a select gate, a control gate, and a charge storage structure. The select gate includes a first portion located over the control gate and a second portion not located over the control gate. In one example, the first portion of the select gate has a sidewall aligned with a sidewall of the control gate and aligned with a sidewall of the charge storage structure. In one example, the control gate has a p-type conductivity. In one example, the gate can be programmed by a hot carrier injection operation and can be erased by a tunneling operation.
摘要翻译：分离栅极存储单元具有选择栅极，控制栅极和电荷存储结构。选择栅极包括位于控制栅极上方的第一部分和不位于控制栅极上方的第二部分。在一个示例中，选择栅极的第一部分具有与控制栅极的侧壁对齐并与电荷存储结构的侧壁对准的侧壁。在一个示例中，控制栅极具有p型导电性。在一个示例中，门可以通过热载流子注入操作来编程，并且可以通过隧道操作来擦除。

5. 发明申请

US20090042349A1 SPLIT GATE MEMORY CELL AND METHOD THEREFOR 有权
标题翻译：分离栅格存储单元及其方法
公开(公告)号：US20090042349A1
公开(公告)日：2009-02-12
申请号：US12254294
申请日：2008-10-20
申请人： Erwin J. Prinz , Michael A. Sadd , Robert F. Steimle
发明人： Erwin J. Prinz , Michael A. Sadd , Robert F. Steimle
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , H01L29/42328 , H01L29/42332
摘要： A split gate memory cell has a select gate, a control gate, and a charge storage structure. The select gate includes a first portion located over the control gate and a second portion not located over the control gate. In one example, the first portion of the select gate has a sidewall aligned with a sidewall of the control gate and aligned with a sidewall of the charge storage structure. In one example, the control gate has a p-type conductivity. In one example, the gate can be programmed by a hot carrier injection operation and can be erased by a tunneling operation.
摘要翻译：分离栅极存储单元具有选择栅极，控制栅极和电荷存储结构。选择栅极包括位于控制栅极上方的第一部分和不位于控制栅极上方的第二部分。在一个示例中，选择栅极的第一部分具有与控制栅极的侧壁对齐并与电荷存储结构的侧壁对准的侧壁。在一个示例中，控制栅极具有p型导电性。在一个示例中，门可以通过热载流子注入操作来编程，并且可以通过隧道操作来擦除。

6. 发明授权

US06847548B2 Memory with multiple state cells and sensing method 有权
标题翻译：具有多状态单元和感测方式的存储器
公开(公告)号：US06847548B2
公开(公告)日：2005-01-25
申请号：US10601256
申请日：2003-06-20
申请人： Craig T. Swift , Michael A. Sadd
发明人： Craig T. Swift , Michael A. Sadd
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0491 , G11C16/0475
摘要： A memory has an array made up of transistors that have two charge storage regions between the channel and control gate. Each bit is made up of two charge storage regions that are from different transistors. A bit is written by first erasing all of the storage locations and then writing one of the charge storage locations that make up the bit. A pair of charge storage locations, one erased and the other programmed, is identified for each bit. The logic state of the bit is read by comparing the charge stored in the two charge storage locations that make up the bit. This comparison is achieved by generating signals representative of the charge present in the two charge storage locations. These signals are then coupled to a sense amplifier that functions as a comparator. This avoids many problems that accompany comparisons to a fixed reference.
摘要翻译：存储器具有由在通道和控制栅极之间具有两个电荷存储区域的晶体管组成的阵列。每个位由来自不同晶体管的两个电荷存储区组成。首先擦除所有存储位置，然后写入构成该位的电荷存储位置之一，写入一位。每一位识别一对电荷存储单元，一个被擦除，另一个编程。通过比较存储在构成该位的两个电荷存储位置中的电荷来读取该位的逻辑状态。该比较通过产生表示两个电荷存储位置中存在的电荷的信号来实现。这些信号然后被耦合到用作比较器的读出放大器。这避免了许多与固定参考比较的问题。

7. 发明授权

US07517747B2 Nanocrystal non-volatile memory cell and method therefor 有权
标题翻译：纳米晶体非挥发性记忆体及其方法
公开(公告)号：US07517747B2
公开(公告)日：2009-04-14
申请号：US11530053
申请日：2006-09-08
申请人： Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Bruce E. White
发明人： Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Bruce E. White
IPC分类号： H01L21/8238
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/28273 , H01L29/513 , H01L29/7881 , Y10S977/773
摘要： A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.
摘要翻译：一种形成半导体器件的方法包括在半导体衬底上形成第一电介质层，在第一介电层上形成多个离散存储元件，热氧化多个离散的存储元件，以在多个离散存储器上形成第二电介质元件，并且在所述第二介电层上形成栅电极，其中所述栅电极的重要部分位于所述多个离散存储元件的对之间。在一个实施例中，栅电极的部分位于离散存储元件之间的空间中并且延伸到空间深度的一半以上。

8. 发明申请

US20080121967A1 NANOCRYSTAL NON-VOLATILE MEMORY CELL AND METHOD THEREFOR 审中-公开
标题翻译： NANOCRYSTAL非易失性记忆细胞及其方法
公开(公告)号：US20080121967A1
公开(公告)日：2008-05-29
申请号：US11530054
申请日：2006-09-08
申请人： Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Bruce E. White
发明人： Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Bruce E. White
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L29/42332 , B82Y10/00 , H01L29/40114 , H01L29/513 , H01L29/7881
摘要： A method of forming a semiconductor device, which is preferably a memory cell, includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, wherein each of the plurality of discrete storage elements has a diameter value that is approximately equal to each other, and forming a second dielectric layer over the plurality of discrete storage elements, wherein the second dielectric layer has a thickness, wherein the ratio of the thickness of the second dielectric to the diameter value is less than approximately 0.8. The spacing between the plurality of discrete storage elements may be greater than or equal to approximately the thickness of the second dielectric layer.
摘要翻译：形成半导体器件的方法，其优选地是存储单元，包括在半导体衬底上形成第一介电层，在第一介电层上形成多个离散存储元件，其中多个离散存储元件中的每一个具有并且在所述多个分立存储元件上形成第二电介质层，其中所述第二电介质层具有厚度，其中所述第二电介质的厚度与所述直径值的比值小于约0.8。多个离散存储元件之间的间隔可以大于或等于第二电介质层的厚度。

9. 发明授权

US07160775B2 Method of discharging a semiconductor device 有权
标题翻译：放电半导体器件的方法
公开(公告)号：US07160775B2
公开(公告)日：2007-01-09
申请号：US10912825
申请日：2004-08-06
申请人： Erwin J. Prinz , Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Robert F. Steimle , Craig T. Swift , Bruce E. White
发明人： Erwin J. Prinz , Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Robert F. Steimle , Craig T. Swift , Bruce E. White
IPC分类号： H01L21/336
CPC分类号： B82Y10/00 , G11C16/0475 , G11C16/14 , G11C2216/06 , H01L21/28273 , H01L21/28282 , H01L29/42332
摘要： In one embodiment, a method for discharging a semiconductor device includes providing a semiconductor substrate, forming a hole blocking dielectric layer over the semiconductor substrate, forming nanoclusters over the hole blocking dielectric layer, forming a charge trapping layer over the nanoclusters, and applying an electric field to the nanoclusters to discharge the semiconductor device. Applying the electric field may occur while applying ultraviolet (UV) light. In one embodiment, the hole blocking dielectric layer comprises forming the hole blocking dielectric layer having a thickness greater than approximately 50 Angstroms.
摘要翻译：在一个实施例中，一种用于放电半导体器件的方法包括提供半导体衬底，在半导体衬底上形成空穴阻挡电介质层，在空穴阻挡介电层上形成纳米团簇，在纳米团簇上形成电荷俘获层，并施加电场到纳米团簇放电半导体器件。施加紫外线（UV）光时可能会发生电场。在一个实施例中，空穴阻挡介电层包括形成厚度大于约50埃的空穴阻挡介电层。

10. 发明授权

US06413819B1 Memory device and method for using prefabricated isolated storage elements 有权
标题翻译：使用预制隔离存储元件的存储器件和方法
公开(公告)号：US06413819B1
公开(公告)日：2002-07-02
申请号：US09595821
申请日：2000-06-16
申请人： Sufi Zafar , Ramachandran Muralidhar , Bich-Yen Nguyen , Sucharita Madhukar , Daniel T. Pham , Michael A. Sadd , Chitra K. Subramanian
发明人： Sufi Zafar , Ramachandran Muralidhar , Bich-Yen Nguyen , Sucharita Madhukar , Daniel T. Pham , Michael A. Sadd , Chitra K. Subramanian
IPC分类号： H01L21336
CPC分类号： B82Y10/00 , H01L21/28273 , H01L29/7883 , H01L29/7888
摘要： A semiconductor device that includes a floating gate made up of a plurality of pre-formed isolated storage elements (18) and a method for making such a device is presented. The device is formed by first providing a semiconductor layer (12) upon which a first gate insulator (14) is formed. A plurality of pre-fabricated isolated storage elements (18) is then deposited on the first gate insulator (14). This deposition step may be accomplished by immersion in a colloidal solution (16) that includes a solvent and pre-fabricated isolated storage elements (18). Once deposited, the solvent of the solution (16) can be removed, leaving the pre-fabricated isolated storage elements (18) deposited on the first gate insulator (14). After depositing the pre-fabricated isolated storage elements (18), a second gate insulator (20) is formed over the pre-fabricated isolated storage elements (18). A gate electrode (24) is then formed over the second gate insulator (20), and portions the first and second gate insulators and the plurality of pre-fabricated isolated storage elements that do not underlie the gate electrode are selectively removed. A source region (32) and a drain region (34) are then formed in the semiconductor layer (12) such that a channel region is formed between underlying the gate electrode (24).
摘要翻译：提供了一种半导体器件，其包括由多个预先形成的隔离存储元件（18）构成的浮动栅极和用于制造这种器件的方法。该器件通过首先提供形成第一栅极绝缘体（14）的半导体层（12）形成。然后，多个预制隔离存储元件（18）沉积在第一栅极绝缘体（14）上。该沉积步骤可以通过浸入包括溶剂和预制隔离存储元件（18）的胶体溶液（16）中来实现。一旦沉积，可以除去溶液（16）的溶剂，留下沉积在第一栅极绝缘体（14）上的预制隔离存储元件（18）。在沉积预制隔离存储元件（18）之后，在预制隔离存储元件（18）上形成第二栅极绝缘体（20）。然后，在第二栅极绝缘体（20）之上形成栅电极（24），并且选择性地去除不在栅电极下面的第一和第二栅极绝缘体和多个预制隔离存储元件的部分。然后在半导体层（12）中形成源极区（32）和漏极区（34），使得在栅电极（24）下方形成沟道区。

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