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1. 发明申请

US20120241909A1 Low-Leakage, High-Capacitance Capacitor Structures and Method of Making 有权
标题翻译：低泄漏，高电容电容器结构及制作方法
公开(公告)号：US20120241909A1
公开(公告)日：2012-09-27
申请号：US13070049
申请日：2011-03-23
申请人： Tushar P. Merchant , Michael A. Sadd
发明人： Tushar P. Merchant , Michael A. Sadd
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/92 , H01L29/94
摘要： A process and device structure is provided for increasing capacitance density of a capacitor structure. A sandwich capacitor is provided in which a bottom silicon-containing conductor plate is formed with holes or cavities, upon which an oxide layer and a top silicon-containing layer conductor is formed. The holes or cavities provide additional capacitive area, thereby increasing capacitance per footprint area of the capacitor structure. The holes can form, for example, a line structure or a waffle-like structure in the bottom conductor plate. Etching techniques used to form the holes in the bottom conductor plate can also result in side wall tapering of the holes, thereby increasing the surface area of the silicon-containing layer defined by the holes. In addition, depth of holes can be adjusted through timed etching to further adjust capacitive area.
摘要翻译：提供了一种用于增加电容器结构的电容密度的工艺和器件结构。提供一种夹层电容器，其中底部含硅导电板形成有孔或空腔，在其上形成氧化物层和顶部含硅层导体。孔或腔提供附加的电容区域，从而增加电容器结构的每个覆盖区域的电容。孔可以形成例如底部导体板中的线结构或华夫饼状结构。用于在底部导体板中形成孔的蚀刻技术还可导致孔的侧壁渐缩，从而增加由孔限定的含硅层的表面积。此外，可以通过定时蚀刻来调整孔的深度，以进一步调整电容面积。

2. 发明授权

US08097873B2 Phase change memory structures 有权
标题翻译：相变记忆结构
公开(公告)号：US08097873B2
公开(公告)日：2012-01-17
申请号：US12881678
申请日：2010-09-14
申请人： Ramachandran Muralidhar , Tushar P. Merchant , Rajesh A. Rao
发明人： Ramachandran Muralidhar , Tushar P. Merchant , Rajesh A. Rao
IPC分类号： H01L29/04 , H01L45/00
CPC分类号： H01L45/1233 , H01L45/06 , H01L45/126 , H01L45/1273 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675
摘要： A phase change memory cell has a first electrode, a plurality of pillars, and a second electrode. The plurality of pillars are electrically coupled with the first electrode. Each of the pillars comprises a phase change material portion and a heater material portion. The second electrode is electrically coupled to each of the pillars. In some examples, the pillars have a width less than 20 nanometers.
摘要翻译：相变存储单元具有第一电极，多个柱和第二电极。多个柱与第一电极电耦合。每个支柱包括相变材料部分和加热器材料部分。第二电极电耦合到每个支柱。在一些示例中，支柱具有小于20纳米的宽度。

3. 发明申请

US20090184309A1 PHASE CHANGE MEMORY CELL WITH HEATER AND METHOD THEREFOR 有权
标题翻译：相变存储器与加热器及其方法
公开(公告)号：US20090184309A1
公开(公告)日：2009-07-23
申请号：US12016733
申请日：2008-01-18
申请人： Leo Mathew , Dharmesh Jawarani , Tushar P. Merchant , Ramachandran Muralidhar
发明人： Leo Mathew , Dharmesh Jawarani , Tushar P. Merchant , Ramachandran Muralidhar
IPC分类号： H01L45/00
CPC分类号： H01L45/1675 , G11C13/0004 , H01L27/2436 , H01L45/06 , H01L45/1226 , H01L45/126 , H01L45/144
摘要： A method for forming a phase change memory cell (PCM) includes forming a heater for the phase change memory and forming a phase change structrure electrically coupled to the heater. The forming a heater includes siliciding a material including silicon to form a silicide structure, wherein the heater includes at least a portion of the silicide structure. The phase change structure exhibits a first resistive value when in a first phase state and exhibits a second resistive value when in a second phase state. The silicide structure produces heat when current flows through the silicide structure for changing the phase state of the phase change structure.
摘要翻译：形成相变存储单元（PCM）的方法包括形成用于相变存储器的加热器，并形成电耦合到加热器的相变结构。形成加热器包括将包括硅的材料硅化以形成硅化物结构，其中加热器包括至少一部分硅化物结构。当处于第一相位状态时，相变结构呈现第一电阻值，并且当处于第二相位状态时呈现第二电阻值。当电流流过硅化物结构以改变相变结构的相位状态时，硅化物结构产生热量。

4. 发明申请

US20070202645A1 METHOD FOR FORMING A DEPOSITED OXIDE LAYER 审中-公开
标题翻译：形成沉积氧化层的方法
公开(公告)号：US20070202645A1
公开(公告)日：2007-08-30
申请号：US11680121
申请日：2007-02-28
申请人： Tien Ying Luo , Lakshmanna Vishnubhotla , Tushar P. Merchant , Rajesh A. Rao , Ramachandran Muralidhar
发明人： Tien Ying Luo , Lakshmanna Vishnubhotla , Tushar P. Merchant , Rajesh A. Rao , Ramachandran Muralidhar
IPC分类号： H01L21/8242
CPC分类号： H01L29/7885 , B82Y10/00 , H01L21/02164 , H01L21/02271 , H01L21/02304 , H01L21/02337 , H01L21/31612 , H01L29/40117 , H01L29/42332 , H01L29/7883
摘要： An oxide layer formed by deposition is subject to a treatment process to repair bond defects of the oxide layer. In one embodiment, the layer is treated with nitric oxide. In one embodiment, a nitric oxide gas is flowed over the dielectric layer at an elevated temperature. In still another embodiment, the oxide layer is treated with fluorine. A layer is deposited over the oxide layer and a species containing fluorine is ion implanted into the layer. The wafer is heated where the species is driven to the oxide layer.
摘要翻译：通过沉积形成的氧化物层经受处理工艺以修复氧化物层的结合缺陷。在一个实施方案中，该层用一氧化氮处理。在一个实施方案中，一氧化氮气体在升高的温度下流过电介质层。在另一个实施方案中，用氟处理氧化物层。在氧化物层上沉积一层，并且将含氟物质离子注入到该层中。加热晶片，将物质驱动到氧化物层。

5. 发明授权

US09112060B2 Low-leakage, high-capacitance capacitor structures and method of making 有权
标题翻译：低泄漏，大电容电容器结构及制造方法
公开(公告)号：US09112060B2
公开(公告)日：2015-08-18
申请号：US13070049
申请日：2011-03-23
申请人： Tushar P. Merchant , Michael A. Sadd
发明人： Tushar P. Merchant , Michael A. Sadd
IPC分类号： H01L21/02 , H01L49/02 , H01L29/94
CPC分类号： H01L28/92 , H01L29/94
摘要： A process and device structure is provided for increasing capacitance density of a capacitor structure. A sandwich capacitor is provided in which a bottom silicon-containing conductor plate is formed with holes or cavities, upon which an oxide layer and a top silicon-containing layer conductor is formed. The holes or cavities provide additional capacitive area, thereby increasing capacitance per footprint area of the capacitor structure. The holes can form, for example, a line structure or a waffle-like structure in the bottom conductor plate. Etching techniques used to form the holes in the bottom conductor plate can also result in side wall tapering of the holes, thereby increasing the surface area of the silicon-containing layer defined by the holes. In addition, depth of holes can be adjusted through timed etching to further adjust capacitive area.
摘要翻译：提供了一种用于增加电容器结构的电容密度的工艺和器件结构。提供一种夹层电容器，其中底部含硅导电板形成有孔或空腔，在其上形成氧化物层和顶部含硅层导体。孔或腔提供附加的电容区域，从而增加电容器结构的每个覆盖区域的电容。孔可以形成例如底部导体板中的线结构或华夫饼状结构。用于在底部导体板中形成孔的蚀刻技术还可导致孔的侧壁渐缩，从而增加由孔限定的含硅层的表面积。此外，可以通过定时蚀刻来调整孔的深度，以进一步调整电容面积。

6. 发明授权

US08575588B2 Phase change memory cell with heater and method therefor 有权
标题翻译：具有加热器的相变存储器单元及其方法
公开(公告)号：US08575588B2
公开(公告)日：2013-11-05
申请号：US13238791
申请日：2011-09-21
申请人： Leo Mathew , Dharmesh Jawarani , Tushar P. Merchant , Ramachandran Muralidhar
发明人： Leo Mathew , Dharmesh Jawarani , Tushar P. Merchant , Ramachandran Muralidhar
IPC分类号： H01L45/00
CPC分类号： H01L45/1675 , G11C13/0004 , H01L27/2436 , H01L45/06 , H01L45/1226 , H01L45/126 , H01L45/144
摘要： A method for forming a phase change memory cell (PCM) includes forming a heater for the phase change memory and forming a phase change structrure electrically coupled to the heater. The forming a heater includes siliciding a material including silicon to form a silicide structure, wherein the heater includes at least a portion of the silicide structure. The phase change structure exhibits a first resistive value when in a first phase state and exhibits a second resistive value when in a second phase state. The silicide structure produces heat when current flows through the silicide structure for changing the phase state of the phase change structure.
摘要翻译：形成相变存储单元（PCM）的方法包括形成用于相变存储器的加热器，并形成电耦合到加热器的相变结构。形成加热器包括将包括硅的材料硅化以形成硅化物结构，其中加热器包括至少一部分硅化物结构。当处于第一相位状态时，相变结构呈现第一电阻值，并且当处于第二相位状态时呈现第二电阻值。当电流流过硅化物结构以改变相变结构的相位状态时，硅化物结构产生热量。

7. 发明授权

US08168468B2 Method of making a semiconductor device including a bridgeable material 有权
标题翻译：制造包括可桥接材料的半导体器件的方法
公开(公告)号：US08168468B2
公开(公告)日：2012-05-01
申请号：US12039909
申请日：2008-02-29
申请人： Varughese Mathew , Sam S. Garcia , Tushar P. Merchant
发明人： Varughese Mathew , Sam S. Garcia , Tushar P. Merchant
IPC分类号： H01L21/00
CPC分类号： H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/1658 , H01L45/1683
摘要： A method for making a semiconductor device (10) includes providing an interconnect layer (14) over an underlying layer (12), forming a first insulating layer (16) over the interconnect layer, and forming an opening (18) through the insulating layer to the interconnect layer. A first conductive layer (24) is formed over the interconnect layer and in the opening. This is performed by plating so it is selective. A second conductive layer (28) in the opening is formed by displacement by immersion. This is performed after the first conductive layer has been formed. The result is the second conductive layer is formed by a selective deposition and is effective for providing it with bridging material. A layer of bridgeable material (34) is formed over the second conductive layer and in the opening. A third conductive layer (42) is formed over the bridgeable material. The semiconductor device may be useable as a conductive bridge memory device.
摘要翻译：制造半导体器件（10）的方法包括在下层（12）之上提供互连层（14），在所述互连层上形成第一绝缘层（16），以及通过绝缘层形成开口（18）到互连层。在互连层上和开口中形成第一导电层（24）。这是通过电镀进行的，所以它是选择性的。开口中的第二导电层（28）通过浸渍移位而形成。这是在形成第一导电层之后进行的。结果是通过选择性沉积形成第二导电层并且有效地为其提供桥接材料。在第二导电层上和开口中形成有可桥接材料层（34）。第三导电层（42）形成在可桥接材料上。半导体器件可以用作导电桥接器件。

8. 发明申请

US20100155825A1 TRANSISTOR DEVICES WITH NANO-CRYSTAL GATE STRUCTURES 有权
标题翻译：具有纳米晶体结构的晶体管器件
公开(公告)号：US20100155825A1
公开(公告)日：2010-06-24
申请号：US12715947
申请日：2010-03-02
申请人： Chun-Li Liu , Tushar P. Merchant , Marius K. Orlowski , Matthew W. Stoker
发明人： Chun-Li Liu , Tushar P. Merchant , Marius K. Orlowski , Matthew W. Stoker
IPC分类号： H01L29/792
CPC分类号： H01L29/7883 , B82Y10/00 , H01L21/28273 , H01L29/42332 , H01L29/513 , H01L29/66825 , H01L29/78
摘要： Embodiments of non-volatile semiconductor devices include a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure containing nano-crystals located above the channel region. The gate structure comprises a gate dielectric substantially in contact with the channel region, spaced-apart nano-crystals disposed in the gate dielectric, one or more impurity blocking layers overlying the gate dielectric, and a gate conductor layer overlying the one more impurity blocking layers. The blocking layer nearest the gate conductor can be used to adjust the threshold voltage of the device and/or retard dopant out-diffusion from the gate conductor layer.
摘要翻译：非易失性半导体器件的实施例包括其中具有源极区域和漏极区域的衬底，所述源极区域和漏极区域被延伸到衬底的第一表面的沟道区域分开，以及包含位于沟道区域上方的纳米晶体的多层栅极结构。栅极结构包括基本上与沟道区接触的栅极电介质，设置在栅极电介质中的间隔开的纳米晶体，覆盖栅极电介质的一个或多个杂质阻挡层，以及叠加在一个以上杂质阻挡层上的栅极导体层。可以使用最靠近栅极导体的阻挡层来调节器件的阈值电压和/或从栅极导体层延迟掺杂剂的扩散。

9. 发明授权

US07704830B2 Split gate memory cell using sidewall spacers 有权
标题翻译：使用侧壁间隔件的分离栅极存储单元
公开(公告)号：US07704830B2
公开(公告)日：2010-04-27
申请号：US11759518
申请日：2007-06-07
申请人： Rajesh A. Rao , Tushar P. Merchant , Ramachandran Muralidhar , Lakshmanna Vishnubhotla
发明人： Rajesh A. Rao , Tushar P. Merchant , Ramachandran Muralidhar , Lakshmanna Vishnubhotla
IPC分类号： H01L21/336
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/28273 , H01L29/42328 , H01L29/7881
摘要： A self-aligned split gate bitcell includes first and second regions of charge storage material separated by a gap devoid of charge storage material. Spacers are formed along sidewalls of sacrificial layer extending above and on opposite sides of the bitcell stack, wherein the spacers are separated from one another by at least a gap length. Etching the bitcell stack, selective to the spacers, forms a gap that splits the bitcell stack into first and second gates which together form the split gate bitcell stack. A storage portion of bitcell stack is also etched, wherein etching extends the gap and separates the corresponding layer into first and second separate regions, the extended gap being devoid of charge storage material. Dielectric material is deposited over the gap and etched back to expose a top surface of the sacrificial layer, which is thereafter removed to expose sidewalls of the split gate bitcell stack.
摘要翻译：自对准分离栅极位单元包括由没有电荷存储材料的间隙分开的电荷存储材料的第一和第二区域。间隔物形成在牺牲层的侧壁上，该牺牲层在位单元堆叠的上方和相对侧上延伸，其中间隔物彼此间隔至少间隙长度。刻蚀对间隔物有选择性的位单元堆叠形成了将位单元堆叠分成第一和第二栅极的间隙，这些栅极组共同构成了分离栅极位单元堆叠。比特单元堆叠的存储部分也被蚀刻，其中蚀刻延伸间隙并将相应的层分离成第一和第二分离区域，扩展间隙没有电荷存储材料。电介质材料沉积在间隙上并被回蚀以暴露牺牲层的顶表面，此牺牲层此后被去除以暴露分裂栅极位晶胞堆叠的侧壁。

10. 发明申请

US20090085023A1 PHASE CHANGE MEMORY STRUCTURES 有权
标题翻译：相变记忆结构
公开(公告)号：US20090085023A1
公开(公告)日：2009-04-02
申请号：US11864257
申请日：2007-09-28
申请人： Ramachandran Muralidhar , Tushar P. Merchant , Rajesh A. Rao
发明人： Ramachandran Muralidhar , Tushar P. Merchant , Rajesh A. Rao
IPC分类号： H01L45/00
CPC分类号： H01L45/1675 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1273 , H01L45/144 , H01L45/148
摘要： A phase change memory cell has a first electrode, a heater, a phase change material, and a second electrode. The heater is over the first electrode, and the heater comprises a pillar. The phase change material is around the heater. The second electrode is electrically coupled to the phase change material. In some embodiments, a method includes forming a electrode layer over a substrate, depositing a first layer, providing nanoclusters over the first layer, and etching the first layer. The first layer comprises one of a group consisting of a heater material and a phase change material. The first layer may be etched using the nanocluster defined pattern to form pillars from the first layer.
摘要翻译：相变存储单元具有第一电极，加热器，相变材料和第二电极。加热器在第一电极之上，并且加热器包括支柱。相变材料在加热器周围。第二电极电耦合到相变材料。在一些实施例中，一种方法包括在衬底上形成电极层，沉积第一层，在第一层上提供纳米团簇，以及蚀刻第一层。第一层包括由加热器材料和相变材料组成的组中的一个。可以使用纳米簇限定图案蚀刻第一层，以形成来自第一层的柱。

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