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1. 发明授权

US06847089B2 Gate edge diode leakage reduction 有权
标题翻译：栅极二极管漏电减少
公开(公告)号：US06847089B2
公开(公告)日：2005-01-25
申请号：US10407128
申请日：2003-04-03
申请人： Srinivasan Chakravarthi , Suresh Potla , Gordon P. Pollack , Amitabh Jain
发明人： Srinivasan Chakravarthi , Suresh Potla , Gordon P. Pollack , Amitabh Jain
IPC分类号： H01L21/265 , H01L21/336 , H01L29/10 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L29/1083 , H01L29/6656
摘要： An embodiment of the invention is an integrated circuit 2 having halo atoms 12 concentrated at a gate side of a channel region and impurity atoms 14 within the channel region. Another embodiment of the invention is a method of manufacturing an integrated circuit that includes the implantation of impurity atoms 14 into a semiconductor substrate 11.
摘要翻译：本发明的一个实施例是集成电路2，其具有集中在沟道区的栅极侧的光子原子12和沟道区内的杂质原子14。本发明的另一实施例是一种制造集成电路的方法，该集成电路包括将杂质原子14注入到半导体衬底11中。

2. 发明申请

US20080308904A1 P-DOPED REGION WITH IMPROVED ABRUPTNESS 审中-公开
标题翻译：具有改善性破坏的P区域
公开(公告)号：US20080308904A1
公开(公告)日：2008-12-18
申请号：US11763497
申请日：2007-06-15
申请人： P. R. Chidambaram , Srinivasan Chakravarthi , Mahalingam Nandakumar , Manoj Mehrotra , Amitabh Jain , Thomas D. Bonifield
发明人： P. R. Chidambaram , Srinivasan Chakravarthi , Mahalingam Nandakumar , Manoj Mehrotra , Amitabh Jain , Thomas D. Bonifield
IPC分类号： H01L21/425 , H01L29/36
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/268 , H01L21/324 , H01L21/823814 , H01L29/165 , H01L29/66068 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： A method of manufacturing a semiconductor device. The method comprises providing C atoms in a semiconductor substrate. The method also comprises implanting In atoms and p-type dopants into a predefined region of the substrate that is configured to have the carbon atoms. The method further comprises thermally annealing the semiconductor substrate to transform the predefined region into an activated doped region.
摘要翻译：一种制造半导体器件的方法。该方法包括在半导体衬底中提供C原子。该方法还包括将In原子和p型掺杂剂注入被配置为具有碳原子的衬底的预定区域中。该方法还包括对半导体衬底进行热退火以将预定区域转变为激活的掺杂区域。

3. 发明申请

US20070218662A1 Antimony ion implantation for semiconductor components 有权
标题翻译：半导体元件的锑离子注入
公开(公告)号：US20070218662A1
公开(公告)日：2007-09-20
申请号：US11725927
申请日：2007-03-20
申请人： Haowen Bu , Amitabh Jain , Srinivasan Chakravarthi , Shashank Ekbote
发明人： Haowen Bu , Amitabh Jain , Srinivasan Chakravarthi , Shashank Ekbote
IPC分类号： H01L21/425
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/324 , H01L29/6653 , H01L29/7833
摘要： A method is disclosed for implanting and activating antimony as a dopant in a semiconductor substrate. A method is also disclosed for implanting and activating antimony to form a source/drain extension region in the formation of a transistor, in such a manner as to achieve high activation and avoid deactivation via subsequent exposure to high temperatures. This technique facilitates the formation of very thin source/drain regions that exhibit reduced sheet resistance while also suppressing short channel effects. Enhancements to these techniques are also suggested for more precise implantation of antimony to create a shallower source/drain extension, and to ensure formation of the source/drain extension region to underlap the gate. Also disclosed are transistors and other semiconductor components that include doped regions comprising activated antimony, such as those formed according to the disclosed methods.
摘要翻译：公开了一种用于在半导体衬底中注入和活化锑作为掺杂剂的方法。还公开了一种用于注入和活化锑以形成晶体管的源极/漏极延伸区域的方法，以便实现高激活并避免随后暴露于高温而失活。该技术有助于形成非常薄的源极/漏极区域，其表现出降低的薄层电阻，同时还抑制短沟道效应。还建议对这些技术的增强用于更精确地注入锑以产生较浅的源极/漏极延伸，并且确保形成源极/漏极延伸区域以使栅极下沉。还公开了晶体管和其它半导体组件，其包括包含活性锑的掺杂区域，例如根据所公开的方法形成的那些。

4. 发明申请

US20060017079A1 N-type transistor with antimony-doped ultra shallow source and drain 审中-公开
标题翻译：具有锑掺杂超浅源极和漏极的N型晶体管
公开(公告)号：US20060017079A1
公开(公告)日：2006-01-26
申请号：US10896421
申请日：2004-07-21
申请人： Srinivasan Chakravarthi , Amitabh Jain , Xin Zhang
发明人： Srinivasan Chakravarthi , Amitabh Jain , Xin Zhang
IPC分类号： H01L29/76 , H01L21/425 , H01L31/117 , H01L21/44
CPC分类号： H01L21/26513 , H01L21/02667 , H01L21/2022 , H01L21/26506 , H01L29/66575 , H01L29/78
摘要： We disclose a process for forming ultra shallow n+p junctions. The junction is formed by, for example, implanting 3E14 ions/cm2 of antimony ions at 5 keV into silicon. The silicon is pre-amorphized by a previous ion-implantation. The pre-amorphizing implant species may be germanium or arsenic. Germanium may be implanted at 15 keV and Arsenic may be implanted at 2 keV. Both the pre-amorphizing implant and the antimony implant are preferably through bare silicon surface—not covered with any foreign material with the exception of possibly a layer of native oxide. The junction is annealed at about 950° C. following the implants to re-crystallize the implanted region and to activate the implanted ions. The ultra shallow junction is superior because it has a abrupt junction, high sheet resistance and can be formed with low thermal budget.
摘要翻译：我们公开了形成超浅层p + p结的方法。该结通过例如以5keV将3E14离子/ cm 2的锑离子注入到硅中而形成。硅通过先前的离子注入而被非晶化。前非晶化植入物种可以是锗或砷。锗可以以15keV注入，砷可以以2keV注入。预非晶化植入物和锑植入物优选通过裸露的硅表面 - 未被任何异物覆盖，除了可能的一层天然氧化物之外。接合点在大约950℃下退火，在植入物重新结晶植入区域并激活注入的离子之后。超浅结是优越的，因为其具有突然的接合，高的薄层电阻，并且可以以低的热预算形成。

5. 发明授权

US07795122B2 Antimony ion implantation for semiconductor components 有权
标题翻译：半导体元件的锑离子注入
公开(公告)号：US07795122B2
公开(公告)日：2010-09-14
申请号：US11725927
申请日：2007-03-20
申请人： Haowen Bu , Amitabh Jain , Srinivasan Chakravarthi , Shashank S. Ekbote
发明人： Haowen Bu , Amitabh Jain , Srinivasan Chakravarthi , Shashank S. Ekbote
IPC分类号： H01L21/425
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/324 , H01L29/6653 , H01L29/7833
摘要： A method is disclosed for implanting and activating antimony as a dopant in a semiconductor substrate. A method is also disclosed for implanting and activating antimony to form a source/drain extension region in the formation of a transistor, in such a manner as to achieve high activation and avoid deactivation via subsequent exposure to high temperatures. This technique facilitates the formation of very thin source/drain regions that exhibit reduced sheet resistance while also suppressing short channel effects. Enhancements to these techniques are also suggested for more precise implantation of antimony to create a shallower source/drain extension, and to ensure formation of the source/drain extension region to underlap the gate. Also disclosed are transistors and other semiconductor components that include doped regions comprising activated antimony, such as those formed according to the disclosed methods.
摘要翻译：公开了一种用于在半导体衬底中注入和活化锑作为掺杂剂的方法。还公开了一种用于注入和活化锑以形成晶体管的源极/漏极延伸区域的方法，以便实现高激活并避免随后暴露于高温而失活。该技术有助于形成非常薄的源极/漏极区域，其表现出降低的薄层电阻同时还抑制短沟道效应。还建议对这些技术的增强用于更精确地注入锑以产生较浅的源极/漏极延伸，并且确保形成源极/漏极延伸区域以使栅极下沉。还公开了晶体管和其它半导体组件，其包括包含活性锑的掺杂区域，例如根据所公开的方法形成的那些。

6. 发明授权

US06797593B2 Methods and apparatus for improved mosfet drain extension activation 有权
标题翻译：改善mosfet漏极扩展激活的方法和装置
公开(公告)号：US06797593B2
公开(公告)日：2004-09-28
申请号：US10243610
申请日：2002-09-13
申请人： Srinivasan Chakravarthi , Amitabh Jain , Xin Zhang
发明人： Srinivasan Chakravarthi , Amitabh Jain , Xin Zhang
IPC分类号： H01L21425
CPC分类号： H01L29/6653 , H01L21/26513 , H01L21/324 , H01L29/665 , H01L29/6659
摘要： Methods are described for fabricating MOS type transistors, in which multiple drain extension implants are performed using different dopant species of the same type. The implanted drain extension dopants are activated using separate anneal processes to provide active dopants of both species throughout the drain extension regions adjacent the transistor channel.
摘要翻译：描述了用于制造MOS型晶体管的方法，其中使用相同类型的不同掺杂剂种类来执行多个漏极延伸注入。注入的漏极延伸掺杂剂使用单独的退火工艺来激活，以在与晶体管沟道相邻的漏极延伸区域提供两种物质的有源掺杂剂。

7. 发明授权

US07371648B2 Method for manufacturing a transistor device having an improved breakdown voltage and a method for manufacturing an integrated circuit using the same 有权
标题翻译：具有改善的击穿电压的晶体管器件的制造方法和使用其的集成电路的制造方法
公开(公告)号：US07371648B2
公开(公告)日：2008-05-13
申请号：US11469512
申请日：2006-09-01
申请人： Jihong Chen , Srinivasan Chakravarthi , Eddie H. Breashears , Amitabh Jain
发明人： Jihong Chen , Srinivasan Chakravarthi , Eddie H. Breashears , Amitabh Jain
IPC分类号： H01L21/336 , H01L21/04 , H01L21/425
CPC分类号： H01L29/7833 , H01L21/26506 , H01L21/823814 , H01L29/6656 , H01L29/6659
摘要： The present invention provides a method for manufacturing a transistor device, and a method for manufacturing an integrated circuit including the same. The method for manufacturing the transistor device, among other elements, includes forming a gate structure over a substrate, implanting an atom selected from the group consisting of fluorine, silicon, or germanium into the substrate proximate the gate structure to cause at least a portion of the substrate to be in a sub-amorphous state, and implanting a dopant into the substrate having the implanted atom therein, thereby forming source/drain regions in the substrate, wherein the transistor device does not have a halo/pocket implant.
摘要翻译：本发明提供一种晶体管器件的制造方法及其制造方法。制造晶体管器件的方法以及其它元件包括在衬底上形成栅极结构，将选自氟，硅或锗的原子在栅极结构附近植入到衬底中，以使至少一部分所述衬底处于亚非晶态，并且将掺杂剂注入到其中具有注入原子的衬底中，从而在衬底中形成源极/漏极区，其中所述晶体管器件不具有卤素/穴袋注入。

8. 发明申请

US20080057654A1 METHOD FOR MANUFACTURING A TRANSISTOR DEVICE HAVING AN IMPROVED BREAKDOWN VOLTAGE AND A METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT USING THE SAME 有权
标题翻译：具有改进的断开电压的晶体管器件的制造方法和使用其制造集成电路的方法
公开(公告)号：US20080057654A1
公开(公告)日：2008-03-06
申请号：US11469512
申请日：2006-09-01
申请人： Jihong Chen , Srinivasan Chakravarthi , Eddie H. Breashears , Amitabh Jain
发明人： Jihong Chen , Srinivasan Chakravarthi , Eddie H. Breashears , Amitabh Jain
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L21/26506 , H01L21/823814 , H01L29/6656 , H01L29/6659
摘要： The present invention provides a method for manufacturing a transistor device, and a method for manufacturing an integrated circuit including the same. The method for manufacturing the transistor device, among other elements, includes forming a gate structure over a substrate, implanting an atom selected from the group consisting of fluorine, silicon, or germanium into the substrate proximate the gate structure to cause at least a portion of the substrate to be in a sub-amorphous state, and implanting a dopant into the substrate having the implanted atom therein, thereby forming source/drain regions in the substrate, wherein the transistor device does not have a halo/pocket implant.
摘要翻译：本发明提供一种晶体管器件的制造方法及其制造方法。制造晶体管器件的方法以及其它元件包括在衬底上形成栅极结构，将选自氟，硅或锗的原子在栅极结构附近植入到衬底中，以使至少一部分所述衬底处于亚非晶态，并且将掺杂剂注入到其中具有注入原子的衬底中，从而在衬底中形成源极/漏极区，其中所述晶体管器件不具有卤素/穴袋注入。

9. 发明授权

US08580663B2 Formation of shallow junctions by diffusion from a dielectronic doped by cluster or molecular ion beams 有权
标题翻译：通过由簇或分子离子束掺杂的电介质扩散形成浅结
公开(公告)号：US08580663B2
公开(公告)日：2013-11-12
申请号：US13217577
申请日：2011-08-25
申请人： Amitabh Jain
发明人： Amitabh Jain
IPC分类号： H01L21/426
CPC分类号： H01L21/823814 , H01L21/2251 , H01L21/2255 , H01L21/26566 , H01L21/823807 , H01L21/823842 , H01L21/84 , H01L29/6659 , H01L29/7833
摘要： A process for forming diffused region less than 20 nanometers deep with an average doping dose above 1014 cm−2 in an IC substrate, particularly LDD region in an MOS transistor, is disclosed. Dopants are implanted into a source dielectric layer using gas cluster ion beam (GCIB) implantation, molecular ion implantation or atomic ion implantation resulting in negligible damage in the IC substrate. A spike anneal or a laser anneal diffuses the implanted dopants into the IC substrate. The inventive process may also be applied to forming source and drain (S/D) regions. One source dielectric layer may be used for forming both NLDD and PLDD regions.
摘要翻译：公开了一种用于在IC衬底，特别是MOS晶体管中的LDD区域形成平均掺杂剂量高于1014cm -2的深度小于20nm的扩散区域的工艺。使用气体簇离子束（GCIB）注入，分子离子注入或原子离子注入将掺杂剂注入到源电介质层中，导致IC衬底中的可忽略的损伤。尖峰退火或激光退火将注入的掺杂剂扩散到IC衬底中。本发明的方法也可以应用于形成源极和漏极（S / D）区域。一个源介质层可用于形成NLDD和PLDD区域。

10. 发明授权

US08252609B2 Curvature reduction for semiconductor wafers 有权
标题翻译：半导体晶圆的曲率减少
公开(公告)号：US08252609B2
公开(公告)日：2012-08-28
申请号：US12757704
申请日：2010-04-09
申请人： Brian K. Kirkpatrick , Steven L. Prins , Amitabh Jain
发明人： Brian K. Kirkpatrick , Steven L. Prins , Amitabh Jain
IPC分类号： H01L21/26 , H01L21/66
CPC分类号： H01L21/26506 , H01L21/02532 , H01L21/02658 , H01L21/02667 , H01L22/12 , H01L22/20
摘要： A method for reducing curvature of a wafer having a semiconductor surface. One or more process steps are identified at which wafers exhibit the largest curvature, and/or wafer curvature that may reduce die yield. A crystal damaging process converts at least a portion of the semiconductor surface into at least one amorphous surface region After or contemporaneously with the crystal damaging, the amorphous surface region is recrystallized by recrystallization annealing that anneals the wafer for a time ≦5 seconds at a temperature sufficient for recrystallization of the amorphous surface region. A subsequent photolithography step is facilitated due to the reduction in average wafer curvature provided by the recrystallization.
摘要翻译：一种用于减小具有半导体表面的晶片的曲率的方法。识别一个或多个工艺步骤，在该处理步骤中，晶片呈现最大的曲率，和/或晶片曲率，其可以降低模具的产量。晶体损伤过程将半导体表面的至少一部分转化成至少一个非晶表面区域在晶体损坏之后或同时与晶体有害的同时，非晶表面区域通过重结晶退火重结晶，使晶片退火一段时间，足以使非晶表面区域再结晶的温度。由于再结晶提供的平均晶片曲率的减小，随后的光刻步骤变得容易。

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