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1. 发明授权

US07313140B2 Method and apparatus to assemble data segments into full packets for efficient packet-based classification 有权
标题翻译：将数据段组合成完整分组的方法和装置，用于有效的基于分组的分类
公开(公告)号：US07313140B2
公开(公告)日：2007-12-25
申请号：US10188087
申请日：2002-07-03
申请人： Sridhar Lakshmanamurthy , Charles E. Narad , Lawrence B. Huston , Yim Pun , Raymond Ng , Debra Bernstein , Mark B. Rosenbluth
发明人： Sridhar Lakshmanamurthy , Charles E. Narad , Lawrence B. Huston , Yim Pun , Raymond Ng , Debra Bernstein , Mark B. Rosenbluth
IPC分类号： H04L12/28
CPC分类号： H04L49/9094 , H04L49/90 , H04L49/9047
摘要： A method may be used for assembling received data segments into full packets in an initial processing stage in a processor. The method may include receiving a plurality of data segments from a packet and determining a first storage location for each of the plurality of data segments. The method may further include storing each of the plurality of data segments in its determined first storage location and determining a second storage location for each of the plurality of data segments, the second storage locations being logically ordered to represent the order the data segments originally occurred in the packet. The method may also include storing each of the plurality of data segments in its determined second storage location to re-assemble the packet and releasing the first storage location associated with each data segment after storing the data segment in its determined second storage location. The method may additionally include, upon the storing of an end of packet data segment from the packet in its determined second storage location, passing control of the plurality of related data segments to a next processing stage in the processor.
摘要翻译：可以在处理器的初始处理阶段中使用一种方法将接收的数据段组装成全分组。该方法可以包括从分组接收多个数据段并且确定多个数据段中的每一个的第一存储位置。该方法还可以包括将多个数据段中的每一个存储在其确定的第一存储位置中，并且为多个数据段中的每一个确定第二存储位置，第二存储位置被逻辑地排序以表示数据段最初发生的顺序在包中。该方法还可以包括将多个数据段中的每一个存储在其确定的第二存储位置中以在将数据段存储在其确定的第二存储位置之后重新组合分组并释放与每个数据段相关联的第一存储位置。该方法可以另外包括在从分组在其确定的第二存储位置中存储分组数据段的结束时，将多个相关数据段的控制传递到处理器中的下一个处理阶段。

2. 发明授权

US07251219B2 Method and apparatus to communicate flow control information in a duplex network processor system 有权
标题翻译：在双工网络处理器系统中传送流量控制信息的方法和装置
公开(公告)号：US07251219B2
公开(公告)日：2007-07-31
申请号：US10188081
申请日：2002-07-03
申请人： Sridhar Lakshmanamurthy , Lawrence B. Huston , Yim Pun , Raymond Ng , Hugh M. Wilkinson, III , Mark B. Rosenbluth , David Romano
发明人： Sridhar Lakshmanamurthy , Lawrence B. Huston , Yim Pun , Raymond Ng , Hugh M. Wilkinson, III , Mark B. Rosenbluth , David Romano
IPC分类号： H04B1/44
CPC分类号： H04L49/30 , H04L47/10 , H04L47/266 , H04L47/30 , H04L49/254 , H04L49/50
摘要： In-band flow control data may be received from a switch fabric at a first network processor. The received in-band flow control data may be transmitted to a second network processor using a flow control bus. The second network processor may determine which receive queues in the switch fabric exceed a predetermined overflow threshold based on the in-band flow control data. The second processor may transmit data to the receive queues in the switch fabric determined not to exceed the predetermined overflow threshold.
摘要翻译：可以在第一网络处理器处从交换结构接收带内流控制数据。接收到的带内流控制数据可以使用流控制总线发送到第二网络处理器。第二网络处理器可以基于带内流控制数据来确定交换结构中的接收队列超过预定的溢出阈值。第二处理器可以将数据发送到被确定为不超过预定溢出阈值的交换结构中的接收队列。

3. 发明授权

US07103821B2 Method and apparatus for improving network router line rate performance by an improved system for error checking 失效
标题翻译：用于通过改进的系统进行错误检查来提高网络路由器线路速率性能的方法和装置
公开(公告)号：US07103821B2
公开(公告)日：2006-09-05
申请号：US10188516
申请日：2002-07-03
申请人： Sridhar Lakshmanamurthy , Charles E. Narad , Lawrence B. Huston , Yim Pun , Kin-Yip Liu
发明人： Sridhar Lakshmanamurthy , Charles E. Narad , Lawrence B. Huston , Yim Pun , Kin-Yip Liu
IPC分类号： H03M13/00
CPC分类号： G06F11/10
摘要： A method and apparatus for improving network router line rate performance by an improved system for error correction is described. In an embodiment of the present invention, error correction is performed by a hardware-based system within the processing engine of a router's network processor.
摘要翻译：描述了一种通过改进的纠错系统来改善网络路由器线路速率性能的方法和装置。在本发明的实施例中，由路由器网络处理器的处理引擎内的基于硬件的系统执行纠错。

4. 发明授权

US07324520B2 Method and apparatus to process switch traffic 有权
标题翻译：处理交换机流量的方法和装置
公开(公告)号：US07324520B2
公开(公告)日：2008-01-29
申请号：US10188419
申请日：2002-07-03
申请人： Sridhar Lakshmanamurthy , Lawrence B. Huston , Debra Bernstein , Hugh M. Wilkinson, III , Mark B. Rosenbluth
发明人： Sridhar Lakshmanamurthy , Lawrence B. Huston , Debra Bernstein , Hugh M. Wilkinson, III , Mark B. Rosenbluth
IPC分类号： H04L12/28
CPC分类号： H04L49/9094 , H04L49/90 , H04L49/9047 , H04L49/9073
摘要： A system and method for reassembling c-frames into coherent packets are disclosed. C-frames contain segments of a data set. A micro-engine operating multiple threads copies the data set segments into assigned queues, following a thread hierarchy to keep the segments in order. The queues are stored in SRAM. The micro-engine maintains a subset of the total number of queues in local memory. If a segment belongs to a queue not in local memory, the least recently used queue is copied to SRAM, the required queue is read from SRAM, and the queue is updated with the data set segment.
摘要翻译：公开了一种用于将c帧重新组合成相干分组的系统和方法。 C帧包含数据集的段。运行多个线程的微引擎将数据集段复制到分配的队列中，遵循线程层次结构以保持段的顺序。队列存储在SRAM中。微引擎维护本地内存中队列总数的一个子集。如果段属于不在本地存储器中的队列，则将最近最少使用的队列复制到SRAM，从SRAM读取所需的队列，并且使用数据集段更新队列。

5. 发明申请

US20050050306A1 Executing instructions on a processor 审中-公开
标题翻译：在处理器上执行指令
公开(公告)号：US20050050306A1
公开(公告)日：2005-03-03
申请号：US10649356
申请日：2003-08-26
申请人： Sridhar Lakshmanamurthy , Prashant Chandra , Wilson Liao , Jeen-Yuan Miin , Yim Pun , Chen-Chi Kuo , Jaroslaw Sydir , Uday Naik
发明人： Sridhar Lakshmanamurthy , Prashant Chandra , Wilson Liao , Jeen-Yuan Miin , Yim Pun , Chen-Chi Kuo , Jaroslaw Sydir , Uday Naik
IPC分类号： G06F9/00 , G06F9/302 , G06F9/32
CPC分类号： G06F9/3001 , G06F9/30094
摘要： A method of executing instructions on a processor includes, receiving a first condition code produced by executing a first instruction during a first clock cycle on an array of engines included in the processor, receiving a second condition code produced by executing a second instruction during a second clock cycle on the array of engines included in the processor, and executing a logical operator on the first and second condition codes during the second clock cycle on the array of engines included in the processor.
摘要翻译：在处理器上执行指令的方法包括：接收通过在包括在处理器中的引擎阵列上的第一时钟周期期间执行第一指令而产生的第一条件代码，接收在第二时间执行第二指令而产生的第二条件代码在包括在处理器中的引擎阵列上的时钟周期，以及在包括在处理器中的引擎阵列上的第二时钟周期期间对第一和第二条件代码执行逻辑运算符。

6. 发明授权

US07707266B2 Scalable, high-performance, global interconnect scheme for multi-threaded, multiprocessing system-on-a-chip network processor unit 失效
标题翻译：可扩展的，高性能的全球互连方案，用于多线程，多处理系统级芯片网络处理器单元
公开(公告)号：US07707266B2
公开(公告)日：2010-04-27
申请号：US10997624
申请日：2004-11-23
申请人： Sridhar Lakshmanamurthy , Mark B. Rosenbluth , Matthew Adiletta , Jeen-Xuan Miin , Bijoy Bose
发明人： Sridhar Lakshmanamurthy , Mark B. Rosenbluth , Matthew Adiletta , Jeen-Xuan Miin , Bijoy Bose
IPC分类号： G06F13/00 , G06F15/173 , G06F15/16
CPC分类号： G06F15/7842 , G06F15/8007
摘要： A scalable, high-performance interconnect scheme for a multi-threaded, multi-processing system-on-a-chip network processor unit. An apparatus implementing the technique includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and a chassis interconnect that may be controlled to selectively connects a given master to a given target. In one embodiment, the chassis interconnect comprises a plurality of sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus, a pull data bus for target writes, and a push data bus for target reads. Multiplexer circuitry for each of the command bus, pull data bus, and push data bus is employed to selectively connect a given cluster to a given target to enable commands and data to be passed between the given cluster and the given target.
摘要翻译：用于多线程，多处理片上系统处理器单元的可扩展的高性能互连方案。实现该技术的装置包括配置在多个集群中的多个主机，多个目标以及可被控制以选择性地将给定主机连接到给定目标的机箱互连。在一个实施例中，机箱互连包括连接在多个群集之间的多组总线，并且多个目标形成横杆互连，包括对应于命令总线的总线线路，用于目标的拉动数据总线写入和用于目标读取的推送数据总线。采用用于每个命令总线，拉数据总线和推数据总线的多路复用器电路来选择性地将给定集群连接到给定目标，以使命令和数据能够在给定集群和给定目标之间传递。

7. 发明授权

US08087024B2 Multiple multi-threaded processors having an L1 instruction cache and a shared L2 instruction cache 失效
标题翻译：具有L1指令高速缓存和共享L2指令高速缓存的多个多线程处理器
公开(公告)号：US08087024B2
公开(公告)日：2011-12-27
申请号：US12313247
申请日：2008-11-18
申请人： Sridhar Lakshmanamurthy , Wilson Y. Liao , Prashant R. Chandra , Jeen-Yuan Miin , Yim Pun
发明人： Sridhar Lakshmanamurthy , Wilson Y. Liao , Prashant R. Chandra , Jeen-Yuan Miin , Yim Pun
IPC分类号： G06F9/46 , G06F13/00 , G06F12/00 , G06F15/76 , G06F9/44
CPC分类号： G06F12/0811 , G06F12/0842 , H04L69/12
摘要： In general, in one aspect, the disclosure describes a processor that includes an instruction store to store instructions of at least a portion of at least one program and multiple engines coupled to the shared instruction store. The engines provide multiple execution threads and include an instruction cache to cache a subset of the at least the portion of the at least one program from the instruction store, with different respective portions of the engine's instruction cache being allocated to different respective ones of the engine threads.
摘要翻译：一般来说，一方面，本发明描述了一种处理器，其包括指令存储器，用于存储至少一个程序的至少一部分和耦合到共享指令存储器的多个引擎的指令。引擎提供多个执行线程并且包括指令高速缓存以从指令存储器缓存至少一个程序的至少一部分的子集，其中引擎指令高速缓存的不同相应部分分配给引擎的不同相应引擎线程。

8. 发明授权

US07536692B2 Thread-based engine cache partitioning 有权
标题翻译：基于线程的引擎缓存分区
公开(公告)号：US07536692B2
公开(公告)日：2009-05-19
申请号：US10704431
申请日：2003-11-06
申请人： Sridhar Lakshmanamurthy , Wilson Y. Liao , Prashant R. Chandra , Jeen-Yuan Miin , Yim Pun
发明人： Sridhar Lakshmanamurthy , Wilson Y. Liao , Prashant R. Chandra , Jeen-Yuan Miin , Yim Pun
IPC分类号： G06F9/46 , G06F12/00
CPC分类号： G06F12/0811 , G06F12/0842 , H04L69/12
摘要： In general, in one aspect, the disclosure describes a processor that includes an instruction store to store instructions of at least a portion of at least one program and multiple engines coupled to the shared instruction store. The engines provide multiple execution threads and include an instruction cache to cache a subset of the at least the portion of the at least one program from the instruction store, with different respective portions of the engine's instruction cache being allocated to different respective ones of the engine threads.
摘要翻译：一般来说，一方面，本发明描述了一种处理器，其包括指令存储器，用于存储至少一个程序的至少一部分和耦合到共享指令存储器的多个引擎的指令。引擎提供多个执行线程并且包括指令高速缓存以从指令存储器缓存至少一个程序的至少一部分的子集，其中引擎指令高速缓存的不同相应部分分配给引擎的不同相应引擎线程。

9. 发明申请

US20050102474A1 Dynamically caching engine instructions 审中-公开
标题翻译：动态缓存引擎指令
公开(公告)号：US20050102474A1
公开(公告)日：2005-05-12
申请号：US10704432
申请日：2003-11-06
申请人： Sridhar Lakshmanamurthy , Wilson Liao , Prashant Chandra , Jeen-Yuan Miin , Yim Pun
发明人： Sridhar Lakshmanamurthy , Wilson Liao , Prashant Chandra , Jeen-Yuan Miin , Yim Pun
IPC分类号： G06F9/30 , G06F9/38 , G06F12/08 , G06F15/78 , G06F12/00
CPC分类号： G06F9/3802 , G06F9/30047 , G06F9/3851 , G06F12/0875 , H04L49/3063
摘要： In general, in one aspect, the disclosure describes a processor that includes an instruction store to store instructions of at least a portion of at least one program and a set of multiple engines coupled to the instruction store. The engines include an engine instruction cache and circuitry to request a subset of the at least the portion of the at least one program.
摘要翻译：通常，在一个方面，本发明描述了一种处理器，其包括指令存储器，用于存储至少一个程序的至少一部分和耦合到指令存储器的多个引擎的集合的指令。引擎包括引擎指令高速缓存和用于请求至少一个程序的至少一部分的子集的电路。

10. 发明申请

US20050108479A1 Servicing engine cache requests 审中-公开
标题翻译：服务引擎缓存请求
公开(公告)号：US20050108479A1
公开(公告)日：2005-05-19
申请号：US10704286
申请日：2003-11-06
申请人： Sridhar Lakshmanamurthy , Wilson Liao , Prashant Chandra , Jeen-Yuan Miin , Yim Pun
发明人： Sridhar Lakshmanamurthy , Wilson Liao , Prashant Chandra , Jeen-Yuan Miin , Yim Pun
IPC分类号： G06F12/08 , G06F13/28
CPC分类号： G06F12/0811
摘要： In general, in one aspect, the disclosure describes a processor that includes a memory to store at least a portion of instructions of at least one program and multiple packet engines that include an engine instruction cache to store a subset of the at least one program. The processor also includes circuitry coupled to the packet engines and the memory to receive requests from the multiple engines for subsets of the at least one portion of the at least one set of instructions.
摘要翻译：通常，在一个方面，本发明描述了一种处理器，其包括存储器，用于存储至少一个程序和多个分组引擎的指令的至少一部分，所述指令包括引擎指令高速缓存以存储所述至少一个程序的子集。处理器还包括耦合到分组引擎和存储器的电路，用于接收来自多个引擎的针对至少一组指令的至少一部分的子集的请求。

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