专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07313140B2 Method and apparatus to assemble data segments into full packets for efficient packet-based classification 有权
标题翻译：将数据段组合成完整分组的方法和装置，用于有效的基于分组的分类
公开(公告)号：US07313140B2
公开(公告)日：2007-12-25
申请号：US10188087
申请日：2002-07-03
申请人： Sridhar Lakshmanamurthy , Charles E. Narad , Lawrence B. Huston , Yim Pun , Raymond Ng , Debra Bernstein , Mark B. Rosenbluth
发明人： Sridhar Lakshmanamurthy , Charles E. Narad , Lawrence B. Huston , Yim Pun , Raymond Ng , Debra Bernstein , Mark B. Rosenbluth
IPC分类号： H04L12/28
CPC分类号： H04L49/9094 , H04L49/90 , H04L49/9047
摘要： A method may be used for assembling received data segments into full packets in an initial processing stage in a processor. The method may include receiving a plurality of data segments from a packet and determining a first storage location for each of the plurality of data segments. The method may further include storing each of the plurality of data segments in its determined first storage location and determining a second storage location for each of the plurality of data segments, the second storage locations being logically ordered to represent the order the data segments originally occurred in the packet. The method may also include storing each of the plurality of data segments in its determined second storage location to re-assemble the packet and releasing the first storage location associated with each data segment after storing the data segment in its determined second storage location. The method may additionally include, upon the storing of an end of packet data segment from the packet in its determined second storage location, passing control of the plurality of related data segments to a next processing stage in the processor.
摘要翻译：可以在处理器的初始处理阶段中使用一种方法将接收的数据段组装成全分组。该方法可以包括从分组接收多个数据段并且确定多个数据段中的每一个的第一存储位置。该方法还可以包括将多个数据段中的每一个存储在其确定的第一存储位置中，并且为多个数据段中的每一个确定第二存储位置，第二存储位置被逻辑地排序以表示数据段最初发生的顺序在包中。该方法还可以包括将多个数据段中的每一个存储在其确定的第二存储位置中以在将数据段存储在其确定的第二存储位置之后重新组合分组并释放与每个数据段相关联的第一存储位置。该方法可以另外包括在从分组在其确定的第二存储位置中存储分组数据段的结束时，将多个相关数据段的控制传递到处理器中的下一个处理阶段。

2. 发明授权

US07251219B2 Method and apparatus to communicate flow control information in a duplex network processor system 有权
标题翻译：在双工网络处理器系统中传送流量控制信息的方法和装置
公开(公告)号：US07251219B2
公开(公告)日：2007-07-31
申请号：US10188081
申请日：2002-07-03
申请人： Sridhar Lakshmanamurthy , Lawrence B. Huston , Yim Pun , Raymond Ng , Hugh M. Wilkinson, III , Mark B. Rosenbluth , David Romano
发明人： Sridhar Lakshmanamurthy , Lawrence B. Huston , Yim Pun , Raymond Ng , Hugh M. Wilkinson, III , Mark B. Rosenbluth , David Romano
IPC分类号： H04B1/44
CPC分类号： H04L49/30 , H04L47/10 , H04L47/266 , H04L47/30 , H04L49/254 , H04L49/50
摘要： In-band flow control data may be received from a switch fabric at a first network processor. The received in-band flow control data may be transmitted to a second network processor using a flow control bus. The second network processor may determine which receive queues in the switch fabric exceed a predetermined overflow threshold based on the in-band flow control data. The second processor may transmit data to the receive queues in the switch fabric determined not to exceed the predetermined overflow threshold.
摘要翻译：可以在第一网络处理器处从交换结构接收带内流控制数据。接收到的带内流控制数据可以使用流控制总线发送到第二网络处理器。第二网络处理器可以基于带内流控制数据来确定交换结构中的接收队列超过预定的溢出阈值。第二处理器可以将数据发送到被确定为不超过预定溢出阈值的交换结构中的接收队列。

3. 发明授权

US07324520B2 Method and apparatus to process switch traffic 有权
标题翻译：处理交换机流量的方法和装置
公开(公告)号：US07324520B2
公开(公告)日：2008-01-29
申请号：US10188419
申请日：2002-07-03
申请人： Sridhar Lakshmanamurthy , Lawrence B. Huston , Debra Bernstein , Hugh M. Wilkinson, III , Mark B. Rosenbluth
发明人： Sridhar Lakshmanamurthy , Lawrence B. Huston , Debra Bernstein , Hugh M. Wilkinson, III , Mark B. Rosenbluth
IPC分类号： H04L12/28
CPC分类号： H04L49/9094 , H04L49/90 , H04L49/9047 , H04L49/9073
摘要： A system and method for reassembling c-frames into coherent packets are disclosed. C-frames contain segments of a data set. A micro-engine operating multiple threads copies the data set segments into assigned queues, following a thread hierarchy to keep the segments in order. The queues are stored in SRAM. The micro-engine maintains a subset of the total number of queues in local memory. If a segment belongs to a queue not in local memory, the least recently used queue is copied to SRAM, the required queue is read from SRAM, and the queue is updated with the data set segment.
摘要翻译：公开了一种用于将c帧重新组合成相干分组的系统和方法。 C帧包含数据集的段。运行多个线程的微引擎将数据集段复制到分配的队列中，遵循线程层次结构以保持段的顺序。队列存储在SRAM中。微引擎维护本地内存中队列总数的一个子集。如果段属于不在本地存储器中的队列，则将最近最少使用的队列复制到SRAM，从SRAM读取所需的队列，并且使用数据集段更新队列。

4. 发明授权

US07707266B2 Scalable, high-performance, global interconnect scheme for multi-threaded, multiprocessing system-on-a-chip network processor unit 失效
标题翻译：可扩展的，高性能的全球互连方案，用于多线程，多处理系统级芯片网络处理器单元
公开(公告)号：US07707266B2
公开(公告)日：2010-04-27
申请号：US10997624
申请日：2004-11-23
申请人： Sridhar Lakshmanamurthy , Mark B. Rosenbluth , Matthew Adiletta , Jeen-Xuan Miin , Bijoy Bose
发明人： Sridhar Lakshmanamurthy , Mark B. Rosenbluth , Matthew Adiletta , Jeen-Xuan Miin , Bijoy Bose
IPC分类号： G06F13/00 , G06F15/173 , G06F15/16
CPC分类号： G06F15/7842 , G06F15/8007
摘要： A scalable, high-performance interconnect scheme for a multi-threaded, multi-processing system-on-a-chip network processor unit. An apparatus implementing the technique includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and a chassis interconnect that may be controlled to selectively connects a given master to a given target. In one embodiment, the chassis interconnect comprises a plurality of sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus, a pull data bus for target writes, and a push data bus for target reads. Multiplexer circuitry for each of the command bus, pull data bus, and push data bus is employed to selectively connect a given cluster to a given target to enable commands and data to be passed between the given cluster and the given target.
摘要翻译：用于多线程，多处理片上系统处理器单元的可扩展的高性能互连方案。实现该技术的装置包括配置在多个集群中的多个主机，多个目标以及可被控制以选择性地将给定主机连接到给定目标的机箱互连。在一个实施例中，机箱互连包括连接在多个群集之间的多组总线，并且多个目标形成横杆互连，包括对应于命令总线的总线线路，用于目标的拉动数据总线写入和用于目标读取的推送数据总线。采用用于每个命令总线，拉数据总线和推数据总线的多路复用器电路来选择性地将给定集群连接到给定目标，以使命令和数据能够在给定集群和给定目标之间传递。

5. 发明授权

US07200699B2 Scalable, two-stage round robin arbiter with re-circulation and bounded latency 有权
标题翻译：可扩展的两阶段循环仲裁器具有重新循环和有限延迟
公开(公告)号：US07200699B2
公开(公告)日：2007-04-03
申请号：US10933621
申请日：2004-09-02
申请人： Bijoy Bose , Sridhar Lakshmanamurthy , Mark B. Rosenbluth , Irwin Vaz , Alok Mathur
发明人： Bijoy Bose , Sridhar Lakshmanamurthy , Mark B. Rosenbluth , Irwin Vaz , Alok Mathur
IPC分类号： G06F13/368
CPC分类号： G06F13/4022 , G06F13/362
摘要： A scalable, two-stage round-robin arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and an chassis interconnect that may be controlled to selectively connects a given master to a given target. The chassis interconnect includes multiple sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus. A two-stage arbitration scheme is employed to arbitrate access to the command bus. The first arbitration stage is used to arbitrate between command requests issued by masters in a given cluster. The second arbitration stage is used to arbitrate between winning first stage command requests. One embodiment of the arbitration scheme employs re-circulation of second stage losers. Another embodiment employs re-prioritization of second stage losers.
摘要翻译：可扩展的两阶段循环仲裁器，具有重新循环和有限延迟，可用于多线程多处理器件。实现两级仲裁器的装置包括配置在多个集群中的多个主机，多个目标以及可被控制以选择性地将给定主机连接到给定目标的机箱互连。底盘互连包括连接在多个群集之间的多组总线，并且多个目标形成横杆互连，包括对应于命令总线的总线线。采用两阶段仲裁方案仲裁访问命令总线。第一个仲裁阶段用于在给定群集中由主人发出的命令请求之间进行仲裁。第二仲裁阶段用于在获胜的第一阶段命令请求之间进行仲裁。仲裁方案的一个实施例采用第二阶段输家的再循环。另一个实施例使用第二阶段输家的重新排序。

6. 发明授权

US07512729B2 Method and apparatus for a high efficiency two-stage rotating priority arbiter with predictable arbitration latency 有权
标题翻译：具有可预测仲裁延迟的高效率两阶段旋转优先仲裁器的方法和装置
公开(公告)号：US07512729B2
公开(公告)日：2009-03-31
申请号：US11097067
申请日：2005-03-31
申请人： Bijoy Bose , Sridhar Lakshmanamurthy , Mark B. Rosenbluth , Irwin J. Vaz , Suri Medapati , Edwin O'Yang
发明人： Bijoy Bose , Sridhar Lakshmanamurthy , Mark B. Rosenbluth , Irwin J. Vaz , Suri Medapati , Edwin O'Yang
IPC分类号： G06F13/00
CPC分类号： H04L49/101 , H04L49/254
摘要： A scalable, two-stage rotating priority arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and an chassis interconnect that may be controlled to selectively connects a given master to a given target. The chassis interconnect includes multiple sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus. A two-stage arbitration scheme is employed to arbitrate access to the command bus. The first arbitration stage is used to arbitrate between target requests issued by masters in a given cluster. The second arbitration stage is used to arbitrate between winning first-stage target requests. One embodiment of the arbitration scheme employs a rotating priority arbitration scheme at the first stage. Another embodiment employs a complementary rotating priority arbitration scheme at the second stage.
摘要翻译：一种可扩展的两阶段旋转优先仲裁器，具有重新循环和有限延迟，可用于多线程多处理设备。实现两级仲裁器的装置包括配置在多个集群中的多个主机，多个目标以及可被控制以选择性地将给定主机连接到给定目标的机箱互连。底盘互连包括连接在多个群集之间的多组总线，并且多个目标形成横杆互连，包括对应于命令总线的总线线。采用两阶段仲裁方案仲裁访问命令总线。第一个仲裁阶段用于在给定群集中由主人发出的目标请求之间进行仲裁。第二仲裁阶段用于在获胜的第一阶段目标请求之间进行仲裁。仲裁方案的一个实施例在第一阶段采用旋转优先权仲裁方案。另一实施例在第二阶段采用互补旋转优先权仲裁方案。

7. 发明授权

US07412551B2 Methods and apparatus for supporting programmable burst management schemes on pipelined buses 有权
标题翻译：在流水线总线上支持可编程突发管理方案的方法和装置
公开(公告)号：US07412551B2
公开(公告)日：2008-08-12
申请号：US10882375
申请日：2004-06-30
申请人： Bijoy Bose , Irwin Vaz , Sridhar Lakshmanamurthy , Mark B. Rosenbluth
发明人： Bijoy Bose , Irwin Vaz , Sridhar Lakshmanamurthy , Mark B. Rosenbluth
IPC分类号： G06F13/36
CPC分类号： G06F13/36 , H04L49/101 , H04L49/102 , H04L49/15 , H04L49/45
摘要： Methods and apparatus for supporting programmable burst management schemes on pipelined buses. The apparatus includes a plurality of bus masters (masters), configured in a plurality of clusters, and a plurality of target sub-groups. Each target sub-group includes one or more shared resource targets. A scalable chassis infrastructure is used to interconnect the targets with the clusters using a crossbar interconnect configuration including pipelined command, and data buses. The interconnect includes sub-group multiplexers for each sub-group and sub-group selection multiplexers coupled to each cluster. A two-stage arbiter, operatively coupled to the targets, sub-group multiplexers, and sub-group selection multiplexers, is employed to arbitrate transaction requests issued from the masters to the targets and manage transactions. The two-stage arbiter includes a provision for supporting programmable burst management, wherein selected sub-groups can be tuned for handling short or long burst traffic.
摘要翻译：在流水线总线上支持可编程突发管理方案的方法和装置。该装置包括配置在多个群集中的多个总线主站（主站）和多个目标子组。每个目标子组包括一个或多个共享资源目标。可扩展的机箱基础架构用于使用包括流水线命令和数据总线的交叉连接配置将目标与群集互连。互连包括用于每个子组的子组多路复用器和耦合到每个集群的子组选择多路复用器。使用可操作地耦合到目标的两级仲裁器，子组多路复用器和子组选择多路复用器来仲裁从主人发送到目标的事务请求并管理事务。两级仲裁器包括用于支持可编程突发管理的规定，其中可以调整所选择的子组以处理短或长突发流量。

8. 发明授权

US07610451B2 Data transfer mechanism using unidirectional pull bus and push bus 有权
标题翻译：数据传输机制采用单向拉总线和推送总线
公开(公告)号：US07610451B2
公开(公告)日：2009-10-27
申请号：US10057738
申请日：2002-01-25
申请人： Gilbert Wolrich , Mark B. Rosenbluth , Debra Bernstein , Matthew J. Adiletta
发明人： Gilbert Wolrich , Mark B. Rosenbluth , Debra Bernstein , Matthew J. Adiletta
IPC分类号： G06F12/00 , G06F15/00
CPC分类号： G06F9/3824 , G06F9/3851
摘要： A method for transferring data between programming agents and memory resources. The method includes transferring data between a processing agent and a memory resource, designating the memory resource for pushing the data to the processing agent via a push bus having a plurality of sources that arbitrate use of the push bus, and designating the memory resource for receiving the data from the processing agent via a pull bus having a plurality of destinations that arbitrate use of the pull bus.
摘要翻译：一种用于在编程代理和存储器资源之间传送数据的方法。该方法包括在处理代理和存储器资源之间传送数据，指定存储器资源，用于经由具有仲裁使用推送总线的多个源的推送总线将数据推送到处理代理，以及指定用于接收的存储器资源来自处理代理的数据经由具有仲裁使用拉总线的多个目的地的拉总线。

9. 发明申请

US20090119671A1 REGISTERS FOR DATA TRANSFERS 审中-公开
标题翻译：数据传输寄存器
公开(公告)号：US20090119671A1
公开(公告)日：2009-05-07
申请号：US12249786
申请日：2008-10-10
申请人： GILBERT WOLRICH , Mark B. Rosenbluth , Debra Bernstein , Matthew Adiletta , Hugh M. Wilkinson, III
发明人： GILBERT WOLRICH , Mark B. Rosenbluth , Debra Bernstein , Matthew Adiletta , Hugh M. Wilkinson, III
IPC分类号： G06F9/46 , G06F9/44 , G06F15/00 , G06F9/30 , G06F12/00
CPC分类号： G06F9/4843 , G06F9/30101 , G06F9/3012 , G06F9/30123 , G06F9/3851
摘要： A system and method for employing registers for data transfer in multiple hardware contexts and programming engines to facilitate high performance data processing. The system and method includes a processor that includes programming engines with registers for transferring data from one of the registers residing in an executing programming engine to a subsequent one of the registers residing in an adjacent programming engine.
摘要翻译：一种用于在多个硬件上下文和编程引擎中采用用于数据传输的寄存器以便于高性能数据处理的系统和方法。该系统和方法包括处理器，其包括具有寄存器的编程引擎，用于将驻留在执行编程引擎中的寄存器中的一个寄存器中的数据传送到驻留在相邻编程引擎中的后续寄存器中的寄存器。

10. 发明授权

US07487505B2 Multithreaded microprocessor with register allocation based on number of active threads 有权
标题翻译：基于活动线程数的多线程微处理器，具有寄存器分配
公开(公告)号：US07487505B2
公开(公告)日：2009-02-03
申请号：US10212945
申请日：2002-08-05
申请人： Mark B. Rosenbluth , Gilbert Wolrich , Debra Bernstein
发明人： Mark B. Rosenbluth , Gilbert Wolrich , Debra Bernstein
IPC分类号： G06F9/46 , G06F15/00 , G06F15/76 , G06F7/38 , G06F9/00 , G06F9/44 , G06F12/00 , G06F12/02
CPC分类号： G06F9/3885 , G06F9/30098 , G06F9/30123 , G06F9/3851
摘要： A mechanism in a multithreaded processor to allocate resources based on configuration information indicating how many threads are in use.
摘要翻译：多线程处理器中基于配置信息分配资源的机制，该配置信息指示正在使用多少线程。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式