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1. 发明授权

US07103821B2 Method and apparatus for improving network router line rate performance by an improved system for error checking 失效
标题翻译：用于通过改进的系统进行错误检查来提高网络路由器线路速率性能的方法和装置
公开(公告)号：US07103821B2
公开(公告)日：2006-09-05
申请号：US10188516
申请日：2002-07-03
申请人： Sridhar Lakshmanamurthy , Charles E. Narad , Lawrence B. Huston , Yim Pun , Kin-Yip Liu
发明人： Sridhar Lakshmanamurthy , Charles E. Narad , Lawrence B. Huston , Yim Pun , Kin-Yip Liu
IPC分类号： H03M13/00
CPC分类号： G06F11/10
摘要： A method and apparatus for improving network router line rate performance by an improved system for error correction is described. In an embodiment of the present invention, error correction is performed by a hardware-based system within the processing engine of a router's network processor.
摘要翻译：描述了一种通过改进的纠错系统来改善网络路由器线路速率性能的方法和装置。在本发明的实施例中，由路由器网络处理器的处理引擎内的基于硬件的系统执行纠错。

2. 发明授权

US07313140B2 Method and apparatus to assemble data segments into full packets for efficient packet-based classification 有权
标题翻译：将数据段组合成完整分组的方法和装置，用于有效的基于分组的分类
公开(公告)号：US07313140B2
公开(公告)日：2007-12-25
申请号：US10188087
申请日：2002-07-03
申请人： Sridhar Lakshmanamurthy , Charles E. Narad , Lawrence B. Huston , Yim Pun , Raymond Ng , Debra Bernstein , Mark B. Rosenbluth
发明人： Sridhar Lakshmanamurthy , Charles E. Narad , Lawrence B. Huston , Yim Pun , Raymond Ng , Debra Bernstein , Mark B. Rosenbluth
IPC分类号： H04L12/28
CPC分类号： H04L49/9094 , H04L49/90 , H04L49/9047
摘要： A method may be used for assembling received data segments into full packets in an initial processing stage in a processor. The method may include receiving a plurality of data segments from a packet and determining a first storage location for each of the plurality of data segments. The method may further include storing each of the plurality of data segments in its determined first storage location and determining a second storage location for each of the plurality of data segments, the second storage locations being logically ordered to represent the order the data segments originally occurred in the packet. The method may also include storing each of the plurality of data segments in its determined second storage location to re-assemble the packet and releasing the first storage location associated with each data segment after storing the data segment in its determined second storage location. The method may additionally include, upon the storing of an end of packet data segment from the packet in its determined second storage location, passing control of the plurality of related data segments to a next processing stage in the processor.
摘要翻译：可以在处理器的初始处理阶段中使用一种方法将接收的数据段组装成全分组。该方法可以包括从分组接收多个数据段并且确定多个数据段中的每一个的第一存储位置。该方法还可以包括将多个数据段中的每一个存储在其确定的第一存储位置中，并且为多个数据段中的每一个确定第二存储位置，第二存储位置被逻辑地排序以表示数据段最初发生的顺序在包中。该方法还可以包括将多个数据段中的每一个存储在其确定的第二存储位置中以在将数据段存储在其确定的第二存储位置之后重新组合分组并释放与每个数据段相关联的第一存储位置。该方法可以另外包括在从分组在其确定的第二存储位置中存储分组数据段的结束时，将多个相关数据段的控制传递到处理器中的下一个处理阶段。

3. 发明授权

US07039054B2 Method and apparatus for header splitting/splicing and automating recovery of transmit resources on a per-transmit granularity 有权
标题翻译：用于标题分割/拼接的方法和装置，并且在每个传输粒度上自动恢复传输资源
公开(公告)号：US07039054B2
公开(公告)日：2006-05-02
申请号：US10300709
申请日：2002-11-19
申请人： Charles E. Narad , Larry B. Huston , Yim Pun , Raymond Ng
发明人： Charles E. Narad , Larry B. Huston , Yim Pun , Raymond Ng
IPC分类号： H04L12/00
CPC分类号： H04L49/9042 , H04L49/90 , H04L49/901 , H04L49/9031
摘要： A multi-threaded microprocessor with support for packet header splitting during receive packet processing operations and packet header splicing during transmit packet processing operations, as well as optimized recovery of transmit resources, is presented.
摘要翻译：提出了一种多线程微处理器，在接收数据包处理操作期间支持数据包报头拆分，并在发送数据包处理操作期间支持数据包标头接合，以及优化的传输资源恢复。

4. 发明授权

US06401117B1 Platform permitting execution of multiple network infrastructure applications 失效
标题翻译：平台允许执行多个网络基础设施应用程序
公开(公告)号：US06401117B1
公开(公告)日：2002-06-04
申请号：US09282790
申请日：1999-03-31
申请人： Charles E. Narad , Kevin Fall , Neil MacAvoy , Pradip Shankar , Leonard M. Rand , Jerry J. Hall
发明人： Charles E. Narad , Kevin Fall , Neil MacAvoy , Pradip Shankar , Leonard M. Rand , Jerry J. Hall
IPC分类号： G06F1300
CPC分类号： H04L45/16 , G06F9/30021 , G06F9/30029 , G06F9/30036 , G06F9/30094 , G06F9/30127 , G06F9/30145 , G06F9/30167 , G06F9/3885 , H04L29/06 , H04L41/0893 , H04L47/10 , H04L47/627 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9047 , H04L49/9094 , H04L69/03 , H04L69/12
摘要： The present invention relates to a general-purpose programmable packet-processing platform for accelerating network infrastructure applications which have been structured so as to separate the stages of classification and action. Network packet classification, execution of actions upon those packets, management of buffer flow, encryption services, and management of Network Interface Controllers are accelerated through the use of a multiplicity of specialized modules. A language interface is defined for specifying both stateless and stateful classification of packets and to associate actions with classification results in order to efficiently utilize these specialized modules.
摘要翻译：本发明涉及一种用于加速网络基础设施应用的通用可编程分组处理平台，其被构造为分离分类和动作的阶段。通过使用多种专用模块，可以加速网络数据包分类，对这些数据包的操作执行，缓冲流的管理，加密服务和网络接口控制器的管理。定义了一种语言界面，用于指定数据包的无状态和有状态分类，并将动作与分类结果相关联，以便有效地利用这些专用模块。

5. 发明授权

US5287503A System having control registers coupled to a bus whereby addresses on the bus select a control register and a function to be performed on the control register 失效
标题翻译：具有耦合到总线的控制寄存器的系统，总线上的地址选择控制寄存器和在控制寄存器上执行的功能
公开(公告)号：US5287503A
公开(公告)日：1994-02-15
申请号：US767122
申请日：1991-09-27
申请人： Charles E. Narad
发明人： Charles E. Narad
IPC分类号： G06F12/08 , G06F9/308 , G06F9/312 , G06F9/318 , G06F9/46 , G06F12/00 , G06F15/167
CPC分类号： G06F9/526 , G06F9/30018 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3836 , G06F2209/521
摘要： A computer storage register architecture permitting secure atomic access to set or clear one or more particular bits wherein a multiple bit register is disclosed. In the preferred embodiment, a multiplicity of unique addresses is assigned to a multiple bit register. One address constitutes a read address, one address constitutes a clear address, and a third address constitutes a set address. An address decoder decodes the addresses assigned to the register so that only that register is accessed for the associated read, clear, and set operations, respectively. Data having a register position equivalent binary pattern of logical zeros and ones corresponding to particular bit locations of the register to be set or cleared are associated with the set and clear addresses. If the position equivalent binary value of the data associated with the address decoded is a logical one, then the corresponding bit in the register will be set or cleared. Otherwise, the bit remains unchanged.
摘要翻译：一种允许安全原子访问来设置或清除其中公开了多位寄存器的一个或多个特定位的计算机存储寄存器结构。在优选实施例中，多个唯一地址被分配给多位寄存器。一个地址构成读地址，一个地址构成一个清除地址，第三个地址构成一个地址。地址解码器对分配给寄存器的地址进行解码，以便分别仅为相关的读取，清除和设置操作访问该寄存器。具有与要设置或清除的寄存器的特定位位置相对应的具有逻辑零的等效二进制模式的寄存器位置的数据与设置和清除地址相关联。如果与解码的地址相关联的数据的位置等效二进制值为逻辑1，则寄存器中的相应位将被置位或清零。否则，该位保持不变。

6. 发明申请

US20120059956A1 DIRECT MEMORY ACCESS (DMA) TRANSFER OF NETWORK INTERFACE STATISTICS 有权
标题翻译：直接存储器访问（DMA）网络接口统计信息的传输
公开(公告)号：US20120059956A1
公开(公告)日：2012-03-08
申请号：US12942790
申请日：2010-11-09
申请人： Charles E. Narad
发明人： Charles E. Narad
IPC分类号： G06F13/28
CPC分类号： H04L45/60 , G06F13/28 , H04L43/0888
摘要： In general, in one aspect, the disclosure describes a method that includes maintaining statistics, at a network interface, metering operation of the network interface. The statistics are transferred by direct memory access from the network interface to a memory accessed by at least one processor.
摘要翻译：通常，一方面，本发明描述了一种方法，其包括在网络接口处维护网络接口的计量操作的统计。通过从网络接口直接存储器访问由至少一个处理器访问的存储器来传送统计数据。

7. 发明授权

US07171486B2 Reassembly of a transmission control protocol (TCP) data stream from payloads of TCP segments of a bidirectional TCP connection 有权
标题翻译：从双向TCP连接的TCP段的有效载荷重新组装传输控制协议（TCP）数据流
公开(公告)号：US07171486B2
公开(公告)日：2007-01-30
申请号：US10748997
申请日：2003-12-29
申请人： Charles E. Narad , Kevin Fall , Neil MacAvoy , Pradip Shankar , Leonard M. Rand , Jerry J. Hall
发明人： Charles E. Narad , Kevin Fall , Neil MacAvoy , Pradip Shankar , Leonard M. Rand , Jerry J. Hall
IPC分类号： G06F13/00
CPC分类号： H04L45/16 , G06F9/30021 , G06F9/30029 , G06F9/30036 , G06F9/30094 , G06F9/30127 , G06F9/30145 , G06F9/30167 , G06F9/3885 , H04L29/06 , H04L41/0893 , H04L47/10 , H04L47/627 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9047 , H04L49/9094 , H04L69/03 , H04L69/12
摘要： Described herein are techniques to perform reassembly of a Transmission Control Protocol (TCP) data stream from payloads of TCP segments of a bidirectional TCP connection between a first TCP end-point operating at a first network device and a second TCP end-point operating at a second network device.
摘要翻译：这里描述的是从在第一网络设备操作的第一TCP端点与在第一网络设备操作的第二TCP端点之间的双向TCP连接的TCP段的有效载荷执行传输控制协议（TCP）数据流的重新组合的技术第二网络设备。

8. 发明授权

US06859841B2 Programmable system for processing a partitioned network infrastructure 失效
标题翻译：用于处理分区网络基础设施的可编程系统
公开(公告)号：US06859841B2
公开(公告)日：2005-02-22
申请号：US10084815
申请日：2002-02-27
申请人： Charles E. Narad , Kevin Fall , Neil MacAvoy , Pradip Shankar , Leonard M. Rand , Jerry J. Hall
发明人： Charles E. Narad , Kevin Fall , Neil MacAvoy , Pradip Shankar , Leonard M. Rand , Jerry J. Hall
IPC分类号： H04L12/24 , H04L12/56 , H04L29/06 , G06F13/00
CPC分类号： H04L45/16 , G06F9/30021 , G06F9/30029 , G06F9/30036 , G06F9/30094 , G06F9/30127 , G06F9/30145 , G06F9/30167 , G06F9/3885 , H04L29/06 , H04L41/0893 , H04L47/10 , H04L47/627 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9047 , H04L49/9094 , H04L69/03 , H04L69/12
摘要： The present invention relates to a general-purpose programmable packet-processing platform for accelerating network infrastructure applications which have been structured so as to separate the stages of classification and action. Network packet classification, execution of actions upon those packets, management of buffer flow, encryption services, and management of Network Interface Controllers are accelerated through the use of a multiplicity of specialized modules. A language interface is defined for specifying both stateless and stateful classification of packets and to associate actions with classification results in order to efficiently utilize these specialized modules.
摘要翻译：本发明涉及一种用于加速网络基础设施应用的通用可编程分组处理平台，其被构造为分离分类和动作的阶段。通过使用多种专用模块，可以加速网络数据包分类，对这些数据包的操作执行，缓冲流的管理，加密服务和网络接口控制器的管理。定义了一种语言界面，用于指定数据包的无状态和有状态分类，并将动作与分类结果相关联，以便有效地利用这些专用模块。

9. 发明授权

US5367695A Bus-to-bus interface for preventing data incoherence in a multiple processor computer system 失效
标题翻译：总线到总线接口，用于防止多处理器计算机系统中的数据不一致
公开(公告)号：US5367695A
公开(公告)日：1994-11-22
申请号：US766784
申请日：1991-09-27
申请人： Charles E. Narad , Sun-Den Chen
发明人： Charles E. Narad , Sun-Den Chen
IPC分类号： G06F15/167 , G06F13/36 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4027
摘要： A bus-to-bus interface preserves data coherence between masters and slaves operating within a multiple processor computer system. Two buses are connected via the interface. The first bus connects a number of self-identifying masters. The second bus connects a number of master devices and a number of slave devices. The second bus has no mechanism with which devices connected to the second bus may identify themselves. The interface contains a pair of registers for each slave device connected through the second bus. One register stores a busy bit if the corresponding slave is engaged on behalf of a master. The second register stores an identifying code for the master delegating a task to the corresponding slave. When a slave has accepted a task on behalf of a master and commanded the master to relinquish the bus, the busy register will be set and the master identification register will store the identifying code for the delegating master. Thereafter no master will be permitted to access the engaged slave unless the master identification code is that of the delegating master. Moreover, a delegating master will be denied access to the slave by that slave until the slave has completed the task accepted on behalf of the master. By preventing unintended masters from accessing slaves prior to the delegating master, inadvertent data transferred to the wrong master is avoided. Data coherence between master and slave is thereby ensured.
摘要翻译：总线到总线接口保持在多处理器计算机系统中操作的主机和从机之间的数据一致性。通过接口连接两条总线。第一条公交车连接了一些自我识别的主人。第二总线连接多个主设备和多个从设备。第二总线没有与第二总线连接的设备可以识别自身的机制。该接口包含一对通过第二总线连接的从设备的寄存器。如果相应的从站代表主站，则一个寄存器存储忙位。第二个寄存器存储用于将任务委托给相应从站的主机的识别码。当一个从机代表一个主机接受一个任务，并命令主机放弃总线时，忙位寄存器将被置位，主机识别寄存器将存储授权主机的识别代码。此后，除非主机识别码是授权主机的主机识别码，否则不允许主机访问从机从机。此外，委托主人将被该从机拒绝访问从机，直到从机完成代表主机接受的任务。通过防止无意的主人在授权主人之前访问从属，避免了传送到错误的主机的无意的数据。从而确保了主机与从机之间的数据一致性。

10. 发明授权

US08266339B2 Direct memory access (DMA) transfer of network interface statistics 有权
公开(公告)号：US08266339B2
公开(公告)日：2012-09-11
申请号：US13344772
申请日：2012-01-06
申请人： Charles E. Narad
发明人： Charles E. Narad
IPC分类号： G06F13/28 , G06F15/173 , G06F15/16
CPC分类号： H04L45/60 , G06F13/28 , H04L43/0888
摘要： In general, in one aspect, the disclosure describes a method that includes maintaining statistics, at a network interface, metering operation of the network interface. The statistics are transferred by direct memory access from the network interface to a memory accessed by at least one processor.

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