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1. 发明授权

US07675104B2 Integrated circuit memory system employing silicon rich layers 有权
标题翻译：集成电路存储系统采用富硅层
公开(公告)号：US07675104B2
公开(公告)日：2010-03-09
申请号：US11461131
申请日：2006-07-31
申请人： Amol Ramesh Joshi , Harpreet Sachar , YouSeok Suh , Shenqing Fang , Chih-Yuh Yang , Lovejeet Singh , David H. Matsumoto , Hidehiko Shiraiwa , Kuo-Tung Chang , Scott A. Bell , Allison Holbrook , Satoshi Torii
发明人： Amol Ramesh Joshi , Harpreet Sachar , YouSeok Suh , Shenqing Fang , Chih-Yuh Yang , Lovejeet Singh , David H. Matsumoto , Hidehiko Shiraiwa , Kuo-Tung Chang , Scott A. Bell , Allison Holbrook , Satoshi Torii
IPC分类号： H01L21/8247
CPC分类号： H01L27/11568 , H01L21/3081 , H01L21/76224 , H01L27/115 , H01L29/66833
摘要： An integrated circuit memory system that includes: providing a substrate; forming a silicon rich charge storage layer over the substrate; forming a first isolation trench through the silicon rich charge storage layer in a first direction; and forming a second isolation trench through the silicon rich charge storage layer in a second direction.
摘要翻译：一种集成电路存储器系统，包括：提供衬底; 在所述衬底上形成富硅电荷存储层; 通过富硅电荷存储层沿第一方向形成第一隔离沟槽; 以及在第二方向上通过富硅电荷存储层形成第二隔离沟槽。

2. 发明申请

US20080023751A1 INTEGRATED CIRCUIT MEMORY SYSTEM EMPLOYING SILICON RICH LAYERS 有权
标题翻译：集成电路记忆系统采用硅胶层
公开(公告)号：US20080023751A1
公开(公告)日：2008-01-31
申请号：US11461131
申请日：2006-07-31
申请人： Amol Ramesh Joshi , Harpreet Sachar , YouSeok Suh , Shenqing Fang , Chih-Yuh Yang , Lovejeet Singh , David H. Matsumoto , Hidehiko Shiraiwa , Kuo-Tung Chang , Scott A. Bell , Allison Holbrook , Satoshi Torii
发明人： Amol Ramesh Joshi , Harpreet Sachar , YouSeok Suh , Shenqing Fang , Chih-Yuh Yang , Lovejeet Singh , David H. Matsumoto , Hidehiko Shiraiwa , Kuo-Tung Chang , Scott A. Bell , Allison Holbrook , Satoshi Torii
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L21/3081 , H01L21/76224 , H01L27/115 , H01L29/66833
摘要： An integrated circuit memory system that includes: providing a substrate; forming a silicon rich charge storage layer over the substrate; forming a first isolation trench through the silicon rich charge storage layer in a first direction; and forming a second isolation trench through the silicon rich charge storage layer in a second direction.
摘要翻译：一种集成电路存储器系统，包括：提供衬底; 在所述衬底上形成富硅电荷存储层; 通过富硅电荷存储层沿第一方向形成第一隔离沟槽; 以及在第二方向上通过富硅电荷存储层形成第二隔离沟槽。

3. 发明授权

US08642441B1 Self-aligned STI with single poly for manufacturing a flash memory device 有权
标题翻译：自对准STI与单个poly制造闪存设备
公开(公告)号：US08642441B1
公开(公告)日：2014-02-04
申请号：US11639667
申请日：2006-12-15
申请人： Tim Thurgate , Shenqing Fang , Kuo-Tung Chang , YouSeok Suh , Meng Ding , Hidehiko Shiraiwa , Amol Joshi , Harpreet Sachar , David Matsumoto , Lovejeet Singh , Chih-Yuh Yang
发明人： Tim Thurgate , Shenqing Fang , Kuo-Tung Chang , YouSeok Suh , Meng Ding , Hidehiko Shiraiwa , Amol Joshi , Harpreet Sachar , David Matsumoto , Lovejeet Singh , Chih-Yuh Yang
IPC分类号： H01L21/76
CPC分类号： H01L27/11563 , H01L21/28282 , H01L21/76232 , H01L21/823481 , H01L27/11568 , H01L29/66833
摘要： A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.
摘要翻译：公开了一种用于制造具有自对准陷阱层和圆形有源区域拐角的存储器件的方法。在本发明中，在形成电荷捕获层和顶层之前进行STI工艺。 STI过程之后立即暴露有源区域的尖角。因为这些尖角在这个时候被曝光，所以它们可以通过任何数量的已知的四舍五入技术进行四舍五入。四舍五入改善了存储设备的性能特征。在舍入处理之后，电荷捕获结构和其它层可以通过自对准工艺形成。

4. 发明申请

US20080142874A1 INTEGRATED CIRCUIT SYSTEM WITH IMPLANT OXIDE 审中-公开
标题翻译：具有氧化铟的集成电路系统
公开(公告)号：US20080142874A1
公开(公告)日：2008-06-19
申请号：US11611860
申请日：2006-12-16
申请人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Hidehiko Shiraiwa , Takayuki Maruyama , Kuo-Tung Chang , YouSeok Suh , Amol Ramesh Joshi , Harpreet Sachar , Simon Siu-Sing Chan
发明人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Hidehiko Shiraiwa , Takayuki Maruyama , Kuo-Tung Chang , YouSeok Suh , Amol Ramesh Joshi , Harpreet Sachar , Simon Siu-Sing Chan
IPC分类号： H01L29/792 , H01L21/3205
CPC分类号： H01L29/792 , H01L29/66833
摘要： A method for forming an integrated circuit system is provided including forming a substrate; forming a stack over the substrate, the stack having a sidewall and formed from a charge trap layer and a semi-conducting layer; and slot plane antenna oxidizing the stack for forming a protection enclosure having a protection layer along the sidewall.
摘要翻译：提供一种用于形成集成电路系统的方法，包括：形成衬底; 在衬底上形成堆叠，所述堆叠具有侧壁并由电荷陷阱层和半导体层形成; 以及缝隙平面天线，用于氧化该叠层以形成具有沿该侧壁的保护层的保护罩。

5. 发明申请

US20080150011A1 INTEGRATED CIRCUIT SYSTEM WITH MEMORY SYSTEM 审中-公开
标题翻译：具有存储器系统的集成电路系统
公开(公告)号：US20080150011A1
公开(公告)日：2008-06-26
申请号：US11958646
申请日：2007-12-18
申请人： Simon Siu-Sing Chan , Lei Xue , YouSeok Suh , Amol Ramesh Joshi , Hidehiko Shiraiwa , Harpreet Sachar , Kuo-Tung Chang , Connie Pin Chin Wang , Paul R. Besser , Shenqing Fang , Meng Ding , Takashi Orimoto , Wei Zheng , Fred TK Cheung
发明人： Simon Siu-Sing Chan , Lei Xue , YouSeok Suh , Amol Ramesh Joshi , Hidehiko Shiraiwa , Harpreet Sachar , Kuo-Tung Chang , Connie Pin Chin Wang , Paul R. Besser , Shenqing Fang , Meng Ding , Takashi Orimoto , Wei Zheng , Fred TK Cheung
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： A method for forming an integrated circuit system is provided including forming a substrate having a core region and a periphery region, forming a charge storage stack over the substrate in the core region, forming a gate stack with a stack header having a metal portion over the substrate in the periphery region, and forming a memory system with the stack header over the charge storage stack.
摘要翻译：提供一种用于形成集成电路系统的方法，包括形成具有芯区域和周边区域的衬底，在芯区域中的衬底上形成电荷存储堆叠，形成具有堆叠集管的栅极堆叠，堆叠集束具有金属部分衬底，并且在电荷存储堆叠上形成具有堆叠头的存储器系统。

6. 发明申请

US20080083946A1 MEMORY CELL SYSTEM WITH CHARGE TRAP 有权
标题翻译：带有电荷捕获的存储单元系统
公开(公告)号：US20080083946A1
公开(公告)日：2008-04-10
申请号：US11539984
申请日：2006-10-10
申请人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Takayuki Maruyama , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , YouSeok Suh , Harpreet Sachar
发明人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Takayuki Maruyama , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , YouSeok Suh , Harpreet Sachar
IPC分类号： H01L29/792 , H01L21/8238
CPC分类号： H01L29/792 , H01L21/28273 , H01L27/115 , H01L27/11568
摘要： A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, and slot plane antenna plasma oxidizing the charge trap layer for forming a second insulator layer.
摘要翻译：提供了一种存储单元系统，包括在半导体衬底上形成第一绝缘体层，在第一绝缘体层上形成电荷陷阱层，以及缝隙平面天线等离子体氧化用于形成第二绝缘体层的电荷陷阱层。

7. 发明授权

US08143661B2 Memory cell system with charge trap 有权
标题翻译：带电荷陷阱的记忆体系统
公开(公告)号：US08143661B2
公开(公告)日：2012-03-27
申请号：US11539984
申请日：2006-10-10
申请人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Takayuki Maruyama , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , YouSeok Suh , Harpreet Sachar
发明人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Takayuki Maruyama , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , YouSeok Suh , Harpreet Sachar
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28273 , H01L27/115 , H01L27/11568
摘要： A memory cell system is provided including a first insulator layer over a semiconductor substrate, a charge trap layer over the first insulator layer, and slot where the charge trap layer includes a second insulator layer having the characteristic of being grown.
摘要翻译：提供一种存储单元系统，包括半导体衬底上的第一绝缘体层，第一绝缘体层上的电荷陷阱层和电荷陷阱层包括具有生长特性的第二绝缘体层的槽。

8. 发明申请

US20080150000A1 MEMORY SYSTEM WITH SELECT GATE ERASE 审中-公开
标题翻译：具有选择栅格擦除的存储器系统
公开(公告)号：US20080150000A1
公开(公告)日：2008-06-26
申请号：US11614839
申请日：2006-12-21
申请人： YouSeok Suh , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , Shenqing Fang
发明人： YouSeok Suh , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , Shenqing Fang
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L29/792 , H01L29/40117
摘要： A memory system includes a substrate, forming a first insulator over the substrate, forming a charge trap layer, having a composition for setting a predetermined electrical charge level, over the first insulator, and forming a second insulator over the charge trap layer.
摘要翻译：存储器系统包括：衬底，在衬底上形成第一绝缘体，在第一绝缘体上形成具有用于设定预定电荷水平的组成的电荷陷阱层，以及在电荷陷阱层上形成第二绝缘体。

9. 发明申请

US20080096357A1 METHOD FOR MANUFACTURING A MEMORY DEVICE 审中-公开
标题翻译：用于制造存储器件的方法
公开(公告)号：US20080096357A1
公开(公告)日：2008-04-24
申请号：US11551535
申请日：2006-10-20
申请人： Youseok Suh , Hidehiko Shiraiwa , Allison Holbrook , Angela Hui , Kuo-Tung Chang
发明人： Youseok Suh , Hidehiko Shiraiwa , Allison Holbrook , Angela Hui , Kuo-Tung Chang
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568
摘要： A method for manufacturing a memory device that includes using a gap-filling material that inhibits charge coupling between memory devices. A semiconductor material is provided that has an active region and an isolation region. A charge trapping structure is formed over the active region and a layer of semiconductor material is formed over the charge trapping structure and the isolation region. A masking structure having sidewalls is formed on the layer of semiconductor material. Spacers are formed adjacent the sidewalls and the layer of semiconductor material is etched to form one or more conductive strips having opposing sides. The one or more conductive strips are formed over the active region. A dielectric material is formed adjacent to the opposing sides of each conductive strip. The dielectric material serves as a gap-filling material. A layer of semiconductor material is formed over the one or more conductive strips.
摘要翻译：一种用于制造存储器件的方法，其包括使用禁止存储器件之间的电荷耦合的间隙填充材料。提供了具有有源区和隔离区的半导体材料。在有源区上形成电荷俘获结构，在电荷俘获结构和隔离区上形成一层半导体材料。在半导体材料层上形成具有侧壁的掩模结构。间隔件邻近侧壁形成，并且半导体材料层被蚀刻以形成具有相对侧面的一个或多个导电条。一个或多个导电条形成在有源区上。在每个导电带的相对侧附近形成电介质材料。介电材料用作间隙填充材料。在一个或多个导电条上形成半导体材料层。

10. 发明授权

US07906395B2 Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications 有权
标题翻译：通过使用非保形膜的自对准图案化方法，并对闪存和其他半导体应用进行回蚀
公开(公告)号：US07906395B2
公开(公告)日：2011-03-15
申请号：US12891481
申请日：2010-09-27
申请人： Shenqing Fang , Kuo-Tung Chang , Tim Thurgate , YouSeok Suh , Allison Holbrook
发明人： Shenqing Fang , Kuo-Tung Chang , Tim Thurgate , YouSeok Suh , Allison Holbrook
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and a void at the top of the STI trench. An etch is performed on the pinch-off oxide and the thin oxide on the trapping layer on the STI oxide. The trapping layer is then partially etched between the core cells. A dip-off of the oxide on the trapping layer is performed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide and thus isolate the trap layer.
摘要翻译：公开了一种用于制造具有自对准陷阱层的存储器件的方法，其被优化用于缩放。在本发明中，在电荷捕获层上沉积非保形氧化物，以在芯源极/漏极区域的顶部上形成厚的氧化物，并在STI沟槽的顶部形成空隙。对STI氧化物上的捕获层上的夹断氧化物和薄氧化物进行蚀刻。然后在核心单元之间部分地蚀刻捕获层。进行捕获层上的氧化物的偏移。并形成顶部氧化物。顶部氧化物将剩余的陷阱层转化为氧化物，从而隔离陷阱层。

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