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1. 发明授权

US06927129B1 Narrow wide spacer 有权
标题翻译：狭窄的间距
公开(公告)号：US06927129B1
公开(公告)日：2005-08-09
申请号：US10821312
申请日：2004-04-08
申请人： Yu Sun , Kuo-Tung Chang , Angela T. Hui , Shenqing Fang
发明人： Yu Sun , Kuo-Tung Chang , Angela T. Hui , Shenqing Fang
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/105
CPC分类号： H01L29/6656 , H01L27/105 , H01L27/11526 , H01L27/11534
摘要： A method for fabricating a semiconductor device. Specifically, A method of manufacturing a semiconductor device comprising: depositing a first oxide layer over a periphery transistor comprising a gate stack, a drain side sidewall and a source side sidewall and over a core transistor comprising a gate stack, a source side sidewall and a drain side sidewall; etching the first oxide layer wherein a portion of the first oxide layer remains on the source side sidewall and on the drain side sidewall of the periphery transistor and on the source side sidewall and on the drain side sidewall of the core transistor; etching the first oxide layer from the source side sidewall of the core transistor; depositing a second oxide layer over the periphery transistor and the core transistor; and etching the second oxide layer wherein a portion of the second oxide layer remains on the first oxide layer formed on the source side sidewall and on the drain side sidewall of the periphery transistor and wherein the second oxide layer remains on the source side sidewall and on the drain side sidewall of the core transistor.
摘要翻译：一种半导体器件的制造方法。具体地说，一种制造半导体器件的方法，包括：在包括栅极堆叠，漏极侧壁和源极侧壁的外围晶体管上沉积第一氧化物层，以及包括栅极堆叠，源极侧壁和排水侧壁蚀刻第一氧化物层，其中第一氧化物层的一部分保留在外围晶体管的源极侧壁和漏极侧壁上，并且在芯晶体管的源极侧壁和漏极侧侧壁上残留; 从芯晶体管的源极侧壁蚀刻第一氧化物层; 在外围晶体管和芯晶体管上沉积第二氧化物层; 以及蚀刻所述第二氧化物层，其中所述第二氧化物层的一部分保留在形成在所述外围晶体管的源极侧壁和漏极侧壁上的第一氧化物层上，并且其中所述第二氧化物层保留在所述源侧侧壁上，芯晶体管的漏极侧壁。

2. 发明授权

US07301193B2 Structure and method for low Vss resistance and reduced DIBL in a floating gate memory cell 有权
标题翻译：浮动栅极存储单元中低Vss电阻和减少DIBL的结构和方法
公开(公告)号：US07301193B2
公开(公告)日：2007-11-27
申请号：US10762445
申请日：2004-01-22
申请人： Shenqing Fang , Timothy Thurgate , Kuo-Tung Chang , Richard Fastow , Angela T. Hui , Kazuhiro Mizutani , Kelwin Ko , Hiroyuki Kinoshita , Yu Sun , Hiroyuki Ogawa
发明人： Shenqing Fang , Timothy Thurgate , Kuo-Tung Chang , Richard Fastow , Angela T. Hui , Kazuhiro Mizutani , Kelwin Ko , Hiroyuki Kinoshita , Yu Sun , Hiroyuki Ogawa
IPC分类号： H01L29/788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/743 , H01L29/41766 , H01L29/66636
摘要： According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate memory cell further comprises a recess formed in the substrate adjacent to the stacked gate structure, where the recess has a sidewall, a bottom, and a depth. According to this exemplary embodiment, the floating gate memory cell further comprises a source situated adjacent to the sidewall of the recess and under the stacked gate structure. The floating gate memory cell further comprises a Vss connection region situated under the bottom of the recess and under the source, where the Vss connection region is connected to the source. The Vss connection region being situated under the bottom of the recess causes the source to have a reduced lateral diffusion in the channel region.
摘要翻译：根据一个示例性实施例，浮动栅极存储器单元包括位于衬底上并位于衬底中的沟道区域上方的堆叠栅极结构。浮动栅极存储单元还包括形成在衬底中的与堆叠的栅极结构相邻的凹部，其中凹部具有侧壁，底部和深度。根据该示例性实施例，浮动栅极存储单元还包括位于与凹部的侧壁相邻并位于堆叠栅极结构下方的源极。浮动栅极存储单元还包括位于凹部底部下方和源极之下的Vss连接区域，其中Vss连接区域连接到源极。位于凹部底部下方的Vss连接区使得源在通道区域中具有减小的横向扩散。

3. 发明授权

US06808992B1 Method and system for tailoring core and periphery cells in a nonvolatile memory 有权
标题翻译：用于定制非易失性存储器中的核心和外围单元的方法和系统
公开(公告)号：US06808992B1
公开(公告)日：2004-10-26
申请号：US10150240
申请日：2002-05-15
申请人： Kelwin Ko , Shenqing Fang , Angela T. Hui , Hiroyuki Kinoshita , Wenmei Li , Yu Sun , Hiroyuki Ogawa
发明人： Kelwin Ko , Shenqing Fang , Angela T. Hui , Hiroyuki Kinoshita , Wenmei Li , Yu Sun , Hiroyuki Ogawa
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11536 , H01L29/6656
摘要： A method and system for providing a semiconductor device are described. The semiconductor device includes a substrate, a core and a periphery. The core includes a plurality of core gate stacks having a first plurality of edges, while the periphery a plurality of periphery gate stacks having a second plurality of edges. The method and system include providing a plurality of core spacers, a plurality of periphery spacers, a plurality of core sources and a plurality of conductive regions. The core spacers reside at the first plurality of edges and have a thickness. The periphery spacers reside at the second plurality of edges and have a second thickness greater than the first thickness. The core sources reside between the plurality of core gate stacks. The conductive regions are on the plurality of core sources. This method allows different thicknesses of the spacers to be formed in the core and the periphery so that the spacers can be tailored to the different requirements of the core and periphery.
摘要翻译：描述了一种用于提供半导体器件的方法和系统。半导体器件包括衬底，芯和周边。芯包括具有第一多个边缘的多个核心栅极叠层，而周边具有多个具有第二多个边缘的外围栅极堆叠。该方法和系统包括提供多个芯间隔件，多个外围间隔件，多个芯源和多个导电区域。芯间隔件位于第一多个边缘处并且具有厚度。外围间隔件位于第二多个边缘处并且具有大于第一厚度的第二厚度。核心源位于多个核心门堆栈之间。导电区域在多个核心源上。该方法允许不同厚度的间隔件形成在芯部和周边中，使得间隔件可以根据芯部和周边的不同要求进行调整。

4. 发明申请

US20050164450A1 Structure and method for low Vss resistance and reduced dibl in a floating gate memory cell 有权
标题翻译：浮动栅极存储单元的低Vss电阻和二极管的结构和方法
公开(公告)号：US20050164450A1
公开(公告)日：2005-07-28
申请号：US10762445
申请日：2004-01-22
申请人： Shenqing Fang , Timothy Thurgate , Kuo-Tung Chang , Richard Fastow , Angela Hui , Kazuhiro Mizutani , Kelwin Ko , Hiroyuki Kinoshita , Yu Sun , Hiroyuki Ogawa
发明人： Shenqing Fang , Timothy Thurgate , Kuo-Tung Chang , Richard Fastow , Angela Hui , Kazuhiro Mizutani , Kelwin Ko , Hiroyuki Kinoshita , Yu Sun , Hiroyuki Ogawa
IPC分类号： H01L21/28 , H01L21/336 , H01L21/74 , H01L29/417 , H01L29/788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/743 , H01L29/41766 , H01L29/66636
摘要： According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate memory cell further comprises a recess formed in the substrate adjacent to the stacked gate structure, where the recess has a sidewall, a bottom, and a depth. According to this exemplary embodiment, the floating gate memory cell further comprises a source situated adjacent to the sidewall of the recess and under the stacked gate structure. The floating gate memory cell further comprises a Vss connection region situated under the bottom of the recess and under the source, where the Vss connection region is connected to the source. The Vss connection region being situated under the bottom of the recess causes the source to have a reduced lateral diffusion in the channel region.
摘要翻译：根据一个示例性实施例，浮动栅极存储器单元包括位于衬底上并位于衬底中的沟道区域上方的堆叠栅极结构。浮动栅极存储单元还包括形成在衬底中的与堆叠的栅极结构相邻的凹部，其中凹部具有侧壁，底部和深度。根据该示例性实施例，浮动栅极存储单元还包括位于与凹部的侧壁相邻并位于堆叠栅极结构下方的源极。浮动栅极存储单元还包括位于凹部底部下方和源极之下的Vss连接区域，其中Vss连接区域连接到源极。位于凹部底部下方的Vss连接区使得源在通道区域中具有减小的横向扩散。

5. 发明授权

US06455373B1 Semiconductor device having gate edges protected from charge gain/loss 有权
标题翻译：具有防止电荷增益/损耗的栅极边缘的半导体器件
公开(公告)号：US06455373B1
公开(公告)日：2002-09-24
申请号：US09834419
申请日：2001-04-12
申请人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
发明人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L21/823468 , H01L27/105 , H01L27/11536
摘要： A plurality of core gate stacks and periphery gates on the substrate, each core gate stack and periphery gate having at least one side and first and second protective shoulders formed on said plurality of core gate stacks and periphery gates, such that a dopant can be implanted sequentially into source and drain regions of a substrate supporting the stacks to establish transistors and such that charge migration into said at least one side of the gate stacks during interlayer dielectric (ILD) formation and device metallization is prevented, at least the second shoulder being frabricated from at least one material selected from a group consisting essentially of nitride and silicon oxynitride (SiON).
摘要翻译：在基板上的多个核心栅极叠层和周边栅极，每个芯栅极叠层和周边栅极具有形成在所述多个芯栅极叠层和外围栅极上的至少一个侧面和第一和第二保护肩部，使得掺杂剂可被植入顺序地进入支撑堆叠的衬底的源极和漏极区域以建立晶体管，并且防止在层间电介质（ILD）形成和器件金属化期间电荷迁移到栅极叠层的所述至少一个侧面，至少第二肩部被破坏选自由氮化物和氮氧化硅（SiON）组成的组中的至少一种材料。

6. 发明授权

US06369416B1 Semiconductor device with contacts having a sloped profile 有权
标题翻译：具有倾斜轮廓的触头的半导体器件
公开(公告)号：US06369416B1
公开(公告)日：2002-04-09
申请号：US09404394
申请日：1999-09-23
申请人： Angela T. Hui , Tuan Duc Pham , Mark T. Ramsbey , Yu Sun
发明人： Angela T. Hui , Tuan Duc Pham , Mark T. Ramsbey , Yu Sun
IPC分类号： H01L2976
CPC分类号： H01L27/115 , H01L21/76804
摘要： A method and system for providing a contact in a semiconductor device including a plurality of gates is disclosed. The method and system include providing an insulating layer substantially surrounding at least a portion of the plurality of gates and providing at least one contact within the insulating layer. The contact has a side defining a sloped profile. The sloped profile includes an angle between the side of the contact and a surface of the substrate that is less than approximately eighty-eight degrees.
摘要翻译：公开了一种用于在包括多个栅极的半导体器件中提供接触的方法和系统。该方法和系统包括提供基本上围绕多个栅极的至少一部分的绝缘层，并且在绝缘层内提供至少一个触点。触点具有限定倾斜轮廓的侧面。倾斜轮廓包括接触侧面和基体表面之间的角度小于大约八十八度。

7. 发明授权

US06342415B1 Method and system for providing reduced-sized contacts in a semiconductor device 失效
标题翻译：用于在半导体器件中提供减小尺寸的触点的方法和系统
公开(公告)号：US06342415B1
公开(公告)日：2002-01-29
申请号：US09404395
申请日：1999-09-23
申请人： Angela T. Hui , Tuan Duc Pham , Mark T. Ramsbey , Yu Sun
发明人： Angela T. Hui , Tuan Duc Pham , Mark T. Ramsbey , Yu Sun
IPC分类号： H01L218238
CPC分类号： H01L21/31144 , H01L21/76816 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A method and system for providing a contact in a semiconductor device including a plurality of gates is disclosed. The method and system include providing an insulating layer substantially surrounding at least a portion of the plurality of gates and providing at least one contact within the insulating layer. The at least one contact has a reduced width that is less than approximately 0.28 microns
摘要翻译：公开了一种用于在包括多个栅极的半导体器件中提供接触的方法和系统。该方法和系统包括提供基本上围绕多个栅极的至少一部分的绝缘层，并且在绝缘层内提供至少一个触点。所述至少一个接触件具有小于约0.28微米的减小的宽度

8. 发明授权

US06248627B1 Method for protecting gate edges from charge gain/loss in semiconductor device 有权
标题翻译：在半导体器件中保护栅极边缘免受电荷增益/损耗的方法
公开(公告)号：US06248627B1
公开(公告)日：2001-06-19
申请号：US09376658
申请日：1999-08-18
申请人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
发明人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L21/823468 , H01L27/105 , H01L27/11536
摘要： A method for making a ULSI MOSFET includes covering core gate stacks with a first protective layer, etching away the first layer such that intended source regions of the substrate are exposed, and implanting dopant into the source regions. A second protective layer is then deposited over the first layer and is etched back to conform to the first layer, covering only the sides of the gate stacks, and exposing intended drain regions of the substrate. Dopant is then implanted into the drain regions. During subsequent manufacturing steps including ILD formation and metallization, mobile ions and other process-induced charges are blocked from entering the floating gates of the gate stacks by the protective layers, thereby preventing unwanted charge gain/loss.
摘要翻译：制造ULSI MOSFET的方法包括用第一保护层覆盖芯栅极叠层，蚀刻掉第一层，使得衬底的预期源极区域暴露，并将掺杂剂注入到源极区域中。然后在第一层上沉积第二保护层，并将其回蚀刻以符合第一层，仅覆盖栅极堆叠的侧面，并暴露衬底的预期漏极区域。然后将掺杂剂注入漏区。在包括ILD形成和金属化的后续制造步骤期间，阻止移动离子和其它工艺感应电荷被保护层进入栅极堆叠的浮置栅极，从而防止不必要的电荷增益/损耗。

9. 发明授权

US06475847B1 Method for forming a semiconductor device with self-aligned contacts using a liner oxide layer 有权
标题翻译：使用衬垫氧化物层形成具有自对准触点的半导体器件的方法
公开(公告)号：US06475847B1
公开(公告)日：2002-11-05
申请号：US10109526
申请日：2002-03-27
申请人： Minh Van Ngo , Yu Sun , Fei Wang , Mark T. Ramsbey , Chi Chang , Angela T. Hui , Mark S. Chang
发明人： Minh Van Ngo , Yu Sun , Fei Wang , Mark T. Ramsbey , Chi Chang , Angela T. Hui , Mark S. Chang
IPC分类号： H01L218238
CPC分类号： H01L27/11521 , H01L21/76829 , H01L21/76897 , H01L27/115 , H01L2924/3011
摘要： A method for shrinking a semiconductor device and minimizing auto-doping problem is disclosed. An etch stop layer is eliminated and is replaced with a consumable liner oxide layer so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. The liner oxide layer is formed directly over a substrate and in contact with stacked gate structures, sidewall spacers, and sources and drains formed on the substrate, and serves as an auto-doping barrier for the dielectric layer to prevent boron and phosphorous formed in the dielectric layer from auto-doping into the sources and drains.
摘要翻译：公开了一种缩小半导体器件并最小化自动掺杂问题的方法。蚀刻停止层被消除并且被可消耗的衬垫氧化物层代替，使得该器件的层叠栅极结构可以被更靠近地放置在一起，从而允许器件收缩。衬垫氧化物层直接形成在衬底上并与堆叠的栅极结构，侧壁间隔物以及形成在衬底上的源极和漏极接触，并且用作电介质层的自动掺杂势垒，以防止形成在衬底中的硼和磷电介质层自动掺入源和漏极。

10. 发明授权

US06232646B1 Shallow trench isolation filled with thermal oxide 失效
标题翻译：浅沟隔离填充热氧化物
公开(公告)号：US06232646B1
公开(公告)日：2001-05-15
申请号：US09082607
申请日：1998-05-20
申请人： Yu Sun , Angela T. Hui , Yue-Song He , Tatsuya Kajita , Mark Chang , Chi Chang , Hung-Sheng Chen
发明人： Yu Sun , Angela T. Hui , Yue-Song He , Tatsuya Kajita , Mark Chang , Chi Chang , Hung-Sheng Chen
IPC分类号： H01L2900
CPC分类号： H01L21/7621 , H01L21/76232
摘要： A semiconductor apparatus and method for producing shallow trench isolation. The method includes the steps providing a semiconductor substrate member fabricated having a thin barrier oxide layer on which are fabricated a plurality of spaced apart silicon nitride pads. The regions between the spaced apart nitride pads delineate U-shaped regions for forming shallow isolation trenches and are layered with silicon oxide and polysilicon. The U-shaped regions provide a buffer region of oxide and polysilicon material adjacent opposing silicon nitride pads that prevent erosion of the nitride during etch formation of the isolation trench. The polysilicon is further etched to form a wider, second U-shaped region having sloped sidewalls that provide opposing spacer-forming buffer material that facilitates forming a V-shaped isolation trench region into the semiconductor substrate member a predetermined depth without eroding the silicon nitride pads. The V-shaped trench is subsequently filled with silicon dioxide that is grown by a hot thermal oxide process. The upper portion of the V-shaped isolation trench may be further filled with deposited silicon dioxide followed by a chemical mechanical polishing process.
摘要翻译：一种用于产生浅沟槽隔离的半导体装置和方法。该方法包括提供制造具有薄的阻挡氧化物层的半导体衬底构件的步骤，在其上制造多个间隔开的氮化硅衬垫。间隔开的氮化物衬垫之间的区域划定用于形成浅隔离沟槽的U形区域并且与氧化硅和多晶硅层叠。 U形区域提供邻近相对的氮化硅焊盘的氧化物和多晶硅材料的缓冲区，其在隔离沟槽的蚀刻形成期间防止氮化物的侵蚀。多晶硅被进一步蚀刻以形成更宽的第二U形区域，其具有倾斜的侧壁，其提供相对的间隔物形成缓冲材料，其有利于在不侵蚀氮化硅焊盘的情况下在半导体衬底构件中形成预定深度的V形隔离沟槽区域。随后，V形沟槽填充二氧化硅，二氧化硅通过热的热氧化工艺生长。 V形隔离沟槽的上部可以进一步填充沉积的二氧化硅，随后进行化学机械抛光工艺。

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