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1. 发明申请

US20080065788A1 System and method for producing high volume flash memory cards 审中-公开
标题翻译：用于生产大容量闪存卡的系统和方法
公开(公告)号：US20080065788A1
公开(公告)日：2008-03-13
申请号：US11979102
申请日：2007-10-31
申请人： David Chow , Sidney Young , Frank Yu , Abraham Ma , Ming-Shiang Shen
发明人： David Chow , Sidney Young , Frank Yu , Abraham Ma , Ming-Shiang Shen
IPC分类号： G06F13/10
CPC分类号： G06F12/1416 , G06F21/32 , G06F21/78 , G07C9/00087 , G07C2009/00095 , H01R13/629
摘要： A system for producing high volume flash memory cards includes a processing unit, a PC interface for connecting to an external PC, a PC drive circuit connected to the PC interface and the processing unit, a card interface for connecting to an external flash memory card, and a card drive circuit connected to the card interface and the processing unit. The PC drive circuit realizes communication between the PC and the processing unit. The card drive circuit realizes communication between the flash memory card and the processing unit. The processing unit receives command or data from the PC interface, and sends card re-initialization command or data to the flash memory card via the card interface.
摘要翻译：一种用于生产大容量闪存卡的系统包括处理单元，用于连接到外部PC的PC接口，连接到PC接口的PC驱动电路和处理单元，用于连接到外部闪存卡的卡接口，以及连接到卡接口和处理单元的卡驱动电路。 PC驱动电路实现PC与处理单元之间的通信。卡驱动电路实现闪存卡和处理单元之间的通信。处理单元从PC接口接收命令或数据，并通过卡接口将卡重新初始化命令或数据发送到闪存卡。

2. 发明申请

US20080071963A1 Express card with extended USB interface 审中-公开
标题翻译：具有扩展USB接口的Express卡
公开(公告)号：US20080071963A1
公开(公告)日：2008-03-20
申请号：US11979103
申请日：2007-10-31
申请人： David Chow , Sidney Young , Charles Lee , Abraham Ma , Ming-Shiang Shen
发明人： David Chow , Sidney Young , Charles Lee , Abraham Ma , Ming-Shiang Shen
IPC分类号： G06F13/20 , G06F12/02
CPC分类号： G06F13/409 , G06F2213/0026 , G06F2213/0042 , Y02D10/14 , Y02D10/151
摘要： An ExpressCard having USB connection has a card case having two opposite first and second end portions and two opposite lateral portions. A card connector is formed at the first end portion of the card case and having a USB interface. Flash chips are implemented in the card case. A USB flash controller implemented in the card case and connected between the USB interface and the flash chips in order to provide a data access to the flash chips through the USB interface. A USB socket, in form factors of Mini-USB or Extended Mini-connector-type, is implemented in the card case and connected to the USB flash controller in order to provide a data access to the one or more flash chips therethrough. An extended Universal-Serial Bus (EUSB) host enters a suspend mode rather than poll an ExpressCard that is busy performing a memory or other operation, thereby saving power.
摘要翻译：具有USB连接的ExpressCard具有具有两个相对的第一和第二端部和两个相对的横向部分的卡盒。卡连接器形成在卡盒的第一端部并且具有USB接口。闪存芯片在卡盒中实现。 USB闪存控制器实现在卡盒中并连接在USB接口和闪存芯片之间，以通过USB接口提供对闪存芯片的数据访问。一个USB插座，以Mini-USB或扩展迷你连接器类型的形式被实现在卡盒中并连接到USB闪存控制器，以便提供对一个或多个闪存芯片的数据访问。扩展的通用串行总线（EUSB）主机进入挂起模式，而不是轮询正忙于执行内存或其他操作的ExpressCard，从而节省电量。

3. 发明申请

US20080052439A1 Portable Data Exchanger with Extended USB Interface 审中-公开
标题翻译：带扩展USB接口的便携式数据交换器
公开(公告)号：US20080052439A1
公开(公告)日：2008-02-28
申请号：US11928604
申请日：2007-10-30
申请人： Sidney YOUNG , David Chow
发明人： Sidney YOUNG , David Chow
IPC分类号： G06F13/14
CPC分类号： G06F13/4027 , G06K19/077 , G06K19/07732 , G06K19/07741
摘要： The present invention discloses a portable data exchanger with extended USB interface. One portable data exchanger of the present invention can exchange data with another portable data exchanger of the same design connected thereto without using a computer. Further, the portable data exchanger with extended USB interface of the present invention is designed to have the hub-supporting USB OTG capability. Thus, the portable data exchanger with extended USB interface of the present invention not only can function as a slave to be controlled by a standard non-OTG USB host device but also can function as a host to control a standard non-OTG USB peripheral device. To be also compatible with the next generation devices, the present invention also proposes a portable data exchanger with extended USB interface using dual-personality extended USB plug and socket with PCI-express or SATA extensions.
摘要翻译：本发明公开了一种具有扩展USB接口的便携式数据交换器。本发明的一个便携式数据交换器可以与其连接的相同设计的另一便携式数据交换机交换数据，而无需使用计算机。此外，本发明的具有扩展USB接口的便携式数据交换机被设计为具有集线器支持的USB OTG能力。因此，本发明的具有扩展USB接口的便携式数据交换器不仅可以作为由标准非OTG USB主机设备控制的从设备，而且可以用作控制标准非OTG USB外围设备的主机。为了兼容下一代设备，本发明还提出了一种具有扩展USB接口的便携式数据交换器，其使用具有PCI-express或SATA扩展的双人格扩展的USB插头和插座。

4. 发明授权

US07968435B1 Method and device for growing pseudomorphic AlInAsSb on InAs 失效
标题翻译：用于在InAs上生长伪晶AlInAsSb的方法和装置
公开(公告)号：US07968435B1
公开(公告)日：2011-06-28
申请号：US12491004
申请日：2009-06-24
申请人： Peter Deelman , Ken Elliott , David Chow
发明人： Peter Deelman , Ken Elliott , David Chow
IPC分类号： H01L21/20
CPC分类号： H01L21/02395 , H01L21/02463 , H01L21/02466 , H01L21/02507 , H01L21/02546 , H01L21/02549 , H01L21/02631
摘要： A semiconductor device and method are being disclosed. The semiconductor device discloses an InAs layer, a plurality of group III-V ternary layers supported by the InAs layer, and a plurality of group III-V quarternary layers supported by the InAs layer, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer. The method discloses providing an InAs layer, growing a plurality of group III-V ternary layers, and growing a plurality of group III-V quarternary layers, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer and are supported by the InAs layer.
摘要翻译：正在公开半导体器件和方法。半导体器件公开了InAs层，由InAs层支撑的多个III-V族三元层和由InAs层支撑的多个III-V族第三层，其中III-V族三元层与彼此由一个III-V组单独的三层组成。该方法公开了提供InAs层，生长多个III-V族三元层，并生长多个III-V族第三层，其中III-V族三元层通过单组III- V第三层，并由InAs层支持。

5. 发明授权

US07598158B1 Method and device for growing pseudomorphic AlInAsSb on InAs 失效
标题翻译：用于在InAs上生长伪晶AlInAsSb的方法和装置
公开(公告)号：US07598158B1
公开(公告)日：2009-10-06
申请号：US11447338
申请日：2006-06-05
申请人： Peter Deelman , Ken Elliott , David Chow
发明人： Peter Deelman , Ken Elliott , David Chow
IPC分类号： H01L21/20
CPC分类号： H01L21/02395 , H01L21/02463 , H01L21/02466 , H01L21/02507 , H01L21/02546 , H01L21/02549 , H01L21/02631
摘要： A semiconductor device and method are being disclosed. The semiconductor device discloses an InAs layer, a plurality of group III-V ternary layers supported by the InAs layer, and a plurality of group III-V quarternary layers supported by the InAs layer, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer. The method discloses providing an InAs layer, growing a plurality of group III-V ternary layers, and growing a plurality of group III-V quarternary layers, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer and are supported by the InAs layer.
摘要翻译：正在公开半导体器件和方法。半导体器件公开了InAs层，由InAs层支撑的多个III-V族三元层和由InAs层支撑的多个III-V族第三层，其中III-V族三元层与彼此由一个III-V组单独的三层组成。该方法公开了提供InAs层，生长多个III-V族三元层，并生长多个III-V族第三层，其中III-V族三元层通过单组III- V第三层，并由InAs层支持。

6. 发明申请

US20080034154A1 Multi-Channel Flash Module with Plane-Interleaved Sequential ECC Writes and Background Recycling to Restricted-Write Flash Chips 有权
标题翻译：具有平面交错顺序ECC的多通道闪存模块写入和背景回收限制写入闪存芯片
公开(公告)号：US20080034154A1
公开(公告)日：2008-02-07
申请号：US11871627
申请日：2007-10-12
申请人： Charles Lee , Abraham Ma , Frank Yu , David Chow , Ming-Shiang Shen
发明人： Charles Lee , Abraham Ma , Frank Yu , David Chow , Ming-Shiang Shen
IPC分类号： G06F12/00
CPC分类号： G06F12/0607 , G06F12/0246 , G06F2212/7201 , G06F2212/7203 , G06F2212/7205 , G06F2212/7208 , G11C16/0408 , G11C2211/5649
摘要： A RAM mapping table is restored from flash memory using plane, block, and page addresses generated by a physical sequential address counter. The RAM mapping table is restored following a plane-interleaved sequence generated by the physical sequential address counter using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. The physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of 0, 1, 4096, 4097, 2, 3, 4098, 4099, etc. in the four planes of flash memory. Background recycling and ECC writes are also performed.
摘要翻译：使用由物理顺序地址计数器生成的平面，块和页面地址从闪存中恢复RAM映射表。 RAM映射表在使用从逻辑块索引的最低位提取的交错比特的物理顺序地址计数器产生的平面交织序列之后恢复。这些平面交织位分为LSB和MSB，LSB与MSB之间的中间物理块位。物理顺序地址计数器通过在中间物理块位之前递增平面交织比特，然后将MSB重定位到中间物理块比特之上来生成物理块号。这导致在闪存的四个平面中以0,1,4096,4097,2,3,40,40,4099等的低高序列访问块。还执行后台回收和ECC写入。

7. 发明申请

US20080034153A1 Flash Module with Plane-Interleaved Sequential Writes to Restricted-Write Flash Chips 有权
标题翻译：闪存模块与平面交错顺序写入限制写入闪存芯片
公开(公告)号：US20080034153A1
公开(公告)日：2008-02-07
申请号：US11871011
申请日：2007-10-11
申请人： Charles Lee , Frank Yu , Abraham Ma , David Chow , Ming-Shiang Shen
发明人： Charles Lee , Frank Yu , Abraham Ma , David Chow , Ming-Shiang Shen
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0607 , G06F2212/7201 , G06F2212/7208 , G11C11/5621 , G11C16/0408
摘要： A flash memory controller on a PCIE bus controls flash-memory modules on a flash bus. The flash-memory modules are plane-interleaved using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. A physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of 0, 1, 4096, 4097, 2, 3, 4098, 4099, etc. in the four planes of flash memory. A RAM physical page valid table tracks valid pages in the four planes, while a RAM mapping table stores the plane, block, and page addresses for logical sectors generated by the physical sequential address counter.
摘要翻译： PCIE总线上的闪存控制器控制闪存总线上的闪存模块。闪存模块使用从逻辑块索引的最低位提取的交错比特进行平面交织。这些平面交织位分为LSB和MSB，LSB与MSB之间的中间物理块位。物理顺序地址计数器通过在中间物理块比特之前递增平面交织比特，然后将MSB重新定位到中间物理块比特之上来生成物理块号。这导致在闪存的四个平面中以0,1,4096,4097,2,3,40,40,4099等的低高序列访问块。 RAM物理页有效表跟踪四个平面中的有效页面，而RAM映射表存储由物理顺序地址计数器生成的逻辑扇区的平面，块和页面地址。

8. 发明申请

US20080016269A1 Flash / Phase-Change Memory in Multi-Ring Topology Using Serial-Link Packet Interface 失效
标题翻译：使用串行链路分组接口的多环拓扑中的闪存/相变存储器
公开(公告)号：US20080016269A1
公开(公告)日：2008-01-17
申请号：US11773827
申请日：2007-07-05
申请人： David Chow , Charles Lee , Frank Yu
发明人： David Chow , Charles Lee , Frank Yu
IPC分类号： G06F12/00
CPC分类号： G06F13/1684 , G11C13/0004 , G11C16/102 , G11C2216/30
摘要： A multi-ring memory controller sends request packets to multiple rings of serial flash-memory chips. Each of the multiple rings has serial flash-memory chips with serial links in a uni-directional ring. Each serial flash-memory chip has a bypassing transceiver with a device ID checker that bypasses serial packets to a clock re-synchronizer and bypass logic for retransmission to the next device in the ring, or extracts the serial packet to the local device when an ID match occurs. Serial packets pass through all devices in the ring during one round-trip transaction from the controller. The average latency of one round is constant for all devices on the ring, reducing data-dependent performance, since the same packet latency occurs regardless of the data location on the ring. The serial links can be a Peripheral Component Interconnect (PCI) Express bus. Packets have modified-PCI-Express headers that define the packet type and data-payload length.
摘要翻译：多环存储器控制器将请求数据包发送到串行闪存芯片的多个环。多个环中的每个环都具有串行闪存芯片，其具有单向环中的串行链路。每个串行闪存芯片都具有一个旁路收发器，其中设备ID检查器将串行数据包绕过时钟重新同步器，并且旁路逻辑用于重传到环中的下一个设备，或者当ID为ID时将串行数据包提取给本地设备匹配发生。在来自控制器的一次往返事务期间，串行数据包通过环中的所有设备。由于相同的数据包延迟发生，环路上的所有设备的平均延迟都是恒定的，从而降低了数据相关性能，无论环的数据位置如何。串行链路可以是外围组件互连（PCI）Express总线。数据包已经修改了PCI-Express头，定义了数据包类型和数据有效负载长度。

9. 发明申请

US20070276988A1 Page and Block Management Algorithm for NAND Flash 有权
标题翻译： NAND Flash的页面和块管理算法
公开(公告)号：US20070276988A1
公开(公告)日：2007-11-29
申请号：US11779804
申请日：2007-07-18
申请人： Jianjun Luo , Chris Tsu , Charles Lee , David Chow
发明人： Jianjun Luo , Chris Tsu , Charles Lee , David Chow
IPC分类号： G06F13/28
CPC分类号： G06F12/0246 , G06F12/0292 , G06F13/28 , G06F2212/1036 , G06F2212/7211
摘要： A flash controller is adapted to communicate with a host and the flash memory and including volatile memory configured to store a page-block table of logical addresses addressable by the physical addresses. The logical addresses are used by the controller to identify the blocks. The table has an address mapping table and a property value table, the property value table includes property values, each of the property values being increased in value every time a block is written up to a maximum value and being associated with a block of a predetermined group of blocks and indicative of the number of times a block has been written, the property values corresponding to the logical addresses of the address mapping table, wherein the maximum number the property values of the predetermined group of blocks take on is adjustably different than the maximum number the property values of another group of blocks.
摘要翻译：闪存控制器适于与主机和闪存进行通信，并且包括被配置为存储可通过物理地址寻址的逻辑地址的页块表的易失性存储器。逻辑地址由控制器用于识别块。该表具有地址映射表和属性值表，属性值表包括属性值，每当一个块写入最大值并且与预定的块相关联时，每个属性值都被增加，指示块的写入次数的一组块，对应于地址映射表的逻辑地址的属性值，其中预定块组的属性值的最大数量可以与最大数量的另一组块的属性值。

10. 发明申请

US20070073293A1 System and method for flexible correction of bony motion segment 审中-公开
标题翻译：骨运动段柔性矫正的系统和方法
公开(公告)号：US20070073293A1
公开(公告)日：2007-03-29
申请号：US11404587
申请日：2006-04-14
申请人： Erik Martz , David Chow , Daniel Rosenthal , Timothy Miller , Jo-Wen Lin , Darrin Friend
发明人： Erik Martz , David Chow , Daniel Rosenthal , Timothy Miller , Jo-Wen Lin , Darrin Friend
IPC分类号： A61F2/30
CPC分类号： A61B17/0401 , A61B17/7022 , A61B17/7059 , A61B17/7062 , A61B17/8085 , A61B2017/00004 , A61B2017/0412 , A61B2017/0427 , A61B2017/044 , A61F2/08 , A61F2/442 , A61F2002/30578 , A61L27/365
摘要： A non-rigid system and method for stabilizing displaced bony members include a flexible unit of tethering material coupled to the displaced bony members so as to restore a desired shape, curvature of or relationship between the bony members without excessively limiting mobility of bony members located adjacent to the displaced members the rest of the portions of the motion bony segment during a restoration process.
摘要翻译：用于稳定移植的骨骼构件的非刚性系统和方法包括耦合到移位的骨构件的系紧材料的柔性单元，以便恢复所需形状，骨骼构件之间的曲率或关系，而不会过度限制邻近的骨构件的运动性在恢复过程中，向移位的成员移动骨段的其余部分。

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