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1. 发明申请

US20070276988A1 Page and Block Management Algorithm for NAND Flash 有权
标题翻译： NAND Flash的页面和块管理算法
公开(公告)号：US20070276988A1
公开(公告)日：2007-11-29
申请号：US11779804
申请日：2007-07-18
申请人： Jianjun Luo , Chris Tsu , Charles Lee , David Chow
发明人： Jianjun Luo , Chris Tsu , Charles Lee , David Chow
IPC分类号： G06F13/28
CPC分类号： G06F12/0246 , G06F12/0292 , G06F13/28 , G06F2212/1036 , G06F2212/7211
摘要： A flash controller is adapted to communicate with a host and the flash memory and including volatile memory configured to store a page-block table of logical addresses addressable by the physical addresses. The logical addresses are used by the controller to identify the blocks. The table has an address mapping table and a property value table, the property value table includes property values, each of the property values being increased in value every time a block is written up to a maximum value and being associated with a block of a predetermined group of blocks and indicative of the number of times a block has been written, the property values corresponding to the logical addresses of the address mapping table, wherein the maximum number the property values of the predetermined group of blocks take on is adjustably different than the maximum number the property values of another group of blocks.
摘要翻译：闪存控制器适于与主机和闪存进行通信，并且包括被配置为存储可通过物理地址寻址的逻辑地址的页块表的易失性存储器。逻辑地址由控制器用于识别块。该表具有地址映射表和属性值表，属性值表包括属性值，每当一个块写入最大值并且与预定的块相关联时，每个属性值都被增加，指示块的写入次数的一组块，对应于地址映射表的逻辑地址的属性值，其中预定块组的属性值的最大数量可以与最大数量的另一组块的属性值。

2. 发明申请

US20080037321A1 Partial-Write-Collector Algorithm for Multi Level Cell (MLC) Flash 有权
标题翻译：用于多级单元（MLC）闪存的部分写入 - 收集器算法
公开(公告)号：US20080037321A1
公开(公告)日：2008-02-14
申请号：US11774906
申请日：2007-07-09
申请人： Jianjun Luo , Chris Tsu , Charles Lee , David Chow
发明人： Jianjun Luo , Chris Tsu , Charles Lee , David Chow
IPC分类号： G11C16/06
CPC分类号： G11C16/102 , G06F8/65 , G11C2211/5641
摘要： A flash memory system includes a multi level cell (MLC) flash memory organized into blocks and having pages of information, which has data and spare. The MLC flash memory includes at least a temporary area to store at least a portion of a page of information during a partial write operation. The MLC flash memory stores a page of information into a block identified by a target physical address. The flash memory system further includes a flash card micro-controller causes communication between a host flash card controller and the MLC flash memory and includes a buffer memory configured to store a portion of a page of information, where the micro-controller writes the at least a portion of a page of information to the temporary area and later copies the written at least a portion of a page of information into the block identified by a target physical address.
摘要翻译：闪存系统包括组织成块并具有数据和备用的信息页的多级单元（MLC）闪存。在部分写入操作期间，MLC闪速存储器至少包括用于存储信息页的至少一部分的临时区域。 MLC闪速存储器将一页信息存储到由目标物理地址识别的块中。闪存系统还包括闪存卡微控制器引起主机闪存卡控制器和MLC闪速存储器之间的通信，并且包括被配置为存储信息页的一部分的缓冲存储器，其中微控制器写入至少信息页面的一部分到临时区域，并且稍后将写入信息页的至少一部分复制到由目标物理地址识别的块中。

3. 发明申请

US20070276987A1 Source and Shadow Wear-Leveling Method and Apparatus 失效
标题翻译：源和阴影磨损均衡方法和装置
公开(公告)号：US20070276987A1
公开(公告)日：2007-11-29
申请号：US11767417
申请日：2007-06-22
申请人： Jianjun Luo , Chris Tsu , Charles Lee , David Chow
发明人： Jianjun Luo , Chris Tsu , Charles Lee , David Chow
IPC分类号： G06F12/02
CPC分类号： G06F13/28 , G06F12/0246 , G06F12/0292 , G06F2212/1036 , G06F2212/7211
摘要： A flash memory system includes flash memory organized into a plurality of blocks of pages for storage of information, a page including data and spare, the blocks being identifiable, within the flash memory, by a physical address. The system further has a flash controller for communicating with a host and the flash memory and includes volatile memory for storing a source-shadow table of logical addresses identifying blocks addressable by the physical addresses. The source-shadow table has an address mapping table and a property value table. The property value table is used to store property values, each of which is associated with a block of a predetermined group of blocks and is indicative of the number of times a block has been written since the last erase operation performed thereon. The property values correspond to the logical addresses of the address mapping table, wherein a block having been written no more than two times is re-written to different areas of the flash memory without requiring an erase operation.
摘要翻译：闪速存储器系统包括组织成多个页面块的闪存，用于存储信息，包括数据和备用的页面，所述块可被闪存存储器内的物理地址识别。该系统还具有用于与主机和闪速存储器进行通信的闪存控制器，并且包括用于存储识别通过物理地址可寻址的块的逻辑地址的源影子表的易失性存储器。 source-shadow表有一个地址映射表和一个属性值表。属性值表用于存储属性值，每个属性值与预定块块组相关联，并且表示自上次执行的上次擦除操作以来写入块的次数。属性值对应于地址映射表的逻辑地址，其中已经写入不超过两次的块被重写到闪速存储器的不同区域，而不需要擦除操作。

4. 发明申请

US20080034154A1 Multi-Channel Flash Module with Plane-Interleaved Sequential ECC Writes and Background Recycling to Restricted-Write Flash Chips 有权
标题翻译：具有平面交错顺序ECC的多通道闪存模块写入和背景回收限制写入闪存芯片
公开(公告)号：US20080034154A1
公开(公告)日：2008-02-07
申请号：US11871627
申请日：2007-10-12
申请人： Charles Lee , Abraham Ma , Frank Yu , David Chow , Ming-Shiang Shen
发明人： Charles Lee , Abraham Ma , Frank Yu , David Chow , Ming-Shiang Shen
IPC分类号： G06F12/00
CPC分类号： G06F12/0607 , G06F12/0246 , G06F2212/7201 , G06F2212/7203 , G06F2212/7205 , G06F2212/7208 , G11C16/0408 , G11C2211/5649
摘要： A RAM mapping table is restored from flash memory using plane, block, and page addresses generated by a physical sequential address counter. The RAM mapping table is restored following a plane-interleaved sequence generated by the physical sequential address counter using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. The physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of 0, 1, 4096, 4097, 2, 3, 4098, 4099, etc. in the four planes of flash memory. Background recycling and ECC writes are also performed.
摘要翻译：使用由物理顺序地址计数器生成的平面，块和页面地址从闪存中恢复RAM映射表。 RAM映射表在使用从逻辑块索引的最低位提取的交错比特的物理顺序地址计数器产生的平面交织序列之后恢复。这些平面交织位分为LSB和MSB，LSB与MSB之间的中间物理块位。物理顺序地址计数器通过在中间物理块位之前递增平面交织比特，然后将MSB重定位到中间物理块比特之上来生成物理块号。这导致在闪存的四个平面中以0,1,4096,4097,2,3,40,40,4099等的低高序列访问块。还执行后台回收和ECC写入。

5. 发明申请

US20080034153A1 Flash Module with Plane-Interleaved Sequential Writes to Restricted-Write Flash Chips 有权
标题翻译：闪存模块与平面交错顺序写入限制写入闪存芯片
公开(公告)号：US20080034153A1
公开(公告)日：2008-02-07
申请号：US11871011
申请日：2007-10-11
申请人： Charles Lee , Frank Yu , Abraham Ma , David Chow , Ming-Shiang Shen
发明人： Charles Lee , Frank Yu , Abraham Ma , David Chow , Ming-Shiang Shen
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0607 , G06F2212/7201 , G06F2212/7208 , G11C11/5621 , G11C16/0408
摘要： A flash memory controller on a PCIE bus controls flash-memory modules on a flash bus. The flash-memory modules are plane-interleaved using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. A physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of 0, 1, 4096, 4097, 2, 3, 4098, 4099, etc. in the four planes of flash memory. A RAM physical page valid table tracks valid pages in the four planes, while a RAM mapping table stores the plane, block, and page addresses for logical sectors generated by the physical sequential address counter.
摘要翻译： PCIE总线上的闪存控制器控制闪存总线上的闪存模块。闪存模块使用从逻辑块索引的最低位提取的交错比特进行平面交织。这些平面交织位分为LSB和MSB，LSB与MSB之间的中间物理块位。物理顺序地址计数器通过在中间物理块比特之前递增平面交织比特，然后将MSB重新定位到中间物理块比特之上来生成物理块号。这导致在闪存的四个平面中以0,1,4096,4097,2,3,40,40,4099等的低高序列访问块。 RAM物理页有效表跟踪四个平面中的有效页面，而RAM映射表存储由物理顺序地址计数器生成的逻辑扇区的平面，块和页面地址。

6. 发明申请

US20080016269A1 Flash / Phase-Change Memory in Multi-Ring Topology Using Serial-Link Packet Interface 失效
标题翻译：使用串行链路分组接口的多环拓扑中的闪存/相变存储器
公开(公告)号：US20080016269A1
公开(公告)日：2008-01-17
申请号：US11773827
申请日：2007-07-05
申请人： David Chow , Charles Lee , Frank Yu
发明人： David Chow , Charles Lee , Frank Yu
IPC分类号： G06F12/00
CPC分类号： G06F13/1684 , G11C13/0004 , G11C16/102 , G11C2216/30
摘要： A multi-ring memory controller sends request packets to multiple rings of serial flash-memory chips. Each of the multiple rings has serial flash-memory chips with serial links in a uni-directional ring. Each serial flash-memory chip has a bypassing transceiver with a device ID checker that bypasses serial packets to a clock re-synchronizer and bypass logic for retransmission to the next device in the ring, or extracts the serial packet to the local device when an ID match occurs. Serial packets pass through all devices in the ring during one round-trip transaction from the controller. The average latency of one round is constant for all devices on the ring, reducing data-dependent performance, since the same packet latency occurs regardless of the data location on the ring. The serial links can be a Peripheral Component Interconnect (PCI) Express bus. Packets have modified-PCI-Express headers that define the packet type and data-payload length.
摘要翻译：多环存储器控制器将请求数据包发送到串行闪存芯片的多个环。多个环中的每个环都具有串行闪存芯片，其具有单向环中的串行链路。每个串行闪存芯片都具有一个旁路收发器，其中设备ID检查器将串行数据包绕过时钟重新同步器，并且旁路逻辑用于重传到环中的下一个设备，或者当ID为ID时将串行数据包提取给本地设备匹配发生。在来自控制器的一次往返事务期间，串行数据包通过环中的所有设备。由于相同的数据包延迟发生，环路上的所有设备的平均延迟都是恒定的，从而降低了数据相关性能，无论环的数据位置如何。串行链路可以是外围组件互连（PCI）Express总线。数据包已经修改了PCI-Express头，定义了数据包类型和数据有效负载长度。

7. 发明申请

US20080098164A1 SRAM Cache & Flash Micro-Controller with Differential Packet Interface 失效
标题翻译：具有差分数据包接口的SRAM缓存和闪存微控制器
公开(公告)号：US20080098164A1
公开(公告)日：2008-04-24
申请号：US11876251
申请日：2007-10-22
申请人： Charles Lee , David Chow , Abraham Ma , Frank Yu , Ming-Shiang Shen
发明人： Charles Lee , David Chow , Abraham Ma , Frank Yu , Ming-Shiang Shen
IPC分类号： G06F12/00
CPC分类号： G06F12/0866 , G06F2212/2022 , G06F2212/2515
摘要： A flash microcontroller has a Static Random-Access-Memory (SRAM) buffer that stores several blocks of boot code read from a flash memory. The SRAM buffer also operates as a cache of flash data after booting is complete. Cache read and write hits use the SRAM cache rather than flash memory, while old cache lines and read misses access the flash memory. Both the external host and the microcontroller are booted from boot code buffered in the SRAM buffer. A boot-loader state machine reads the flash ID and programs flash parameter registers with timing parameters for the flash memory. The flash microcontroller uses a differential interface to the external host, with a differential transceiver and a differential serial interface. Frame, packet, and encoded clock processing is also performed by the serial interface.
摘要翻译：闪存微控制器具有静态随机存取存储器（SRAM）缓冲器，其存储从闪存读取的几个引导代码块。引导完成后，SRAM缓冲区还可以作为闪存数据缓存。缓存读取和写入命中使用SRAM缓存而不是闪存，而旧的缓存行和读取未命中访问闪存。外部主机和微控制器均由缓冲在SRAM缓冲区中的引导代码引导。引导加载器状态机读取闪存ID，并使用Flash存储器的时序参数对闪存参数寄存器进行编程。闪存单片机使用与外部主机的差分接口，具有差分收发器和差分串行接口。帧，分组和编码时钟处理也由串行接口执行。

8. 发明申请

US20080071963A1 Express card with extended USB interface 审中-公开
标题翻译：具有扩展USB接口的Express卡
公开(公告)号：US20080071963A1
公开(公告)日：2008-03-20
申请号：US11979103
申请日：2007-10-31
申请人： David Chow , Sidney Young , Charles Lee , Abraham Ma , Ming-Shiang Shen
发明人： David Chow , Sidney Young , Charles Lee , Abraham Ma , Ming-Shiang Shen
IPC分类号： G06F13/20 , G06F12/02
CPC分类号： G06F13/409 , G06F2213/0026 , G06F2213/0042 , Y02D10/14 , Y02D10/151
摘要： An ExpressCard having USB connection has a card case having two opposite first and second end portions and two opposite lateral portions. A card connector is formed at the first end portion of the card case and having a USB interface. Flash chips are implemented in the card case. A USB flash controller implemented in the card case and connected between the USB interface and the flash chips in order to provide a data access to the flash chips through the USB interface. A USB socket, in form factors of Mini-USB or Extended Mini-connector-type, is implemented in the card case and connected to the USB flash controller in order to provide a data access to the one or more flash chips therethrough. An extended Universal-Serial Bus (EUSB) host enters a suspend mode rather than poll an ExpressCard that is busy performing a memory or other operation, thereby saving power.
摘要翻译：具有USB连接的ExpressCard具有具有两个相对的第一和第二端部和两个相对的横向部分的卡盒。卡连接器形成在卡盒的第一端部并且具有USB接口。闪存芯片在卡盒中实现。 USB闪存控制器实现在卡盒中并连接在USB接口和闪存芯片之间，以通过USB接口提供对闪存芯片的数据访问。一个USB插座，以Mini-USB或扩展迷你连接器类型的形式被实现在卡盒中并连接到USB闪存控制器，以便提供对一个或多个闪存芯片的数据访问。扩展的通用串行总线（EUSB）主机进入挂起模式，而不是轮询正忙于执行内存或其他操作的ExpressCard，从而节省电量。

9. 发明申请

US20080065794A1 Chained DMA for Low-Power Extended USB Flash Device Without Polling 失效
标题翻译：用于低功耗扩展USB闪存设备的链接DMA，无轮询
公开(公告)号：US20080065794A1
公开(公告)日：2008-03-13
申请号：US11928124
申请日：2007-10-30
申请人： Charles Lee , David Chow , Abraham Ma , Frank Yu , Ming-Shiang Shen , Horng-Yee Chou
发明人： Charles Lee , David Chow , Abraham Ma , Frank Yu , Ming-Shiang Shen , Horng-Yee Chou
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , Y02D10/14
摘要： An extended Universal-Serial Bus (EUSB) host has reduced loading by using radio frequency (RF) transceivers or direct wiring traces rather than a pair of legacy USB cables. The reduced loading opens the eye pattern. The EUSB device transfers internal data using chained Direct-Memory Access (DMA). Registers in a DMA controller point to a vector table that has vector entries, each pointing to a destination and a source. The source is a memory table for a memory group. The memory table has entries for several memory segments. Each memory-table entry has a pointer to a memory segment and a byte count for the segment. Once all bytes in the segment are transferred, a flag in the entry indicates when another memory segment follows within the memory group. When an END flag is read, then vector table is advanced to the next vector entry, and another memory group of memory segments processed.
摘要翻译：扩展的通用串行总线（EUSB）主机通过使用射频（RF）收发器或直接布线轨迹而不是一对传统的USB电缆减少了负载。减少负荷打开眼睛图案。 EUSB设备使用链接的直接内存访问（DMA）传输内部数据。 DMA控制器中的寄存器指向具有向量条目的向量表，每个向量表指向一个目的地和一个源。源是内存组的内存表。内存表有几个内存段的条目。每个存储表条目具有指向存储器段的指针和段的字节计数。一旦片段中的所有字节都被传送，该条目中的标志表示在存储器组中跟随其他内存段的时间。读取END标志时，向量表前进到下一个向量条目，并处理另一个内存段的内存组。

10. 发明申请

US20080046608A1 Low-Power Extended USB Flash Device Without Polling 审中-公开
标题翻译：低功耗扩展USB闪存设备，无轮询
公开(公告)号：US20080046608A1
公开(公告)日：2008-02-21
申请号：US11925933
申请日：2007-10-27
申请人： Charles Lee , David Chow , Abraham Ma , Frank Yu , Ming-Shiang Shen , Horng-Yee Chou
发明人： Charles Lee , David Chow , Abraham Ma , Frank Yu , Ming-Shiang Shen , Horng-Yee Chou
IPC分类号： G06F3/00
CPC分类号： G06F13/4045 , Y02D10/14 , Y02D10/151
摘要： An extended Universal-Serial Bus (EUSB) host enters a suspend mode rather than poll an EUSB device that is busy performing a memory or other operation. Power is saved since polling is avoided. The busy EUSB device sends a not-yet NYET signal back to the EUSB host to instruct the host to enter the suspend mode. When the EUSB device is ready to continue transfer with the host, the EUSB device wakes up the host by sending a ready RDY signal back to the host. The NYET and RDY signals may be tokens or flags in serial packets sent over a full-duplex connection to the host with two sets of differential pairs. Transfers may be re-started by the host after suspension once the requested data is read from flash memory, or space is made available in a sector buffer by completing earlier writes to flash memory.
摘要翻译：扩展的通用串行总线（EUSB）主机进入暂停模式，而不是轮询正忙于执行内存或其他操作的EUSB设备。省电，因为避免轮询。繁忙的EUSB设备向EUSB主机发送一个尚未发送的NYET信号，指示主机进入挂起模式。当EUSB设备准备好继续与主机进行传输时，EUSB设备通过将准备好的RDY信号发送回主机来唤醒主机。 NYET和RDY信号可以是通过全双工连接发送到具有两组差分对的主机的串行数据包中的令牌或标志。一旦所请求的数据从闪存中读取，主机可以重新启动传输，或者通过完成对闪存的更早写入，在扇区缓冲器中可用空间。

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