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1. 发明授权

US06267659B1 Stacked polish pad 失效
标题翻译：堆积抛光垫
公开(公告)号：US06267659B1
公开(公告)日：2001-07-31
申请号：US09564785
申请日：2000-05-04
申请人： Shyng-Tsong Chen , Michael F. Lofaro , Woody Ray Smith
发明人： Shyng-Tsong Chen , Michael F. Lofaro , Woody Ray Smith
IPC分类号： B24D1100
CPC分类号： B24B37/22 , B24B37/24 , B24B49/08 , B24D13/20
摘要： A polishing pad assembly is described for use in a chemical-mechanical polishing apparatus having a polishing platen. The polishing pad assembly includes a first pad disposed on the platen. The first pad comprises a sealable enclosure with a flexible outer skin and partially filled with a porous material. A control is adapted to inject fluid into and to remove fluid from the enclosure. The first pad has a hardness which is variable according to an amount of fluid in the enclosure. A second pad is disposed on the first pad.
摘要翻译：描述了一种用于具有研磨台板的化学机械抛光装置中的抛光垫组件。抛光垫组件包括设置在台板上的第一垫。第一垫包括具有柔性外表皮并部分填充有多孔材料的可密封外壳。控制器适于将流体注入并从外壳中移除流体。第一垫具有根据外壳中的流体量可变的硬度。第二垫设置在第一垫上。

2. 发明授权

US07064064B2 Copper recess process with application to selective capping and electroless plating 有权
标题翻译：铜凹槽工艺，适用于选择性封盖和无电镀
公开(公告)号：US07064064B2
公开(公告)日：2006-06-20
申请号：US11058783
申请日：2005-02-16
申请人： Shyng-Tsong Chen , Timothy J. Dalton , Kenneth M. Davis , Chao-Kun Hu , Fen F. Jamin , Steffen K. Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael F. Lofaro , Sandra G. Malhotra , Chandrasekhar Narayan , David L. Rath , Judith M. Rubino , Katherine L. Saenger , Andrew H. Simon , Sean P. E. Smith , Wei-tsu Tseng
发明人： Shyng-Tsong Chen , Timothy J. Dalton , Kenneth M. Davis , Chao-Kun Hu , Fen F. Jamin , Steffen K. Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael F. Lofaro , Sandra G. Malhotra , Chandrasekhar Narayan , David L. Rath , Judith M. Rubino , Katherine L. Saenger , Andrew H. Simon , Sean P. E. Smith , Wei-tsu Tseng
IPC分类号： H01L21/44
CPC分类号： H01L21/76849 , H01L21/76834 , H01L21/76847 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.
摘要翻译：公开了一种集成电路结构，其具有逻辑和功能器件层以及逻辑和功能器件层之上的互连层。互连层具有衬底，衬底内的导电特征和仅位于导电特征之上的盖。

3. 发明授权

US06975032B2 Copper recess process with application to selective capping and electroless plating 有权
公开(公告)号：US06975032B2
公开(公告)日：2005-12-13
申请号：US10319967
申请日：2002-12-16
申请人： Shyng-Tsong Chen , Timothy J. Dalton , Kenneth M. Davis , Chao-Kun Hu , Fen F. Jamin , Steffen K. Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael F. Lofaro , Sandra G. Malhotra , Chandrasekhar Narayan , David L. Rath , Judith M. Rubino , Katherine L. Saenger , Andrew H. Simon , Sean P. E. Smith , Wei-tsu Tseng
发明人： Shyng-Tsong Chen , Timothy J. Dalton , Kenneth M. Davis , Chao-Kun Hu , Fen F. Jamin , Steffen K. Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael F. Lofaro , Sandra G. Malhotra , Chandrasekhar Narayan , David L. Rath , Judith M. Rubino , Katherine L. Saenger , Andrew H. Simon , Sean P. E. Smith , Wei-tsu Tseng
IPC分类号： H01L21/768 , H01L23/532 , H01L23/48
CPC分类号： H01L21/76849 , H01L21/76834 , H01L21/76847 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

4. 发明授权

US08513127B2 Chemical mechanical planarization processes for fabrication of FinFET devices 有权
标题翻译：用于制造FinFET器件的化学机械平面化工艺
公开(公告)号：US08513127B2
公开(公告)日：2013-08-20
申请号：US13012836
申请日：2011-01-25
申请人： Josephine B. Chang , Leslie Charns , Jason E. Cummings , Michael A. Guillorn , Lukasz J. Hupka , Dinesh R. Koli , Tomohisa Konno , Mahadevaiyer Krishnan , Michael F. Lofaro , Jakub W. Nalaskowski , Masahiro Noda , Dinesh K. Penigalapati , Tatsuya Yamanaka
发明人： Josephine B. Chang , Leslie Charns , Jason E. Cummings , Michael A. Guillorn , Lukasz J. Hupka , Dinesh R. Koli , Tomohisa Konno , Mahadevaiyer Krishnan , Michael F. Lofaro , Jakub W. Nalaskowski , Masahiro Noda , Dinesh K. Penigalapati , Tatsuya Yamanaka
IPC分类号： H01L21/302
CPC分类号： H01L21/31053 , H01L29/517 , H01L29/6653 , H01L29/66545
摘要： A planarization method includes planarizing a semiconductor wafer in a first chemical mechanical polish step to remove overburden and planarize a top layer leaving a thickness of top layer material over underlying layers. The top layer material is planarized in a second chemical mechanical polish step to further remove the top layer and expose underlying layers of a second material and a third material such that a selectivity of the top layer material to the second material to the third material is between about 1:1:1 to about 2:1:1 to provide a planar topography.
摘要翻译：平面化方法包括在第一化学机械抛光步骤中平坦化半导体晶片以去除覆盖层并平坦化顶层，从而在顶层之上留下厚度的顶层材料。顶层材料在第二化学机械抛光步骤中被平坦化，以进一步去除顶层并暴露第二材料和第三材料的下层，使得顶层材料对第二材料对第三材料的选择性在约1：1至约2：1：1，以提供平面形貌。

5. 发明授权

US08273598B2 Method for forming a self-aligned bit line for PCRAM and self-aligned etch back process 有权
标题翻译：用于形成PCRAM和自对准回蚀工艺的自对准位线的方法
公开(公告)号：US08273598B2
公开(公告)日：2012-09-25
申请号：US13020051
申请日：2011-02-03
申请人： Matthew J. Breitwisch , Chieh-Fang Chen , Shih-Hung Chen , Eric A. Joseph , Chung Hon Lam , Michael F. Lofaro , Hsiang-Lan Lung , Alejandro G. Schrott , Min Yang
发明人： Matthew J. Breitwisch , Chieh-Fang Chen , Shih-Hung Chen , Eric A. Joseph , Chung Hon Lam , Michael F. Lofaro , Hsiang-Lan Lung , Alejandro G. Schrott , Min Yang
IPC分类号： H01L21/00
CPC分类号： H01L45/06 , H01L45/144 , H01L45/1608 , H01L45/1683
摘要： A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and forming at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.
摘要翻译：一种形成与相变材料对准的位线的方法，包括在下电极的一部分上形成牺牲材料的基座并且形成与所述牺牲材料相邻的至少一个电介质材料，其中所述至少一种电介质材料具有上表面与牺牲材料的基座的上表面基本共面。牺牲材料的基座被选择性地移除到至少一个电介质材料和下电极以提供到下电极的暴露表面的开口。在下电极的暴露表面上形成相变材料，并且用导电填充材料填充开口。还提供了自对准的回蚀工艺。

6. 发明申请

US20120083121A1 Fabrication of Replacement Metal Gate Devices 有权
标题翻译：替代金属门装置的制造
公开(公告)号：US20120083121A1
公开(公告)日：2012-04-05
申请号：US13012879
申请日：2011-01-25
申请人： Takashi Ando , Leslie Charns , Jason E. Cummings , Lukasz J. Hupka , Dinesh R. Koli , Tomohisa Konno , Mahadevaiyer Krishnan , Michael F. Lofaro , Jakub W. Nalaskowski , Masahiro Noda , Dinesh K. Penigalapati , Tatsuya Yamanaka
发明人： Takashi Ando , Leslie Charns , Jason E. Cummings , Lukasz J. Hupka , Dinesh R. Koli , Tomohisa Konno , Mahadevaiyer Krishnan , Michael F. Lofaro , Jakub W. Nalaskowski , Masahiro Noda , Dinesh K. Penigalapati , Tatsuya Yamanaka
IPC分类号： H01L21/463
CPC分类号： H01L21/31053 , H01L29/517 , H01L29/6653 , H01L29/66545
摘要： Methods for polishing multiple dielectric layers to form replacement metal gate structures include a first chemical mechanical polish step to remove overburden and planarize a top layer to leave a planarized thickness over a gate structure. A second chemical mechanical polish step includes removal of the thickness to expose an underlying covered surface of a dielectric of the gate structure with a slurry configured to polish the top layer and the underlying covered surface substantially equally to accomplish a planar topography. A third chemical mechanical polish step is employed to remove the dielectric of the gate structure and expose a gate conductor.
摘要翻译：用于抛光多个电介质层以形成替换金属栅极结构的方法包括第一化学机械抛光步骤，以去除覆盖层并平坦化顶层以在栅极结构上留下平坦化的厚度。第二化学机械抛光步骤包括去除厚度以暴露栅极结构的电介质的下面覆盖的表面，其中浆料被配置成基本上等同地抛光顶层和下面的被覆表面以实现平面形貌。采用第三种化学机械抛光步骤来去除栅极结构的电介质并露出栅极导体。

7. 发明授权

US07179760B2 Bilayer cap structure including HDP/bHDP films for conductive metallization and method of making same 失效
标题翻译：双层盖结构，包括用于导电金属化的HDP / bHDP膜及其制造方法
公开(公告)号：US07179760B2
公开(公告)日：2007-02-20
申请号：US10908833
申请日：2005-05-27
申请人： Richard A. Conti , Thomas F. Houghton , Michael F. Lofaro , Jeffery B. Maxson , Ann H. McDonald , Yun-Yu Wang , Keith Kwong Hon Wong , Daewon Yang
发明人： Richard A. Conti , Thomas F. Houghton , Michael F. Lofaro , Jeffery B. Maxson , Ann H. McDonald , Yun-Yu Wang , Keith Kwong Hon Wong , Daewon Yang
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L23/53238 , H01L21/28556 , H01L21/76849 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a bilayer cap structure for interconnect structures that comprise copper metallization or other conductive metallization. Such bilayer cap structure includes a first cap layer formed by an unbiased high density plasma (HDP) chemical vapor deposition process, and a second cap layer over the first cap layer, where the second cap layer is formed by a biased high density plasma (bHDP) chemical vapor deposition process. During the bHDP chemical vapor deposition process, a low AC bias power is applied to the substrate to increase the ion bombardment on the substrate surface and to induce resputtering of the capping material, thereby forming a seamless second cap layer with excellent reactive ion etching (RIE) selectivity.
摘要翻译：本发明涉及一种用于互连结构的双层盖结构，其包括铜金属化或其它导电金属化。这种双层盖结构包括通过无偏高密度等离子体（HDP）化学气相沉积工艺形成的第一盖层和在第一盖层上的第二盖层，其中第二盖层由偏置的高密度等离子体（bHDP ）化学气相沉积工艺。在bHDP化学气相沉积工艺期间，将低AC偏置功率施加到衬底上以增加衬底表面上的离子轰击并引起封盖材料的再溅射，从而形成具有优异的反应离子蚀刻（RIE）的无缝第二帽层）选择性。

8. 发明授权

US06098788A Casting of complex micromechanical objects 失效
标题翻译：铸造复杂的微机械物体
公开(公告)号：US06098788A
公开(公告)日：2000-08-08
申请号：US926401
申请日：1997-09-09
申请人： Nancy Anne Greco , Ernest Norman Levine , Michael F. Lofaro , James Gardner Ryan
发明人： Nancy Anne Greco , Ernest Norman Levine , Michael F. Lofaro , James Gardner Ryan
IPC分类号： B29C33/30 , B29C33/38 , B65G33/00
CPC分类号： B29C33/38 , B29C33/302 , Y10T428/24322
摘要： A seamless micromechanical object is cast by forming a multilevel mold, filling the mold, and selectively removing the mold with respect to the micromechanical object. The mold can have a first level having a first opening therein, and a second level on the first level, the second level having a second opening therein, the second opening smaller than the first opening. The object may contain a controlled void, for example a micromechanical auger with a void formed therethrough to be used as a capillary to drain off fluids when the auger is in use.
摘要翻译：通过形成多层模具，填充模具并相对于微机械物体选择性地移除模具来铸造无缝微机械物体。模具可以具有在其中具有第一开口的第一层和第一层上的第二层，第二层在其中具有第二开口，第二开口小于第一开口。该物体可以包含受控的空隙，例如具有穿过其形成的空隙的微机械螺旋钻，用作毛细管以在使用螺旋推运器时排出流体。

9. 发明授权

US5618354A Apparatus and method for carrier backing film reconditioning 失效
标题翻译：载体背膜修复的装置和方法
公开(公告)号：US5618354A
公开(公告)日：1997-04-08
申请号：US642830
申请日：1996-05-03
申请人： Michael F. Lofaro
发明人： Michael F. Lofaro
IPC分类号： B08B3/02 , B24B37/34 , B08B11/02
CPC分类号： B24B37/34 , B08B3/02 , Y10S134/902
摘要： An apparatus and method for cleaning and reconditioning a wafer carrier backing film. The apparatus comprises a flat perforated surface plate with a perforated film or perforated embossed glass plate on its surface; a backing plate connected to the surface plate which is fitted for connection to a cleaning solution supply and a vacuum source; and a contacting mechanism for extension/retraction of the surface plate until it contacts the carrier backing film. Following a wafer unload cycle, the carrier backing film is reconditioned by spraying a cleaning solution at the carrier backing film so as to rinse slurry deposits from the film material; extending the surface plate to make sealed contact with the wafer carrier; initiating a vacuum condition to press the carrier backing film and draw out slurry residuals and excessive water content from within the film; and retracting the surface plate to reconstitute the film as the material draws in surrounding air to break the vacuum condition.
摘要翻译：一种用于清洁和修复晶片载体背衬膜的设备和方法。该装置包括在其表面上具有穿孔膜或穿孔压花玻璃板的扁平穿孔表面板; 连接到表面板的背板，其被安装用于连接到清洁溶液供应源和真空源; 以及用于表面板的延伸/缩回的接触机构，直到其接触载体背衬膜。在晶片卸载循环之后，通过在载体背衬膜上喷射清洁溶液来重新调整载体背衬膜，以便从膜材料中冲洗浆料沉积物; 延伸表面板以与晶片载体密封接触; 启动真空条件以压制载体背衬膜并从膜内抽出浆液残留物和过多的含水量; 并且当材料吸入周围的空气中以折回真空条件时，缩回表面板以重构膜。

10. 发明授权

US08807318B2 Multi-generational carrier platform 有权
标题翻译：多代载体平台
公开(公告)号：US08807318B2
公开(公告)日：2014-08-19
申请号：US13237328
申请日：2011-09-20
申请人： Michael F. Lofaro
发明人： Michael F. Lofaro
IPC分类号： B65G43/00
CPC分类号： H01L21/67706 , B23Q3/088 , H01L21/67173 , H01L21/6776 , H01L21/68764 , H01L21/68771 , H01L21/68785
摘要： A multi-generational carrier platform is configured to carry substrate carriers of different sizes depending on processing needs. Multiple carrier adaptors are provided on one side of a support plate, and substrate carriers can be distributed among the carrier adaptors to mount a maximum number of substrates under the constraint of non-overlap of the substrates and the substrate carriers. The multi-generational carrier platform can be configured to provide rotation to each substrate carrier mounted thereupon, and is compatible with chemical mechanical planarization processes that require rotation of substrates against an abrasive surface. The multi-generational carrier platform facilitates maximum utilization of a processing area provided by a tool configured to process substrates of different sizes.
摘要翻译：多代载体平台被配置为根据加工需要携带不同尺寸的衬底载体。多个载体适配器设置在支撑板的一侧上，并且衬底载体可以分布在载体适配器之间以在衬底和衬底载体的不重叠的约束下安装最大数量的衬底。多代载体平台可以被配置为向安装在其上的每个基板载体提供旋转，并且与要求将基板旋转抵靠研磨表面的化学机械平面化工艺兼容。多代载体平台有助于最大限度地利用由配置成处理不同尺寸的基板的工具提供的处理区域。

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