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1. 发明授权

US07160795B2 Method and structures for reduced parasitic capacitance in integrated circuit metallizations 有权
标题翻译：集成电路金属化中减小寄生电容的方法和结构
公开(公告)号：US07160795B2
公开(公告)日：2007-01-09
申请号：US10293789
申请日：2002-11-12
申请人： Shubneesh Batra , Michael D. Chaine , Brent Keeth , Salman Akram , Troy A. Manning , Brian Johnson , Chris G. Martin , Todd A. Merritt , Eric J. Smith
发明人： Shubneesh Batra , Michael D. Chaine , Brent Keeth , Salman Akram , Troy A. Manning , Brian Johnson , Chris G. Martin , Todd A. Merritt , Eric J. Smith
IPC分类号： H01L21/44
CPC分类号： H01L24/05 , H01L23/5222 , H01L24/03 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/01041 , H01L2924/01061 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/30105
摘要： A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels is described. The method comprises forming a bond pad at least partially exposed at the top surface of the integrated circuit, forming a metal pad on the metal level below the bond pad and forming an underlying metal pad on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads to the area of the bond pad is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.
摘要翻译：描述了一种降低具有三个或更多个金属水平的集成电路中的寄生电容的方法。该方法包括形成至少部分地暴露在集成电路的顶表面处的接合焊盘，在接合焊盘下方的金属层上形成金属焊盘，并在一个或多个下金属层的每一个上形成下面的金属焊盘。在所示的实施例中，下面的金属焊盘中的至少一个的面积与焊盘的面积之比小于30％。寄生电容因此大大降低，信号传播速度提高。

2. 发明授权

US06909196B2 Method and structures for reduced parasitic capacitance in integrated circuit metallizations 有权
标题翻译：集成电路金属化中减小寄生电容的方法和结构
公开(公告)号：US06909196B2
公开(公告)日：2005-06-21
申请号：US10178172
申请日：2002-06-21
申请人： Shubneesh Batra , Michael D. Chaine , Brent Keeth , Salman Akram , Troy A. Manning , Brian Johnson , Chris G. Martin , Todd A. Merritt , Eric J. Smith
发明人： Shubneesh Batra , Michael D. Chaine , Brent Keeth , Salman Akram , Troy A. Manning , Brian Johnson , Chris G. Martin , Todd A. Merritt , Eric J. Smith
IPC分类号： H01L23/485 , H01L23/522 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L23/5222 , H01L24/03 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/01041 , H01L2924/01061 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/30105
摘要： A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels is described. The method comprises forming a bond pad at least partially exposed at the top surface of the integrated circuit, forming a metal pad on the metal level below the bond pad and forming an underlying metal pad on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads to the area of the bond pad is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.
摘要翻译：描述了一种降低具有三个或更多个金属水平的集成电路中的寄生电容的方法。该方法包括形成至少部分地暴露在集成电路的顶表面处的接合焊盘，在接合焊盘下方的金属层上形成金属焊盘，并在一个或多个下金属层的每一个上形成下面的金属焊盘。在所示的实施例中，下面的金属焊盘中的至少一个的面积与焊盘的面积之比小于30％。寄生电容因此大大降低，信号传播速度提高。

3. 发明授权

US08611058B2 Combination ESD protection circuits and methods 有权
公开(公告)号：US08611058B2
公开(公告)日：2013-12-17
申请号：US13216147
申请日：2011-08-23
申请人： Xaiofeng Fan , Michael D. Chaine
发明人： Xaiofeng Fan , Michael D. Chaine
IPC分类号： H02H9/00 , H01C7/12 , H02H1/00 , H02H1/04
CPC分类号： H02H9/044 , H01L27/0259 , H01L27/0262 , H01L27/0617 , H01L27/0817 , H02H9/046
摘要： Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. In an example method, a thyristor is triggered to conduct current from a signal node to a reference voltage node using leakage currents provided by a transistor formed in a semiconductor doped well shared with the base of the thyristor. The leakage currents are responsive to a noise event (e.g., electrostatic discharge (ESD) event) at the signal node, and increase the voltage of the semiconductor doped well to forward bias the base and the collector of the thyristor. The triggered thyristor conducts the current resulting from the ESD event to the reference voltage node.

4. 发明授权

US06809386B2 Cascode I/O driver with improved ESD operation 有权
标题翻译：串行I / O驱动器，具有改进的ESD操作
公开(公告)号：US06809386B2
公开(公告)日：2004-10-26
申请号：US10231879
申请日：2002-08-29
申请人： Michael D. Chaine , Manny K. F. Ma
发明人： Michael D. Chaine , Manny K. F. Ma
IPC分类号： H01L2976
CPC分类号： H01L29/7831 , H01L27/0266 , H01L29/0649 , H01L29/0692 , H01L29/41725
摘要： A cascode I/O driver is described that includes a barrier formed in the shared region between the two transistors. The barrier region allows the I/O driver to be designed to primarily meet I/O requirements. Accordingly, improved operating speeds are achieved. An system is described that includes an I/O driver in parallel with an ESD device. In an embodiment, the I/O driver may assist the ESD device in discharging electrostatic, after the ESD begins conducting.
摘要翻译：描述了包括形成在两个晶体管之间的共享区域中的屏障的级联I / O驱动器。屏障区域允许I / O驱动程序设计为主要满足I / O要求。因此，实现了改进的操作速度。描述了包括与ESD装置并联的I / O驱动器的系统。在一个实施例中，在ESD开始导通之后，I / O驱动器可以辅助静电装置放电静电。

5. 发明授权

US07253064B2 Cascode I/O driver with improved ESD operation 有权
标题翻译：串行I / O驱动器，具有改进的ESD操作
公开(公告)号：US07253064B2
公开(公告)日：2007-08-07
申请号：US10853538
申请日：2004-05-25
申请人： Michael D. Chaine , Manny K. F. Ma
发明人： Michael D. Chaine , Manny K. F. Ma
IPC分类号： H01L21/336
CPC分类号： H01L29/7831 , H01L27/0266 , H01L29/0649 , H01L29/0692 , H01L29/41725
摘要： A cascode I/O driver is described that includes a barrier formed in the shared region between the two transistors. The barrier region allows the I/O driver to be designed to primarily meet I/O requirements. Accordingly, improved operating speeds are achieved. An system is described that includes an I/O driver in parallel with an ESD device. In an embodiment, the I/O driver may assist the ESD device in discharging electrostatic, after the ESD begins conducting.
摘要翻译：描述了包括形成在两个晶体管之间的共享区域中的屏障的级联I / O驱动器。屏障区域允许I / O驱动程序设计为主要满足I / O要求。因此，实现了改进的操作速度。描述了包括与ESD装置并联的I / O驱动器的系统。在一个实施例中，在ESD开始导通之后，I / O驱动器可以辅助静电装置放电静电。

6. 发明授权

US6118323A Electrostatic discharge protection circuit and method 失效
标题翻译：静电放电保护电路及方法
公开(公告)号：US6118323A
公开(公告)日：2000-09-12
申请号：US996734
申请日：1997-12-23
申请人： Michael D. Chaine , Thuyanh Bui , Scott E. Smith
发明人： Michael D. Chaine , Thuyanh Bui , Scott E. Smith
IPC分类号： G11C5/14 , G11C7/10 , G11C7/00
CPC分类号： G11C5/143 , G11C7/1051
摘要： An integrated circuit includes a voltage supply internal to the integrated circuit and circuitry for sensing the voltage level of the internal voltage supply, the circuitry responsive to produce a flag signal, VPUEN, that is in a first logical state when the voltage level is below the desired level and in a second logical state when the voltage level is above the desired level. The integrated circuit also includes a buffer driver 406 having an input terminal and an output terminal, the input terminal being coupled to the circuitry for sensing the voltage level of the internal voltage supply. The operation of the circuit is such that the output terminal 400 of the buffer driver is in a high-impedance state when the flag signal is in the first logical state, and is responsive to data signals on the input terminal to produce corresponding output signals at the output terminal when the flag signal is in the second logical state.
摘要翻译：集成电路包括集成电路内部的电压源和用于感测内部电压源的电压电平的电路，电路响应于产生标志信号VPUEN，当电压电平低于该值时，该信号处于第一逻辑状态当电压电平高于所需电平时，处于第二逻辑状态。该集成电路还包括具有输入端和输出端的缓冲驱动器406，该输入端耦合到用于检测内部电压源的电压电平的电路。电路的动作使得当标志信号处于第一逻辑状态时，缓冲驱动器的输出端子400处于高阻态，并响应于输入端上的数据信号产生相应的输出信号当标志信号处于第二逻辑状态时，输出端子。

7. 发明申请

US20130128399A1 APPARATUSES, CIRCUITS, AND METHODS FOR PROTECTION CIRCUITS FOR DUAL-DIRECTION NODES 有权
标题翻译：双向保护电路保护电路的设备，电路及方法
公开(公告)号：US20130128399A1
公开(公告)日：2013-05-23
申请号：US13302943
申请日：2011-11-22
申请人： James E. Davis , Michael D. Chaine
发明人： James E. Davis , Michael D. Chaine
IPC分类号： H02H9/04
CPC分类号： H01L27/0262 , H01L27/0255 , H01L29/7436 , H01L29/87
摘要： Apparatuses, circuits, and methods are disclosed for biased protection circuits for dual-direction nodes. In one such example apparatus, a protection circuit is coupled to a dual-direction node, and includes a positive protection component and a negative protection component. The protection circuit is configured to protect the dual-direction node during an over-limit electrical condition. The protection circuit is configured to control a turn-on condition of the protection circuit.
摘要翻译：公开了用于双向节点的偏置保护电路的装置，电路和方法。在一个这样的示例性装置中，保护电路耦合到双向节点，并且包括正保护组件和负保护组件。保护电路被配置为在超限电气状态期间保护双向节点。保护电路被配置为控制保护电路的导通状态。

8. 发明申请

US20130050887A1 COMBINATION ESD PROTECTION CIRCUITS AND METHODS 有权
标题翻译：组合ESD保护电路和方法
公开(公告)号：US20130050887A1
公开(公告)日：2013-02-28
申请号：US13216147
申请日：2011-08-23
申请人： Xiaofeng Fan , Michael D. Chaine
发明人： Xiaofeng Fan , Michael D. Chaine
IPC分类号： H02H9/02 , H01L27/06
CPC分类号： H02H9/044 , H01L27/0259 , H01L27/0262 , H01L27/0617 , H01L27/0817 , H02H9/046
摘要： Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. In an example method, a thyristor is triggered to conduct current from a signal node to a reference voltage node using leakage currents provided by a transistor formed in a semiconductor doped well shared with the base of the thyristor. The leakage currents are responsive to a noise event (e.g., electrostatic discharge (ESD) event) at the signal node, and increase the voltage of the semiconductor doped well to forward bias the base and the collector of the thyristor. The triggered thyristor conducts the current resulting from the ESD event to the reference voltage node.
摘要翻译：公开了用于保护电路免受静电放电事件的电路，集成电路，装置和方法。在一个示例性方法中，晶闸管被触发以使用由在晶体管的基极共享的半导体掺杂阱中形成的晶体管提供的漏电流从信号节点传导到参考电压节点。泄漏电流响应于信号节点处的噪声事件（例如，静电放电（ESD）事件），并且增加半导体掺杂阱的电压以使晶闸管的基极和集电极正向偏置。触发晶闸管将ESD事件导致的电流导通到参考电压节点。

9. 发明授权

US06624660B2 CMOS output driver for semiconductor device and related method for improving latch-up immunity in a CMOS output driver 有权
标题翻译：用于半导体器件的CMOS输出驱动器和用于提高CMOS输出驱动器中的闭锁抑制的相关方法
公开(公告)号：US06624660B2
公开(公告)日：2003-09-23
申请号：US10010820
申请日：2001-12-06
申请人： Wen Li , Michael D. Chaine , Manny Kin Ma
发明人： Wen Li , Michael D. Chaine , Manny Kin Ma
IPC分类号： H03K19094
CPC分类号： H03K19/00315
摘要： An output driver circuit for a semiconductor device. In one embodiment, the output driver is coupled to an output terminal of the semiconductor device and consists of an N-channel pull-down transistor and a P-channel pull-up transistor formed in an N-well in a P-type substrate. A tie-down region formed in the N-well is selectively coupled to a supply potential by means of a decoupling transistor, and during normal operation of the driver maintains the supply voltage bias of the N-well. An overdrive detection circuit is coupled to the output terminal. Upon detection of an overdrive condition on the output terminal, such as a voltage exceeding a predetermined maximum, or excessive current injected into the output terminal (or both), the overdrive detection circuit deasserts a control signal applied to the gate of the decoupling transistor, thereby decoupling the N-well from the supply potential. In one embodiment, the decoupling transistor is not coupled to the output terminal.
摘要翻译：一种用于半导体器件的输出驱动器电路。在一个实施例中，输出驱动器耦合到半导体器件的输出端子，并且由形成在P型衬底中的N阱中的N沟道下拉晶体管和P沟道上拉晶体管组成。形成在N阱中的结合区域通过去耦晶体管选择性地耦合到电源电位，并且在驱动器的正常操作期间维持N阱的电源电压偏置。过驱动检测电路耦合到输出端子。在检测出输出端子上的过驱动条件（例如超过预定最大值的电压）或注入输出端子（或两者）的过电流时，过驱动检测电路解除施加到去耦晶体管的栅极的控制信号，从而将N阱与电源电位分离。在一个实施例中，去耦晶体管不耦合到输出端。

10. 发明授权

US5814865A Bimodal ESD protection for DRAM power supplies and SCRs for DRAMs and logic circuits 失效
标题翻译：用于DRAM电源的双模式ESD保护和用于DRAM和逻辑电路的SCR
公开(公告)号：US5814865A
公开(公告)日：1998-09-29
申请号：US742196
申请日：1996-10-31
申请人： Charvaka Duvvury , Michael D. Chaine
发明人： Charvaka Duvvury , Michael D. Chaine
IPC分类号： H01L27/02 , H01L23/62
CPC分类号： H01L27/0248 , H01L2924/0002
摘要： An embodiment of the instant invention is an ESD protection circuit (100) for protecting a circuit from negative stress, the ESD protection circuit comprising: a first terminal (102); a second terminal (104), the circuit to be protected connected between the first and the second terminals; a substrate (202) of a first conductivity type; a first doped region (206) of a second conductivity type opposite the first conductivity type and formed in the substrate, the first doped region forming the source of a transistor; a second doped region (208) of the second conductivity and formed in the substrate spaced from the first doped region by a channel region, the second doped region forming the drain of the transistor; a first diode region (210) of the first conductivity type and formed in the substrate, the first diode region being spaced a minimum distance from the second doped region and wherein the first diode region forms the anode of a diode (108) and the second doped region forms the cathode of the diode; and wherein the diode and the transistor (106) are connected between the first terminal and the second terminal, the diode protects the transistor and the circuit during the negative stress.
摘要翻译：本发明的实施例是用于保护电路免受负应力的ESD保护电路（100），所述ESD保护电路包括：第一端子（102）; 第二端子（104），被保护的电路连接在第一和第二端子之间; 第一导电类型的衬底（202）; 与第一导电类型相反并形成在衬底中的第二导电类型的第一掺杂区域（206），形成晶体管源极的第一掺杂区域; 所述第二导电性的第二掺杂区域（208）形成在所述衬底中，与所述第一掺杂区域间隔开沟道区，所述第二掺杂区域形成所述晶体管的漏极; 第一导电类型的第一二极管区域（210）并形成在衬底中，第一二极管区域与第二掺杂区域间隔开最小距离，并且其中第一二极管区域形成二极管（108）的阳极，第二二极管区域形成二极管掺杂区形成二极管的阴极; 并且其中二极管和晶体管（106）连接在第一端子和第二端子之间，二极管在负应力期间保护晶体管和电路。

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