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1. 发明授权

US6118323A Electrostatic discharge protection circuit and method 失效
标题翻译：静电放电保护电路及方法
公开(公告)号：US6118323A
公开(公告)日：2000-09-12
申请号：US996734
申请日：1997-12-23
申请人： Michael D. Chaine , Thuyanh Bui , Scott E. Smith
发明人： Michael D. Chaine , Thuyanh Bui , Scott E. Smith
IPC分类号： G11C5/14 , G11C7/10 , G11C7/00
CPC分类号： G11C5/143 , G11C7/1051
摘要： An integrated circuit includes a voltage supply internal to the integrated circuit and circuitry for sensing the voltage level of the internal voltage supply, the circuitry responsive to produce a flag signal, VPUEN, that is in a first logical state when the voltage level is below the desired level and in a second logical state when the voltage level is above the desired level. The integrated circuit also includes a buffer driver 406 having an input terminal and an output terminal, the input terminal being coupled to the circuitry for sensing the voltage level of the internal voltage supply. The operation of the circuit is such that the output terminal 400 of the buffer driver is in a high-impedance state when the flag signal is in the first logical state, and is responsive to data signals on the input terminal to produce corresponding output signals at the output terminal when the flag signal is in the second logical state.
摘要翻译：集成电路包括集成电路内部的电压源和用于感测内部电压源的电压电平的电路，电路响应于产生标志信号VPUEN，当电压电平低于该值时，该信号处于第一逻辑状态当电压电平高于所需电平时，处于第二逻辑状态。该集成电路还包括具有输入端和输出端的缓冲驱动器406，该输入端耦合到用于检测内部电压源的电压电平的电路。电路的动作使得当标志信号处于第一逻辑状态时，缓冲驱动器的输出端子400处于高阻态，并响应于输入端上的数据信号产生相应的输出信号当标志信号处于第二逻辑状态时，输出端子。

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