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1. 发明授权

US07447934B2 System and method for using hot plug configuration for PCI error recovery 失效
标题翻译：使用热插拔配置进行PCI错误恢复的系统和方法
公开(公告)号：US07447934B2
公开(公告)日：2008-11-04
申请号：US11168145
申请日：2005-06-27
申请人： Shiva R. Dasari , Sudhir Dhawan , Ryuji Orita , Wingcheung T. Tam
发明人： Shiva R. Dasari , Sudhir Dhawan , Ryuji Orita , Wingcheung T. Tam
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0745
摘要： A method, system, and program product for recovering from a bus error in a computer system having a hot plug interface. In accordance with the method of the present invention, an operating system transparent interrupt, such as a system management interrupt, is generated in response to a bus error. Responsive to the operating system transparent interrupt, the hot pluggable bus is scanned and a device associated with the error is identified by an interrupt handler invoked by the interrupt. Finally, a hot plug configuration manager, such as an advanced configuration and power interface is utilized to remove the identified device from system operations without having to restart the system.
摘要翻译：一种用于从具有热插拔接口的计算机系统中的总线错误中恢复的方法，系统和程序产品。根据本发明的方法，响应总线错误产生诸如系统管理中断的操作系统透明中断。响应于操作系统透明中断，热插拔总线被扫描，并且与该错误相关联的设备由中断调用的中断处理程序识别。最后，使用诸如高级配置和电源接口之类的热插拔配置管理器来将所识别的设备从系统操作中移除，而不必重新启动系统。

2. 发明授权

US08140937B2 Memory initialization time reduction 有权
标题翻译：内存初始化时间缩短
公开(公告)号：US08140937B2
公开(公告)日：2012-03-20
申请号：US11969449
申请日：2008-01-04
申请人： Shiva R. Dasari , Sudhir Dhawan , Joseph Allen Kirscht , Jennifer L. Vargus
发明人： Shiva R. Dasari , Sudhir Dhawan , Joseph Allen Kirscht , Jennifer L. Vargus
IPC分类号： G11C29/00
CPC分类号： G06F11/1044 , G11C2029/0411
摘要： A method and apparatus to improve memory initialization in a memory of a computer system. Memory units in the memory comprise a plurality of ranks, each rank having a unique rank select. A parity generator outputs a parity bit corresponding to whether an encoded rank select has an even or odd number of “1”s. The parity bit is used by an Error Checking and Correcting (ECC) unit that generates ECC bits that are stored in a rank having an active rank select. During a first interval in a memory initialization period, ranks having an even number of “1”s in their encoded rank select are initialized in parallel. During a second interval in the memory initialization period, ranks having an odd number of “1”s in their encoded rank select are initialized in parallel.
摘要翻译：一种用于改善计算机系统的存储器中的存储器初始化的方法和装置。存储器中的存储器单元包括多个等级，每个等级具有唯一的等级选择。奇偶校验发生器输出与编码秩选择是否具有偶数或奇数“1”相对应的奇偶校验位。奇偶校验位由生成ECC位的错误检查和校正（ECC）单元使用，ECC位存储在具有活动秩选择的等级中。在存储器初始化周期的第一间隔期间，并行地初始化其编码级选择中具有偶数“1”的等级。在存储器初始化期间的第二间隔期间，并行地初始化其编码秩选择中具有奇数“1”的等级。

3. 发明申请

US20090177946A1 Memory Initialization Time Reduction 有权
标题翻译：内存初始化时间缩短
公开(公告)号：US20090177946A1
公开(公告)日：2009-07-09
申请号：US11969449
申请日：2008-01-04
申请人： Shiva R. Dasari , Sudhir Dhawan , Joseph Allen Kirscht , Jennifer L. Vargus
发明人： Shiva R. Dasari , Sudhir Dhawan , Joseph Allen Kirscht , Jennifer L. Vargus
IPC分类号： G11C29/00 , G06F11/00
CPC分类号： G06F11/1044 , G11C2029/0411
摘要： A method and apparatus to improve memory initialization in a memory of a computer system. Memory units in the memory comprise a plurality of ranks, each rank having a unique rank select. A parity generator outputs a parity bit corresponding to whether an encoded rank select has an even or odd number of “1”s. The parity bit is used by an Error Checking and Correcting (ECC) unit that generates ECC bits that are stored in a rank having an active rank select. During a first interval in a memory initialization period, ranks having an even number of “1”s in their encoded rank select are initialized in parallel. During a second interval in the memory initialization period, ranks having an odd number of “1”s in their encoded rank select are initialized in parallel.
摘要翻译：一种用于改善计算机系统的存储器中的存储器初始化的方法和装置。存储器中的存储器单元包括多个等级，每个等级具有唯一的等级选择。奇偶校验发生器输出与编码秩选择是否具有偶数或奇数“1”相对应的奇偶校验位。奇偶校验位由生成ECC位的错误检查和校正（ECC）单元使用，ECC位存储在具有活动秩选择的等级中。在存储器初始化周期的第一间隔期间，并行地初始化其编码级选择中具有偶数“1”的等级。在存储器初始化期间的第二间隔期间，并行地初始化其编码秩选择中具有奇数“1”的等级。

4. 发明授权

US07873754B2 Structure for option ROM characterization 有权
标题翻译：选项ROM表征的结构
公开(公告)号：US07873754B2
公开(公告)日：2011-01-18
申请号：US12136619
申请日：2008-06-10
申请人： William L. Bircher , Shiva R. Dasari , Wingcheung Tam
发明人： William L. Bircher , Shiva R. Dasari , Wingcheung Tam
IPC分类号： G06F3/00 , G06F9/00 , G06F9/24 , G06F15/177 , G06F1/24
CPC分类号： G06F12/023 , G06F2212/1044
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is disclosed for option ROM characterization by establishing an isolating execution environment for an expansion adapter of a computer, the adapter having an option ROM containing initialization code for the adapter, executing the initialization code for the expansion adapter in the isolating execution environment, identifying operating characteristics of the option ROM, including characteristics of the option ROM unavailable prior to execution of the initialization code in the isolating execution environment, and allocating virtual memory address space in a normal execution environment of the computer to the option ROM of the expansion adapter in dependence upon the identified operating characteristics of the option ROM.
摘要翻译：通过建立用于计算机的扩展适配器的隔离执行环境，公开了用于设计，制造和/或测试设计的机器可读存储介质中的设计结构，用于选项ROM表征，该适配器具有包含初始化代码的选项ROM 对于适配器，在隔离执行环境中执行扩展适配器的初始化代码，识别选项ROM的操作特性，包括在隔离执行环境中执行初始化代码之前不可用的选项ROM的特性，以及分配虚拟存储器将计算机的正常执行环境中的地址空间依赖于所选择的ROM的所识别的操作特性到扩展适配器的选项ROM。

5. 发明授权

US07759958B2 Apparatus, system, and method for integrated component testing 有权
标题翻译：用于集成组件测试的装置，系统和方法
公开(公告)号：US07759958B2
公开(公告)日：2010-07-20
申请号：US11859540
申请日：2007-09-21
申请人： Moises Cases , Shiva R. Dasari , Erdem Matoglu , Bhyrav M. Mutnury , Nam H. Pham
发明人： Moises Cases , Shiva R. Dasari , Erdem Matoglu , Bhyrav M. Mutnury , Nam H. Pham
IPC分类号： G01R31/02 , G06F17/50
CPC分类号： G06F11/24 , G11C5/04 , G11C29/028 , G11C29/12005 , G11C29/50 , G11C2029/5004
摘要： An apparatus, system, and method are disclosed for integrating component testing. A voltage module modifies a reference voltage integral to an electronic device to a plurality of reference voltage values. A test module tests a component of the electronic device at each of the plurality of reference voltage values. In addition, the test module determines a voltage range for the component, wherein the voltage range comprises voltage values between a high voltage failure and a low voltage failure. An optimization module sets the reference voltage value to within the voltage range.
摘要翻译：公开了用于集成部件测试的装置，系统和方法。电压模块将对电子设备积分的参考电压修改为多个参考电压值。测试模块在多个参考电压值中的每一个测试电子设备的组件。此外，测试模块确定组件的电压范围，其中电压范围包括高电压故障和低电压故障之间的电压值。优化模块将参考电压值设置在电压范围内。

6. 发明申请

US20130097412A1 Performing A Boot Sequence In A Multi-Processor System 审中-公开
标题翻译：在多处理器系统中执行引导顺序
公开(公告)号：US20130097412A1
公开(公告)日：2013-04-18
申请号：US13275019
申请日：2011-10-17
申请人： Shiva R. Dasari , Raghuswamyreddy Gundam , Newton P. Liu , Terence Rodrigues , Mehul M. Shah , Robert K. Sloan , Wingcheung Tam , Mark W. Wenning
发明人： Shiva R. Dasari , Raghuswamyreddy Gundam , Newton P. Liu , Terence Rodrigues , Mehul M. Shah , Robert K. Sloan , Wingcheung Tam , Mark W. Wenning
IPC分类号： G06F9/445
CPC分类号： G06F9/4405
摘要： Methods, apparatuses, and computer program products for performing a boot sequence in a multi-processor system are provided. Embodiments include: in response to detecting initiation of a boot sequence of the multi-processor system, initializing, by a bootstrap processor (BSP), BSP memory associated with the BSP and initializing, by an application processor, memory associated with the application processor; determining, by the BSP, whether the initialization of the BSP memory is completed; and if the initialization of the BSP memory is completed, loading, by the BSP, an operating system on the BSP memory regardless of whether the application processor has completed initialization of the memory associated with the application processor.
摘要翻译：提供了用于在多处理器系统中执行引导顺序的方法，装置和计算机程序产品。实施例包括：响应于检测到多处理器系统的引导序列的启动，由引导处理器（BSP）初始化与BSP相关联的BSP存储器并由应用处理器初始化与应用处理器相关联的存储器; 由BSP确定BSP存储器的初始化是否完成; 并且如果BSP存储器的初始化完成，则由BSP加载BSP存储器上的操作系统，而不管应用处理器是否已经完成与应用处理器相关联的存储器的初始化。

7. 发明授权

US07526578B2 Option ROM characterization 失效
标题翻译：选项ROM表征
公开(公告)号：US07526578B2
公开(公告)日：2009-04-28
申请号：US11356793
申请日：2006-02-17
申请人： William L. Bircher , Shiva R. Dasari , Wingcheung Tam
发明人： William L. Bircher , Shiva R. Dasari , Wingcheung Tam
IPC分类号： G06F3/00 , G06F9/00 , G06F9/24 , G06F15/177 , G06F1/24
CPC分类号： G06F9/4411
摘要： Methods, apparatus, and computer program products are disclosed for option ROM characterization by establishing an isolating execution environment for an expansion adapter of a computer, the adapter having an option ROM containing initialization code for the adapter, executing the initialization code for the expansion adapter in the isolating execution environment, identifying operating characteristics of the option ROM, including characteristics of the option ROM unavailable prior to execution of the initialization code in the isolating execution environment, and allocating virtual memory address space in a normal execution environment of the computer to the option ROM of the expansion adapter in dependence upon the identified operating characteristics of the option ROM.
摘要翻译：通过建立用于计算机的扩展适配器的隔离执行环境，公开了用于选项ROM表征的方法，装置和计算机程序产品，该适配器具有包含适配器的初始化代码的选项ROM，对扩展适配器执行初始化代码隔离执行环境，识别选项ROM的操作特性，包括在隔离执行环境中执行初始化代码之前不可用的选项ROM的特性，以及将计算机的正常执行环境中的虚拟内存地址空间分配给该选项 ROM，其根据所选择的ROM的识别操作特性而定。

8. 发明申请

US20130311761A1 Intelligently Loading Legacy Option ROMs In A Computing System 有权
标题翻译：在计算系统中智能加载传统选项ROM
公开(公告)号：US20130311761A1
公开(公告)日：2013-11-21
申请号：US13476230
申请日：2012-05-21
申请人： Shiva R. Dasari , Raghuswamyreddy Gundam , Newton P. Liu , Douglas W. Oliver , Terence Rodrigues , Mehul M. Shah , Wingcheung Tam
发明人： Shiva R. Dasari , Raghuswamyreddy Gundam , Newton P. Liu , Douglas W. Oliver , Terence Rodrigues , Mehul M. Shah , Wingcheung Tam
IPC分类号： G06F9/24
CPC分类号： G06F9/24 , G06F9/4401 , G06F9/4411
摘要： Intelligently loading legacy option ROMs in a computing system, including: generating, by a legacy option ROM manager, an inventory for the computing system, wherein the inventory for the computing system identifies one or more devices in the computing system; determining, by the legacy option ROM manager for each option ROM available for loading, whether a device supported by the option ROM is included in the inventory for the computing system; responsive to determining that the device supported by the option ROM is not included in the inventory for the computing system, preventing the option ROM from being loaded into an option ROM address space; and responsive to determining that the device supported by the option ROM is included in the inventory for the computing system, enabling the option ROM to be loaded into the option ROM address space.
摘要翻译：在计算系统中智能地加载传统选项ROM，包括：由遗留选项ROM管理器生成计算系统的清单，其中计算系统的清单识别计算系统中的一个或多个设备; 通过遗留选项ROM管理器为可用于加载的每个选项ROM确定是否将包含选项ROM的设备包括在计算系统的清单中; 响应于确定由选项ROM支持的设备不包括在计算系统的清单中，防止选项ROM被加载到选项ROM地址空间中; 并且响应于确定由所述选项ROM支持的设备被包括在所述计算系统的清单中，使得所述选项ROM被加载到所述选项ROM地址空间中。

9. 发明申请

US20100125731A1 METHOD FOR SECURELY MERGING MULTIPLE NODES HAVING TRUSTED PLATFORM MODULES 有权
标题翻译：用于安全地合并具有有争议的平台模块的多个节点的方法
公开(公告)号：US20100125731A1
公开(公告)日：2010-05-20
申请号：US12270888
申请日：2008-11-14
申请人： Shiva R. Dasari , Lee H. Wilson , Scott N. Durham , Sumeet Kochar , William B. Schwartz , Kenneth A. Goldman
发明人： Shiva R. Dasari , Lee H. Wilson , Scott N. Durham , Sumeet Kochar , William B. Schwartz , Kenneth A. Goldman
IPC分类号： H04L9/00
CPC分类号： G06F9/5061 , G06F21/57 , G06F2221/2105
摘要： Method, apparatus and computer program product are provided for operating a plurality of computer nodes while maintaining trust. A primary computer node and at least one secondary computer node are connected into a cluster, wherein each of the clustered computer nodes includes a trusted platform module (TPM) that is accessible to software and includes security status information about the respective computer node. Each clustered computer node is then merged into a single node with only the TPM of the primary computer node being accessible to software. The TPM of the primary computer node is updated to include the security status information of each TPM in the cluster. Preferably, the step of merging is controlled by power on self test (POST) basic input output system (BIOS) code associated with a boot processor in the primary node.
摘要翻译：提供了用于操作多个计算机节点同时保持信任的方法，装置和计算机程序产品。主计算机节点和至少一个辅助计算机节点连接到集群中，其中每个集群计算机节点包括可由软件访问的可信平台模块（TPM），并且包括关于相应计算机节点的安全状态信息。然后将每个集群计算机节点合并到单个节点，只有主计算机节点的TPM才能被软件访问。更新主计算机节点的TPM以包括集群中每个TPM的安全状态信息。优选地，合并步骤由与主节点中的引导处理器相关联的上电自检（POST）基本输入输出系统（BIOS）代码来控制。

10. 发明授权

US07594144B2 Handling fatal computer hardware errors 失效
标题翻译：处理致命的计算机硬件错误
公开(公告)号：US07594144B2
公开(公告)日：2009-09-22
申请号：US11464364
申请日：2006-08-14
申请人： Mark A. Brandyberry , Shiva R. Dasari , Daniel E. Hurlimann , Bruce J. Wilkie , Lee H. Wilson , Christopher L. Wood
发明人： Mark A. Brandyberry , Shiva R. Dasari , Daniel E. Hurlimann , Bruce J. Wilkie , Lee H. Wilson , Christopher L. Wood
IPC分类号： G06F11/00
CPC分类号： G06F11/0787 , G06F11/0745
摘要： Methods and apparatus are disclosed for handling fatal computer hardware errors on a computer that include halting data processing operations of the computer upon occurrence of a fatal hardware error; signaling by a source chip of a chipset to the programmable logic device the occurrence of a fatal hardware error; signaling by the programmable logic device to an embedded system microcontroller the occurrence of a fatal hardware error; reading by the embedded system microcontroller through at least one sideband bus from registers in chips of the chipset information regarding the cause of the fatal hardware error; and storing by the embedded system microcontroller the information in non-volatile random access memory of the embedded system microcontroller.
摘要翻译：公开了用于处理计算机上的致命计算机硬件错误的方法和装置，包括在发生致命硬件错误时停止计算机的数据处理操作; 由芯片组的源芯片向可编程逻辑器件发出致命硬件错误的发生; 信号由可编程逻辑器件向嵌入式系统微控制器发生致命的硬件错误; 嵌入式系统微控制器通过芯片芯片寄存器中的至少一个边带总线读取有关致命硬件错误原因的信息; 并将嵌入式系统微控制器存储在嵌入式系统微控制器的非易失性随机存取存储器中。

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