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1. 发明申请

US20090177946A1 Memory Initialization Time Reduction 有权
标题翻译：内存初始化时间缩短
公开(公告)号：US20090177946A1
公开(公告)日：2009-07-09
申请号：US11969449
申请日：2008-01-04
申请人： Shiva R. Dasari , Sudhir Dhawan , Joseph Allen Kirscht , Jennifer L. Vargus
发明人： Shiva R. Dasari , Sudhir Dhawan , Joseph Allen Kirscht , Jennifer L. Vargus
IPC分类号： G11C29/00 , G06F11/00
CPC分类号： G06F11/1044 , G11C2029/0411
摘要： A method and apparatus to improve memory initialization in a memory of a computer system. Memory units in the memory comprise a plurality of ranks, each rank having a unique rank select. A parity generator outputs a parity bit corresponding to whether an encoded rank select has an even or odd number of “1”s. The parity bit is used by an Error Checking and Correcting (ECC) unit that generates ECC bits that are stored in a rank having an active rank select. During a first interval in a memory initialization period, ranks having an even number of “1”s in their encoded rank select are initialized in parallel. During a second interval in the memory initialization period, ranks having an odd number of “1”s in their encoded rank select are initialized in parallel.
摘要翻译：一种用于改善计算机系统的存储器中的存储器初始化的方法和装置。存储器中的存储器单元包括多个等级，每个等级具有唯一的等级选择。奇偶校验发生器输出与编码秩选择是否具有偶数或奇数“1”相对应的奇偶校验位。奇偶校验位由生成ECC位的错误检查和校正（ECC）单元使用，ECC位存储在具有活动秩选择的等级中。在存储器初始化周期的第一间隔期间，并行地初始化其编码级选择中具有偶数“1”的等级。在存储器初始化期间的第二间隔期间，并行地初始化其编码秩选择中具有奇数“1”的等级。

2. 发明授权

US08140937B2 Memory initialization time reduction 有权
标题翻译：内存初始化时间缩短
公开(公告)号：US08140937B2
公开(公告)日：2012-03-20
申请号：US11969449
申请日：2008-01-04
申请人： Shiva R. Dasari , Sudhir Dhawan , Joseph Allen Kirscht , Jennifer L. Vargus
发明人： Shiva R. Dasari , Sudhir Dhawan , Joseph Allen Kirscht , Jennifer L. Vargus
IPC分类号： G11C29/00
CPC分类号： G06F11/1044 , G11C2029/0411
摘要： A method and apparatus to improve memory initialization in a memory of a computer system. Memory units in the memory comprise a plurality of ranks, each rank having a unique rank select. A parity generator outputs a parity bit corresponding to whether an encoded rank select has an even or odd number of “1”s. The parity bit is used by an Error Checking and Correcting (ECC) unit that generates ECC bits that are stored in a rank having an active rank select. During a first interval in a memory initialization period, ranks having an even number of “1”s in their encoded rank select are initialized in parallel. During a second interval in the memory initialization period, ranks having an odd number of “1”s in their encoded rank select are initialized in parallel.
摘要翻译：一种用于改善计算机系统的存储器中的存储器初始化的方法和装置。存储器中的存储器单元包括多个等级，每个等级具有唯一的等级选择。奇偶校验发生器输出与编码秩选择是否具有偶数或奇数“1”相对应的奇偶校验位。奇偶校验位由生成ECC位的错误检查和校正（ECC）单元使用，ECC位存储在具有活动秩选择的等级中。在存储器初始化周期的第一间隔期间，并行地初始化其编码级选择中具有偶数“1”的等级。在存储器初始化期间的第二间隔期间，并行地初始化其编码秩选择中具有奇数“1”的等级。

3. 发明授权

US07970980B2 Method and apparatus for accessing memory in a computer system architecture supporting heterogeneous configurations of memory structures 失效
标题翻译：用于在支持存储器结构的异构配置的计算机系统架构中访问存储器的方法和装置
公开(公告)号：US07970980B2
公开(公告)日：2011-06-28
申请号：US11013149
申请日：2004-12-15
申请人： Philip Rogers Hillier, III , Joseph Allen Kirscht , Jamie Randall Kuesel
发明人： Philip Rogers Hillier, III , Joseph Allen Kirscht , Jamie Randall Kuesel
IPC分类号： G06F12/00 , G06F12/06 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0813
摘要： A computer system includes at least one processor, multiple memory modules embodying a main memory, a communications medium for communicating data between the at least one processor and main memory, and memory access control logic which controls the routing of data and access to memory. The communications medium and memory access control logic are designed to accommodate a heterogenous collection of main memory configurations, in which at least one physical parameter is variable for different configurations. The bits of the memory address are mapped to actual memory locations by assigning fixed bit positions to the most critical physical parameters across multiple different module types, and assigning remaining non-contiguous bit positions to less critical physical parameters. In the preferred embodiment, the computer system employs a distributed memory architecture.
摘要翻译：计算机系统包括至少一个处理器，体现主存储器的多个存储器模块，用于在至少一个处理器和主存储器之间传送数据的通信介质，以及控制数据路由和访问存储器的存储器访问控制逻辑。通信介质和存储器访问控制逻辑被设计为适应主存储器配置的异质集合，其中至少一个物理参数对于不同的配置是可变的。通过将固定位位置分配给跨多个不同模块类型的最关键物理参数，并将剩余的非连续位位置分配给不太关键的物理参数，将存储器地址的位映射到实际存储器位置。在优选实施例中，计算机系统采用分布式存储器架构。

4. 发明申请

US20090132876A1 Maintaining Error Statistics Concurrently Across Multiple Memory Ranks 审中-公开
标题翻译：跨多个内存等级同时维护错误统计信息
公开(公告)号：US20090132876A1
公开(公告)日：2009-05-21
申请号：US11942116
申请日：2007-11-19
申请人： Ronald Ernest Freking , Joseph Allen Kirscht , Elizabeth A. McGlone
发明人： Ronald Ernest Freking , Joseph Allen Kirscht , Elizabeth A. McGlone
IPC分类号： G11C29/00
CPC分类号： G06F11/106 , G11C5/04 , G11C29/42 , G11C29/44 , G11C29/56008 , G11C29/76 , G11C2029/0411 , G11C2029/1208 , G11C2029/5606
摘要： A method and apparatus to maintain memory read error information concurrently across multiple ranks in a computer memory. An error detection unit associates a read error with a particular rank and with a particular chip in the rank. The error detection unit reports the error and the associated rank ID and chip ID to an error logging unit. The error logging unit maintains, for each rank ID and chip ID for which an error has been detected, a total number of errors that occur. A memory controller uses a fault pattern in the error logging unit to replace failing memory chips or memory ranks with a spare memory chip or a spare memory rank.
摘要翻译：一种在计算机存储器中跨多个级别同时维持存储器读取错误信息的方法和装置。错误检测单元将读取错误与特定级别和排名中的特定芯片相关联。错误检测单元向错误记录单元报告错误和相关的排名ID和芯片ID。错误记录单元对于检测到错误的每个等级ID和芯片ID维护发生的错误总数。存储器控制器使用错误记录单元中的故障模式来替换故障存储器芯片或具有备用存储器芯片或备用存储器等级的存储器级别。

5. 发明授权

US07328317B2 Memory controller and method for optimized read/modify/write performance 有权
标题翻译：用于优化读/写/写性能的内存控制器和方法
公开(公告)号：US07328317B2
公开(公告)日：2008-02-05
申请号：US10970400
申请日：2004-10-21
申请人： Philip Rogers Hillier, III , William Paul Hovis , Joseph Allen Kirscht
发明人： Philip Rogers Hillier, III , William Paul Hovis , Joseph Allen Kirscht
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.
摘要翻译：存储器控制器通过将RMW命令分解成不需要一起执行的单独且唯一的读取和写入命令来优化执行读/修改/写入命令，但只需要以正确的顺序执行。最优选的实施例结合读队列和写队列使用控制器中的单独的RMW队列。在其他实施例中，控制器将RMW的读取和写入部分放置在读取和写入队列中，但是写入队列具有与写入队列中的RMW写入命令相关联的依赖指示，以确保控制器维持正确的执行顺序。实施例允许存储器控制器以正确的执行顺序将RMW命令转换为读写命令以保持数据一致性。

6. 发明授权

US07949836B2 Memory controller and method for copying mirrored memory that allows processor accesses to memory during a mirror copy operation 失效
标题翻译：用于复制镜像存储器的内存控制器和方法，允许处理器在镜像复制操作期间访问存储器
公开(公告)号：US07949836B2
公开(公告)日：2011-05-24
申请号：US10865250
申请日：2004-06-10
申请人： Philip Rogers Hillier, III , Joseph Allen Kirscht , Elizabeth A. McGlone
发明人： Philip Rogers Hillier, III , Joseph Allen Kirscht , Elizabeth A. McGlone
IPC分类号： G06F13/00
CPC分类号： G06F11/1666 , G06F11/20 , G06F11/2056
摘要： A memory controller performs a mirror copy function in a way that allows processor accesses to memory to continue during the mirror copy operations that make up the mirror copy function. Data integrity of mirror copy operations is assured by protocols set up in the memory controller. The result is a memory controller that performs a mirror copy function in a way that allows normal processor accesses to memory to be interleaved with mirror copy operations, thereby minimizing the impact on system performance of executing the mirror copy function.
摘要翻译：存储器控制器以允许处理器访问存储器在构成镜像复制功能的镜像复制操作期间继续执行镜像复制功能。通过在存储器控制器中设置的协议来保证镜像复制操作的数据完整性。结果是一个内存控制器，它以允许正常的处理器访问存储器与镜像复制操作交错的方式执行镜像复制功能，从而最小化执行镜像复制功能对系统性能的影响。

7. 发明申请

US20090070648A1 Efficient Scheduling of Background Scrub Commands 失效
标题翻译：后台擦写命令的高效调度
公开(公告)号：US20090070648A1
公开(公告)日：2009-03-12
申请号：US11851487
申请日：2007-09-07
申请人： Brian David Allison , Joseph Allen Kirscht , Elizabeth A. McGlone
发明人： Brian David Allison , Joseph Allen Kirscht , Elizabeth A. McGlone
IPC分类号： G06F11/00
CPC分类号： G06F11/106
摘要： A method and apparatus to efficiently scrub a memory, during a scrub period, of a computer system that has a memory comprising a number of memory elements. Examples of memory elements are memory ranks and banks. A memory rank may further comprise one or more banks. The computer system has a memory controller that receives read requests and write requests from a processor. The memory controller includes a scrub controller configured to output more than one scrub request during a particular request selector cycle. The memory controller includes a request selector that services a read request, a write request, or one of the scrub requests during a request selector cycle.
摘要翻译：一种在具有包括多个存储元件的存储器的计算机系统的擦洗期间有效擦洗存储器的方法和装置。内存元素的例子是内存级别和存储体。存储器级别还可以包括一个或多个存储体。计算机系统具有从处理器接收读取请求和写入请求的存储器控制器。存储器控制器包括擦除控制器，其被配置为在特定请求选择器周期期间输出多于一个擦除请求。存储器控制器包括在请求选择器周期期间服务读取请求，写入请求或擦除请求之一的请求选择器。

8. 发明申请

US20090070647A1 Scheduling of Background Scrub Commands to Reduce High Workload Memory Request Latency 有权
标题翻译：调度后台擦除命令以减少高工作负载内存请求延迟
公开(公告)号：US20090070647A1
公开(公告)日：2009-03-12
申请号：US11851458
申请日：2007-09-07
申请人： Brian David Allison , Joseph Allen Kirscht , Elizabeth A. McGlone
发明人： Brian David Allison , Joseph Allen Kirscht , Elizabeth A. McGlone
IPC分类号： G06F11/00
CPC分类号： G06F11/106
摘要： A method and apparatus to scrub a memory during a scrub period, of a computer system. The computer system has a memory controller that receives read requests and write requests from a processor. The memory controller provides a different priority for scrub requests versus read requests during a period of relatively light memory workload versus a period of relatively heavy workload. The memory controller provides a relatively higher priority for scrub requests near an end of a scrub period if scrub progress is behind an expected scrub progress.
摘要翻译：一种在计算机系统的擦洗期间擦洗存储器的方法和装置。计算机系统具有从处理器接收读取请求和写入请求的存储器控制器。存储器控制器在相对较轻的存储器工作负载期间与相对较重工作负载的时间段内为擦除请求与读请求提供了不同的优先级。如果擦除进度落后于预期的擦洗进度，内存控制器会在擦洗周期结束时提供较高的优先级。

9. 发明授权

US07257686B2 Memory controller and method for scrubbing memory without using explicit atomic operations 失效
标题翻译：内存控制器和擦除内存的方法，而不使用明确的原子操作
公开(公告)号：US07257686B2
公开(公告)日：2007-08-14
申请号：US10860404
申请日：2004-06-03
申请人： Philip Rogers Hillier, III , Joseph Allen Kirscht , Elizabeth A. McGlone
发明人： Philip Rogers Hillier, III , Joseph Allen Kirscht , Elizabeth A. McGlone
IPC分类号： G06F12/06
CPC分类号： G06F11/106
摘要： A memory controller includes scrub circuitry that performs scrub cycles in a way that does not delay processor reads to memory during the scrub cycle. Atomicity of the scrub operation is assured by protocols set up in the memory controller, not by using an explicit atomic read-correct-write operation. The result is a memory controller that efficiently scrubs memory while minimizing the impact of scrub cycles on system performance.
摘要翻译：存储器控制器包括擦洗电路，其以不会在擦洗周期期间将处理器读取延迟到存储器的方式执行擦洗循环。擦除操作的原子性通过在存储器控制器中设置的协议来确保，而不是通过使用明确的原子读取 - 正确写入操作。结果是一个内存控制器，可以有效地擦洗内存，同时最大限度地减少擦洗周期对系统性能的影响。

10. 发明授权

US08245009B2 Simulating memory hot add 有权
标题翻译：模拟内存热添加
公开(公告)号：US08245009B2
公开(公告)日：2012-08-14
申请号：US13162139
申请日：2011-06-16
申请人： Joseph Allen Kirscht , Sumeet Kochar , Barry Alan Kritt , William Bradley Schwartz
发明人： Joseph Allen Kirscht , Sumeet Kochar , Barry Alan Kritt , William Bradley Schwartz
IPC分类号： G06F12/00
CPC分类号： G06F9/4406
摘要： Memory is logically partitioned into two regions. A first region may be a similar size relative to the second region or the first region may be a small subset of the memory. The first region of memory is initialized and an operating system utilizes the first region. A system handler simulates a physical hot add of the second region. After the simulated physical hot add, the operating system may utilize the second region as if it were newly added physical memory and/or may utilize both the first region and second region.
摘要翻译：内存在逻辑上分为两个区域。第一区域可以相对于第二区域具有相似的尺寸，或者第一区域可以是存储器的小子集。存储器的第一区被初始化，并且操作系统利用第一区域。系统处理程序模拟第二区域的物理热添加。在模拟的物理热添加之后，操作系统可以利用第二区域，就好像它是新添加的物理存储器和/或可以利用第一区域和第二区域两者。

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