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1. 发明授权

US07328317B2 Memory controller and method for optimized read/modify/write performance 有权
标题翻译：用于优化读/写/写性能的内存控制器和方法
公开(公告)号：US07328317B2
公开(公告)日：2008-02-05
申请号：US10970400
申请日：2004-10-21
申请人： Philip Rogers Hillier, III , William Paul Hovis , Joseph Allen Kirscht
发明人： Philip Rogers Hillier, III , William Paul Hovis , Joseph Allen Kirscht
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.
摘要翻译：存储器控制器通过将RMW命令分解成不需要一起执行的单独且唯一的读取和写入命令来优化执行读/修改/写入命令，但只需要以正确的顺序执行。最优选的实施例结合读队列和写队列使用控制器中的单独的RMW队列。在其他实施例中，控制器将RMW的读取和写入部分放置在读取和写入队列中，但是写入队列具有与写入队列中的RMW写入命令相关联的依赖指示，以确保控制器维持正确的执行顺序。实施例允许存储器控制器以正确的执行顺序将RMW命令转换为读写命令以保持数据一致性。

2. 发明申请

US20090024808A1 MEMORY CONTROLLER AND METHOD FOR OPTIMIZED READ/MODIFY/WRITE PERFORMANCE 审中-公开
标题翻译：用于优化读/修/写性能的存储器控制器和方法
公开(公告)号：US20090024808A1
公开(公告)日：2009-01-22
申请号：US12136752
申请日：2008-06-10
申请人： Philip Rogers Hillier, III , William Paul Hovis , Joseph Allen Kirscht
发明人： Philip Rogers Hillier, III , William Paul Hovis , Joseph Allen Kirscht
IPC分类号： G06F12/00
CPC分类号： G06F13/1642 , G06F9/3004
摘要： A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.
摘要翻译：存储器控制器通过将RMW命令分解成不需要一起执行的单独且唯一的读取和写入命令来优化执行读/修改/写入命令，但只需要以正确的顺序执行。最优选的实施例结合读队列和写队列使用控制器中的单独的RMW队列。在其他实施例中，控制器将RMW的读取和写入部分放置在读取和写入队列中，但是写入队列具有与写入队列中的RMW写入命令相关联的依赖指示，以确保控制器维持正确的执行顺序。这些实施例允许存储器控制器以正确的执行顺序将RMW命令转换为读写命令以保持数据一致性。

3. 发明申请

US20090024807A1 MEMORY CONTROLLER AND METHOD FOR OPTIMIZED READ/MODIFY/WRITE PERFORMANCE 失效
公开(公告)号：US20090024807A1
公开(公告)日：2009-01-22
申请号：US12136750
申请日：2008-06-10
申请人： Philip Rogers Hillier, III , William Paul Hovis , Joseph Allen Kirscht
发明人： Philip Rogers Hillier, III , William Paul Hovis , Joseph Allen Kirscht
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.

4. 发明授权

US07908443B2 Memory controller and method for optimized read/modify/write performance 失效
标题翻译：用于优化读/写/写性能的内存控制器和方法
公开(公告)号：US07908443B2
公开(公告)日：2011-03-15
申请号：US12136750
申请日：2008-06-10
申请人： Philip Rogers Hillier, III , William Paul Hovis , Joseph Allen Kirscht
发明人： Philip Rogers Hillier, III , William Paul Hovis , Joseph Allen Kirscht
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.
摘要翻译：存储器控制器通过将RMW命令分解成不需要一起执行的单独且唯一的读取和写入命令来优化执行读/修改/写入命令，但只需要以正确的顺序执行。最优选的实施例结合读队列和写队列使用控制器中的单独的RMW队列。在其他实施例中，控制器将RMW的读取和写入部分放置在读取和写入队列中，但是写入队列具有与写入队列中的RMW写入命令相关联的依赖指示，以确保控制器维持正确的执行顺序。实施例允许存储器控制器以正确的执行顺序将RMW命令转换为读写命令以保持数据一致性。

5. 发明授权

US07475202B2 Memory controller and method for optimized read/modify/write performance 有权
标题翻译：用于优化读/写/写性能的内存控制器和方法
公开(公告)号：US07475202B2
公开(公告)日：2009-01-06
申请号：US11779277
申请日：2007-07-18
申请人： Philip Rogers Hillier, III , William Paul Hovis , Joseph Allen Kirscht
发明人： Philip Rogers Hillier, III , William Paul Hovis , Joseph Allen Kirscht
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.
摘要翻译：存储器控制器通过将RMW命令分解成不需要一起执行的单独且唯一的读取和写入命令来优化执行读/修改/写入命令，但只需要以正确的顺序执行。最优选的实施例结合读队列和写队列使用控制器中的单独的RMW队列。在其他实施例中，控制器将RMW的读取和写入部分放置在读取和写入队列中，但是写入队列具有与写入队列中的RMW写入命令相关联的依赖指示，以确保控制器维持正确的执行顺序。实施例允许存储器控制器以正确的执行顺序将RMW命令转换为读写命令以保持数据一致性。

6. 发明授权

US07426672B2 Method for implementing processor bus speculative data completion 失效
标题翻译：实现处理器总线推测数据完成的方法
公开(公告)号：US07426672B2
公开(公告)日：2008-09-16
申请号：US11116624
申请日：2005-04-28
申请人： Wayne Melvin Barrett , Philip Rogers Hillier, III , Joseph Allen Kirscht , Elizabeth A. McGlone
发明人： Wayne Melvin Barrett , Philip Rogers Hillier, III , Joseph Allen Kirscht , Elizabeth A. McGlone
IPC分类号： H03M13/00
CPC分类号： G06F11/10
摘要： A method, and apparatus are provided for implementing processor bus speculative data completion in a computer system. A memory controller in the computer system sends uncorrected data from a memory to a processor bus. The memory controller also applies the uncorrected data to error correcting code (ECC) checking and correcting circuit. When a single bit error (SBE) is detected, corrected data is sent to the processor bus a predefined number of cycles after the uncorrected data.
摘要翻译：提供了一种用于在计算机系统中实现处理器总线推测数据完成的方法和装置。计算机系统中的存储器控制器将未校正的数据从存储器发送到处理器总线。存储器控制器还将未校正的数据应用于纠错码（ECC）校验和校正电路。当检测到单个位错误（SBE）时，校正的数据在未校正的数据之后被发送到处理器总线预定数量的周期。

7. 发明授权

US07328315B2 System and method for managing mirrored memory transactions and error recovery 有权
标题翻译：用于管理镜像内存事务和错误恢复的系统和方法
公开(公告)号：US07328315B2
公开(公告)日：2008-02-05
申请号：US11050291
申请日：2005-02-03
申请人： Philip Rogers Hillier, III , Joseph Allen Kirscht , Elizabeth A. McGlone
发明人： Philip Rogers Hillier, III , Joseph Allen Kirscht , Elizabeth A. McGlone
IPC分类号： G06F12/00
CPC分类号： G06F11/1666 , G06F11/141 , G06F11/20
摘要： In a data processing system having a memory control device including at least two mirrored memory ports, a method, system, and article of manufacture for processing read requests are disclosed herein. In accordance with the method of the present invention, a read request is received on a system interconnect coupling read requestors with memory resources. The received read request is issued only to a specified one of the at least two mirrored memory ports within the memory control device. In response to detecting an unrecoverable error resulting from the read request issued to the one mirrored memory port, the received read request is issued to an alternate of the at least two mirrored memory ports.
摘要翻译：在具有包括至少两个镜像存储器端口的存储器控制装置的数据处理系统中，本文公开了一种用于处理读请求的方法，系统和制品。根据本发明的方法，在将读请求者与存储器资源耦合的系统互连上接收到读请求。所接收的读取请求仅发送到存储器控制设备内的至少两个镜像存储器端口中的指定的一个。响应于检测到从所发送到所述一个镜像存储器端口的读取请求而导致的不可恢复的错误，所接收的读取请求被发布到所述至少两个镜像存储器端口的替代。

8. 发明授权

US07949836B2 Memory controller and method for copying mirrored memory that allows processor accesses to memory during a mirror copy operation 失效
标题翻译：用于复制镜像存储器的内存控制器和方法，允许处理器在镜像复制操作期间访问存储器
公开(公告)号：US07949836B2
公开(公告)日：2011-05-24
申请号：US10865250
申请日：2004-06-10
申请人： Philip Rogers Hillier, III , Joseph Allen Kirscht , Elizabeth A. McGlone
发明人： Philip Rogers Hillier, III , Joseph Allen Kirscht , Elizabeth A. McGlone
IPC分类号： G06F13/00
CPC分类号： G06F11/1666 , G06F11/20 , G06F11/2056
摘要： A memory controller performs a mirror copy function in a way that allows processor accesses to memory to continue during the mirror copy operations that make up the mirror copy function. Data integrity of mirror copy operations is assured by protocols set up in the memory controller. The result is a memory controller that performs a mirror copy function in a way that allows normal processor accesses to memory to be interleaved with mirror copy operations, thereby minimizing the impact on system performance of executing the mirror copy function.
摘要翻译：存储器控制器以允许处理器访问存储器在构成镜像复制功能的镜像复制操作期间继续执行镜像复制功能。通过在存储器控制器中设置的协议来保证镜像复制操作的数据完整性。结果是一个内存控制器，它以允许正常的处理器访问存储器与镜像复制操作交错的方式执行镜像复制功能，从而最小化执行镜像复制功能对系统性能的影响。

9. 发明授权

US07257686B2 Memory controller and method for scrubbing memory without using explicit atomic operations 失效
标题翻译：内存控制器和擦除内存的方法，而不使用明确的原子操作
公开(公告)号：US07257686B2
公开(公告)日：2007-08-14
申请号：US10860404
申请日：2004-06-03
申请人： Philip Rogers Hillier, III , Joseph Allen Kirscht , Elizabeth A. McGlone
发明人： Philip Rogers Hillier, III , Joseph Allen Kirscht , Elizabeth A. McGlone
IPC分类号： G06F12/06
CPC分类号： G06F11/106
摘要： A memory controller includes scrub circuitry that performs scrub cycles in a way that does not delay processor reads to memory during the scrub cycle. Atomicity of the scrub operation is assured by protocols set up in the memory controller, not by using an explicit atomic read-correct-write operation. The result is a memory controller that efficiently scrubs memory while minimizing the impact of scrub cycles on system performance.
摘要翻译：存储器控制器包括擦洗电路，其以不会在擦洗周期期间将处理器读取延迟到存储器的方式执行擦洗循环。擦除操作的原子性通过在存储器控制器中设置的协议来确保，而不是通过使用明确的原子读取 - 正确写入操作。结果是一个内存控制器，可以有效地擦洗内存，同时最大限度地减少擦洗周期对系统性能的影响。

10. 发明授权

US07970980B2 Method and apparatus for accessing memory in a computer system architecture supporting heterogeneous configurations of memory structures 失效
标题翻译：用于在支持存储器结构的异构配置的计算机系统架构中访问存储器的方法和装置
公开(公告)号：US07970980B2
公开(公告)日：2011-06-28
申请号：US11013149
申请日：2004-12-15
申请人： Philip Rogers Hillier, III , Joseph Allen Kirscht , Jamie Randall Kuesel
发明人： Philip Rogers Hillier, III , Joseph Allen Kirscht , Jamie Randall Kuesel
IPC分类号： G06F12/00 , G06F12/06 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0813
摘要： A computer system includes at least one processor, multiple memory modules embodying a main memory, a communications medium for communicating data between the at least one processor and main memory, and memory access control logic which controls the routing of data and access to memory. The communications medium and memory access control logic are designed to accommodate a heterogenous collection of main memory configurations, in which at least one physical parameter is variable for different configurations. The bits of the memory address are mapped to actual memory locations by assigning fixed bit positions to the most critical physical parameters across multiple different module types, and assigning remaining non-contiguous bit positions to less critical physical parameters. In the preferred embodiment, the computer system employs a distributed memory architecture.
摘要翻译：计算机系统包括至少一个处理器，体现主存储器的多个存储器模块，用于在至少一个处理器和主存储器之间传送数据的通信介质，以及控制数据路由和访问存储器的存储器访问控制逻辑。通信介质和存储器访问控制逻辑被设计为适应主存储器配置的异质集合，其中至少一个物理参数对于不同的配置是可变的。通过将固定位位置分配给跨多个不同模块类型的最关键物理参数，并将剩余的非连续位位置分配给不太关键的物理参数，将存储器地址的位映射到实际存储器位置。在优选实施例中，计算机系统采用分布式存储器架构。

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